pub type CacheCtrl2Reg = RegValueT<CacheCtrl2Reg_SPEC>;Expand description
Cache control register 2
Aliased Type§
pub struct CacheCtrl2Reg { /* private fields */ }Implementations§
Source§impl CacheCtrl2Reg
impl CacheCtrl2Reg
Sourcepub fn enable_also_qspiflash_cached(
self,
) -> RegisterFieldBool<12, 1, 0, CacheCtrl2Reg_SPEC, RW>
pub fn enable_also_qspiflash_cached( self, ) -> RegisterFieldBool<12, 1, 0, CacheCtrl2Reg_SPEC, RW>
Enable also the QSPI FLASH cacheability when remapped to OTP (cached). See also the notes at “CACHE_LEN”.
Sourcepub fn enable_also_otp_cached(
self,
) -> RegisterFieldBool<11, 1, 0, CacheCtrl2Reg_SPEC, RW>
pub fn enable_also_otp_cached( self, ) -> RegisterFieldBool<11, 1, 0, CacheCtrl2Reg_SPEC, RW>
Enable also the OTP cacheability when remapped to QSPI FLASH (cached). See also the notes at “CACHE_LEN”.
Sourcepub fn cache_cgen(self) -> RegisterFieldBool<10, 1, 0, CacheCtrl2Reg_SPEC, RW>
pub fn cache_cgen(self) -> RegisterFieldBool<10, 1, 0, CacheCtrl2Reg_SPEC, RW>
0: Cache controller clock gating is not enabled. 1: Cache controller clock gating is enabled (enabling power saving). Note: This bit must be set to ‘0’ (default) when setting the CACHE_FLUSH bit while executing from other than QSPI FLASH cached or OTP cached, e.g. from Booter or SYSRAM.
Sourcepub fn cache_wen(self) -> RegisterFieldBool<9, 1, 0, CacheCtrl2Reg_SPEC, RW>
pub fn cache_wen(self) -> RegisterFieldBool<9, 1, 0, CacheCtrl2Reg_SPEC, RW>
0: Cache Data and TAG memory read only. 1: Cache Data and TAG memory read/write. The TAG and Data memory are only updated by the cache controller. There is no HW protection to prevent unauthorized access by the ARM. Note: When accessing the memory mapped Cache Data and TAG memory (for debugging purposes) only 32 bits access is allowed to the Cache Data memory and only 16 bits access is allowed to the Cache TAG memory.
Sourcepub fn cache_len(
self,
) -> RegisterField<0, 0x1ff, 1, 0, u16, u16, CacheCtrl2Reg_SPEC, RW>
pub fn cache_len( self, ) -> RegisterField<0, 0x1ff, 1, 0, u16, u16, CacheCtrl2Reg_SPEC, RW>
Length of QSPI FLASH cacheable memory. (N+1)*64kbyte. N=1 to 512 (Max of 32 Mbyte). Setting CACHE_LEN=0 disables the cache. Note 1: The OTP memory is completely cacheable (when enabled). Note 2: The max. size/length of QSPI FLASH cacheable memory is 16 Mbyte when also OTP is cached.