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RegisterBlock

da14531::adplldig

Struct RegisterBlock 

Source 
pub struct RegisterBlock {
Show 32 fields
    pub adpll_attr_ctrl_reg: Reg<ADPLL_ATTR_CTRL_REG_SPEC>,
    pub adpll_cn_ctrl_reg: Reg<ADPLL_CN_CTRL_REG_SPEC>,
    pub adpll_fif_ctrl1_reg: Reg<ADPLL_FIF_CTRL1_REG_SPEC>,
    pub adpll_fif_ctrl2_reg: Reg<ADPLL_FIF_CTRL2_REG_SPEC>,
    pub adpll_kdco_cal_ctrl1_reg: Reg<ADPLL_KDCO_CAL_CTRL1_REG_SPEC>,
    pub adpll_kdco_cal_ctrl2_reg: Reg<ADPLL_KDCO_CAL_CTRL2_REG_SPEC>,
    pub adpll_kdtctdc_cal_ctrl1_reg: Reg<ADPLL_KDTCTDC_CAL_CTRL1_REG_SPEC>,
    pub adpll_kdtctdc_cal_ctrl2_reg: Reg<ADPLL_KDTCTDC_CAL_CTRL2_REG_SPEC>,
    pub adpll_dcoamp_cal_ctrl_reg: Reg<ADPLL_DCOAMP_CAL_CTRL_REG_SPEC>,
    pub adpll_txmod_ctrl_reg: Reg<ADPLL_TXMOD_CTRL_REG_SPEC>,
    pub adpll_sdmod_ctrl_reg: Reg<ADPLL_SDMOD_CTRL_REG_SPEC>,
    pub adpll_lf_ctrl1_reg: Reg<ADPLL_LF_CTRL1_REG_SPEC>,
    pub adpll_lf_ctrl2_reg: Reg<ADPLL_LF_CTRL2_REG_SPEC>,
    pub adpll_ana_ctrl_reg: Reg<ADPLL_ANA_CTRL_REG_SPEC>,
    pub adpll_div_ctrl_reg: Reg<ADPLL_DIV_CTRL_REG_SPEC>,
    pub adpll_init_ctrl_reg: Reg<ADPLL_INIT_CTRL_REG_SPEC>,
    pub adpll_fsm_ctrl_reg: Reg<ADPLL_FSM_CTRL_REG_SPEC>,
    pub adpll_mon_ctrl_reg: Reg<ADPLL_MON_CTRL_REG_SPEC>,
    pub adpll_misc_ctrl_reg: Reg<ADPLL_MISC_CTRL_REG_SPEC>,
    pub adpll_overrule_ctrl1_reg: Reg<ADPLL_OVERRULE_CTRL1_REG_SPEC>,
    pub adpll_overrule_ctrl2_reg: Reg<ADPLL_OVERRULE_CTRL2_REG_SPEC>,
    pub adpll_overrule_ctrl3_reg: Reg<ADPLL_OVERRULE_CTRL3_REG_SPEC>,
    pub adpll_rfpt_ctrl_reg: Reg<ADPLL_RFPT_CTRL_REG_SPEC>,
    pub adpll_anatst_ctrl_reg: Reg<ADPLL_ANATST_CTRL_REG_SPEC>,
    pub adpll_acc_ctrl_reg: Reg<ADPLL_ACC_CTRL_REG_SPEC>,
    pub adpll_freqmeas_rd_reg: Reg<ADPLL_FREQMEAS_RD_REG_SPEC>,
    pub adpll_dco_rd_reg: Reg<ADPLL_DCO_RD_REG_SPEC>,
    pub adpll_kdco_rd_reg: Reg<ADPLL_KDCO_RD_REG_SPEC>,
    pub adpll_kdtc_rd_reg: Reg<ADPLL_KDTC_RD_REG_SPEC>,
    pub adpll_tunestate_rd_reg: Reg<ADPLL_TUNESTATE_RD_REG_SPEC>,
    pub adpll_pllfcwdt_rd_reg: Reg<ADPLL_PLLFCWDT_RD_REG_SPEC>,
    pub adpll_anatst_rd_reg: Reg<ADPLL_ANATST_RD_REG_SPEC>,
    /* private fields */

}
Expand description

Register block

Fields§

§adpll_attr_ctrl_reg: Reg<ADPLL_ATTR_CTRL_REG_SPEC>

0x00 -

§adpll_cn_ctrl_reg: Reg<ADPLL_CN_CTRL_REG_SPEC>

0x04 -

§adpll_fif_ctrl1_reg: Reg<ADPLL_FIF_CTRL1_REG_SPEC>

0x08 -

§adpll_fif_ctrl2_reg: Reg<ADPLL_FIF_CTRL2_REG_SPEC>

0x0c -

§adpll_kdco_cal_ctrl1_reg: Reg<ADPLL_KDCO_CAL_CTRL1_REG_SPEC>

0x10 -

§adpll_kdco_cal_ctrl2_reg: Reg<ADPLL_KDCO_CAL_CTRL2_REG_SPEC>

0x14 -

§adpll_kdtctdc_cal_ctrl1_reg: Reg<ADPLL_KDTCTDC_CAL_CTRL1_REG_SPEC>

0x18 -

§adpll_kdtctdc_cal_ctrl2_reg: Reg<ADPLL_KDTCTDC_CAL_CTRL2_REG_SPEC>

0x1c -

§adpll_dcoamp_cal_ctrl_reg: Reg<ADPLL_DCOAMP_CAL_CTRL_REG_SPEC>

0x20 -

§adpll_txmod_ctrl_reg: Reg<ADPLL_TXMOD_CTRL_REG_SPEC>

0x24 -

§adpll_sdmod_ctrl_reg: Reg<ADPLL_SDMOD_CTRL_REG_SPEC>

0x28 -

§adpll_lf_ctrl1_reg: Reg<ADPLL_LF_CTRL1_REG_SPEC>

0x2c -

§adpll_lf_ctrl2_reg: Reg<ADPLL_LF_CTRL2_REG_SPEC>

0x30 -

§adpll_ana_ctrl_reg: Reg<ADPLL_ANA_CTRL_REG_SPEC>

0x34 -

§adpll_div_ctrl_reg: Reg<ADPLL_DIV_CTRL_REG_SPEC>

0x38 -

§adpll_init_ctrl_reg: Reg<ADPLL_INIT_CTRL_REG_SPEC>

0x3c -

§adpll_fsm_ctrl_reg: Reg<ADPLL_FSM_CTRL_REG_SPEC>

0x40 -

§adpll_mon_ctrl_reg: Reg<ADPLL_MON_CTRL_REG_SPEC>

0x44 -

§adpll_misc_ctrl_reg: Reg<ADPLL_MISC_CTRL_REG_SPEC>

0x48 -

§adpll_overrule_ctrl1_reg: Reg<ADPLL_OVERRULE_CTRL1_REG_SPEC>

0x50 -

§adpll_overrule_ctrl2_reg: Reg<ADPLL_OVERRULE_CTRL2_REG_SPEC>

0x54 -

§adpll_overrule_ctrl3_reg: Reg<ADPLL_OVERRULE_CTRL3_REG_SPEC>

0x58 -

§adpll_rfpt_ctrl_reg: Reg<ADPLL_RFPT_CTRL_REG_SPEC>

0x5c -

§adpll_anatst_ctrl_reg: Reg<ADPLL_ANATST_CTRL_REG_SPEC>

0x60 -

§adpll_acc_ctrl_reg: Reg<ADPLL_ACC_CTRL_REG_SPEC>

0x64 -

§adpll_freqmeas_rd_reg: Reg<ADPLL_FREQMEAS_RD_REG_SPEC>

0x7c -

§adpll_dco_rd_reg: Reg<ADPLL_DCO_RD_REG_SPEC>

0x80 -

§adpll_kdco_rd_reg: Reg<ADPLL_KDCO_RD_REG_SPEC>

0x84 -

§adpll_kdtc_rd_reg: Reg<ADPLL_KDTC_RD_REG_SPEC>

0x88 -

§adpll_tunestate_rd_reg: Reg<ADPLL_TUNESTATE_RD_REG_SPEC>

0x8c -

§adpll_pllfcwdt_rd_reg: Reg<ADPLL_PLLFCWDT_RD_REG_SPEC>

0x90 -

§adpll_anatst_rd_reg: Reg<ADPLL_ANATST_RD_REG_SPEC>

0x94 -

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