Timer1CtrlReg

Type Alias Timer1CtrlReg 

Source
pub type Timer1CtrlReg = RegValueT<Timer1CtrlReg_SPEC>;
Expand description

Timer1 control register

Aliased Type§

pub struct Timer1CtrlReg { /* private fields */ }

Implementations§

Source§

impl Timer1CtrlReg

Source

pub fn timer1_clk_en( self, ) -> RegisterFieldBool<16, 1, 0, Timer1CtrlReg_SPEC, RW>

0 = timer1 clock is disabled 1 = timer1 clock is enabled

Source

pub fn timer1_use_sys_clk( self, ) -> RegisterFieldBool<15, 1, 0, Timer1CtrlReg_SPEC, RW>

0 = Timer1 use the clock LP clock 1 = Timer1 use the system clock

Source

pub fn timer1_free_run_mode_en( self, ) -> RegisterFieldBool<14, 1, 0, Timer1CtrlReg_SPEC, RW>

Applicable when timer counts up 1 = timer1 goes to zero when it reaches the max value. 0 = timer1 goes to zero when it reaches the reload value.

Source

pub fn timer1_irq_en( self, ) -> RegisterFieldBool<13, 1, 0, Timer1CtrlReg_SPEC, RW>

0 = timer1 IRQ masked 1 = timer1 IRQ unmasked

Source

pub fn timer1_count_down_en( self, ) -> RegisterFieldBool<12, 1, 0, Timer1CtrlReg_SPEC, RW>

0 = timer1 counts up 1 = timer1 counts down

Source

pub fn timer1_enable( self, ) -> RegisterFieldBool<11, 1, 0, Timer1CtrlReg_SPEC, RW>

0 = Timer1 disabled 1 = Timer1 enabled

Source

pub fn timer1_reload( self, ) -> RegisterField<0, 0x7ff, 1, 0, u16, u16, Timer1CtrlReg_SPEC, RW>

Reload or max value in timer mode. Actual delay is the register value plus synchronization time (3 clock cycles)

Trait Implementations§

Source§

impl Default for Timer1CtrlReg

Source§

fn default() -> Timer1CtrlReg

Returns the “default value” for a type. Read more