Struct CCU 

pub struct CCU { /* private fields */ }

Clock Controller Unit

Implementations

impl CCU

pub const PTR: *const RegisterBlock

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn pll_cpu_ctrl(&self) -> &PLL_CPU_CTRL

0x00 - PLL_CPU Control Register

pub fn pll_ddr_ctrl(&self) -> &PLL_DDR_CTRL

0x10 - PLL_DDR Control Register

pub fn pll_peri_ctrl(&self) -> &PLL_PERI_CTRL

0x20 - PLL_PERI Control Register

pub fn pll_video0_ctrl(&self) -> &PLL_VIDEO0_CTRL

0x40 - PLL_VIDEO0 Control Register

pub fn pll_video1_ctrl(&self) -> &PLL_VIDEO1_CTRL

0x48 - PLL_VIDEO1 Control Register

pub fn pll_ve_ctrl(&self) -> &PLL_VE_CTRL

0x58 - PLL_VE Control Register

pub fn pll_audio0_ctrl(&self) -> &PLL_AUDIO0_CTRL

0x78 - PLL_AUDIO0 Control Register

pub fn pll_audio1_ctrl(&self) -> &PLL_AUDIO1_CTRL

0x80 - PLL_AUDIO1 Control Register

pub fn pll_ddr_pat0_ctrl(&self) -> &PLL_DDR_PAT0_CTRL

0x110 - PLL_DDR Pattern0 Control Register

pub fn pll_ddr_pat1_ctrl(&self) -> &PLL_DDR_PAT1_CTRL

0x114 - PLL_DDR Pattern1 Control Register

pub fn pll_peri_pat0_ctrl(&self) -> &PLL_PERI_PAT0_CTRL

0x120 - PLL_PERI Pattern0 Control Register

pub fn pll_peri_pat1_ctrl(&self) -> &PLL_PERI_PAT1_CTRL

0x124 - PLL_PERI Pattern1 Control Register

pub fn pll_video0_pat0_ctrl(&self) -> &PLL_VIDEO0_PAT0_CTRL

0x140 - PLL_VIDEO0 Pattern0 Control Register

pub fn pll_video0_pat1_ctrl(&self) -> &PLL_VIDEO0_PAT1_CTRL

0x144 - PLL_VIDEO0 Pattern1 Control Register

pub fn pll_video1_pat0_ctrl(&self) -> &PLL_VIDEO1_PAT0_CTRL

0x148 - PLL_VIDEO1 Pattern0 Control Register

pub fn pll_video1_pat1_ctrl(&self) -> &PLL_VIDEO1_PAT1_CTRL

0x14c - PLL_VIDEO1 Pattern1 Control Register

pub fn pll_ve_pat0_ctrl(&self) -> &PLL_VE_PAT0_CTRL

0x158 - PLL_VE Pattern0 Control Register

pub fn pll_ve_pat1_ctrl(&self) -> &PLL_VE_PAT1_CTRL

0x15c - PLL_VE Pattern1 Control Register

pub fn pll_audio0_pat0_ctrl(&self) -> &PLL_AUDIO0_PAT0_CTRL

0x178 - PLL_AUDIO0 Pattern0 Control Register

pub fn pll_audio0_pat1_ctrl(&self) -> &PLL_AUDIO0_PAT1_CTRL

0x17c - PLL_AUDIO0 Pattern1 Control Register

pub fn pll_audio1_pat0_ctrl(&self) -> &PLL_AUDIO1_PAT0_CTRL

0x180 - PLL_AUDIO1 Pattern0 Control Register

pub fn pll_audio1_pat1_ctrl(&self) -> &PLL_AUDIO1_PAT1_CTRL

0x184 - PLL_AUDIO1 Pattern1 Control Register

pub fn pll_cpu_bias(&self) -> &PLL_CPU_BIAS

0x300 - PLL_CPU Bias Register

pub fn pll_ddr_bias(&self) -> &PLL_DDR_BIAS

0x310 - PLL_DDR Bias Register

pub fn pll_peri_bias(&self) -> &PLL_PERI_BIAS

0x320 - PLL_PERI Bias Register

pub fn pll_video0_bias(&self) -> &PLL_VIDEO0_BIAS

0x340 - PLL_VIDEO0 Bias Register

pub fn pll_video1_bias(&self) -> &PLL_VIDEO1_BIAS

0x348 - PLL_VIDEO1 Bias Register

pub fn pll_ve_bias(&self) -> &PLL_VE_BIAS

0x358 - PLL_VE Bias Register

pub fn pll_audio0_bias(&self) -> &PLL_AUDIO0_BIAS

0x378 - PLL_AUDIO0 Bias Register

pub fn pll_audio1_bias(&self) -> &PLL_AUDIO1_BIAS

0x380 - PLL_AUDIO1 Bias Register

pub fn pll_cpu_tun(&self) -> &PLL_CPU_TUN

0x400 - PLL_CPU Tuning Register

pub fn cpu_axi_cfg(&self) -> &CPU_AXI_CFG

0x500 - CPU_AXI Configuration Register

pub fn cpu_gating(&self) -> &CPU_GATING

0x504 - CPU_GATING Configuration Register

pub fn psi_clk(&self) -> &PSI_CLK

0x510 - PSI Clock Register

pub fn apb_clk(&self, n: usize) -> &APB_CLK

0x520..0x528 - APB Clock Register

pub fn apb0_clk(&self) -> &APB_CLK

0x520 - APB Clock Register

pub fn apb1_clk(&self) -> &APB_CLK

0x524 - APB Clock Register

pub fn mbus_clk(&self) -> &MBUS_CLK

0x540 - MBUS Clock Register

pub fn de_clk(&self) -> &DE_CLK

0x600 - DE Clock Register

pub fn de_bgr(&self) -> &DE_BGR

0x60c - DE Bus Gating Reset Register

pub fn di_clk(&self) -> &DI_CLK

0x620 - DI Clock Register

pub fn di_bgr(&self) -> &DI_BGR

0x62c - DI Bus Gating Reset Register

pub fn g2d_clk(&self) -> &G2D_CLK

0x630 - G2D Clock Register

pub fn g2d_bgr(&self) -> &G2D_BGR

0x63c - G2D Bus Gating Reset Register

pub fn ce_clk(&self) -> &CE_CLK

0x680 - CE Clock Register

pub fn ce_bgr(&self) -> &CE_BGR

0x68c - CE Bus Gating Reset Register

pub fn ve_clk(&self) -> &VE_CLK

0x690 - VE Clock Register

pub fn ve_bgr(&self) -> &VE_BGR

0x69c - VE Bus Gating Reset Register

pub fn dma_bgr(&self) -> &DMA_BGR

0x70c - DMA Bus Gating Reset Register

pub fn msgbox_bgr(&self) -> &MSGBOX_BGR

0x71c - MSGBOX Bus Gating Reset Register

pub fn spinlock_bgr(&self) -> &SPINLOCK_BGR

0x72c - SPINLOCK Bus Gating Reset Register

pub fn hstimer_bgr(&self) -> &HSTIMER_BGR

0x73c - HSTIMER Bus Gating Reset Register

pub fn avs_clk(&self) -> &AVS_CLK

0x740 - AVS Clock Register

pub fn dbgsys_bgr(&self) -> &DBGSYS_BGR

0x78c - DBGSYS Bus Gating Reset Register

pub fn pwm_bgr(&self) -> &PWM_BGR

0x7ac - PWM Bus Gating Reset Register

pub fn iommu_bgr(&self) -> &IOMMU_BGR

0x7bc - IOMMU Bus Gating Reset Register

pub fn dram_clk(&self) -> &DRAM_CLK

0x800 - DRAM Clock Register

pub fn mbus_mat_clk_gating(&self) -> &MBUS_MAT_CLK_GATING

0x804 - MBUS Master Clock Gating Register

pub fn dram_bgr(&self) -> &DRAM_BGR

0x80c - DRAM Bus Gating Reset Register

pub fn smhc0_clk(&self) -> &SMHC0_CLK

0x830 - SMHC0 Clock Register

pub fn smhc1_clk(&self) -> &SMHC1_CLK

0x834 - SMHC1 Clock Register

pub fn smhc2_clk(&self) -> &SMHC2_CLK

0x838 - SMHC2 Clock Register

pub fn smhc_bgr(&self) -> &SMHC_BGR

0x84c - SMHC Bus Gating Reset Register

pub fn uart_bgr(&self) -> &UART_BGR

0x90c - UART Bus Gating Reset Register

pub fn twi_bgr(&self) -> &TWI_BGR

0x91c - TWI Bus Gating Reset Register

pub fn spi0_clk(&self) -> &SPI0_CLK

0x940 - SPI0 Clock Register

pub fn spi1_clk(&self) -> &SPI1_CLK

0x944 - SPI1 Clock Register

pub fn spi_bgr(&self) -> &SPI_BGR

0x96c - SPI Bus Gating Reset Register

pub fn emac_25m_clk(&self) -> &EMAC_25M_CLK

0x970 - EMAC_25M Clock Register

pub fn emac_bgr(&self) -> &EMAC_BGR

0x97c - EMAC Bus Gating Reset Register

pub fn irtx_clk(&self) -> &IRTX_CLK

0x9c0 - IRTX Clock Register

pub fn irtx_bgr(&self) -> &IRTX_BGR

0x9cc - IRTX Bus Gating Reset Register

pub fn gpadc_bgr(&self) -> &GPADC_BGR

0x9ec - GPADC Bus Gating Reset Register

pub fn ths_bgr(&self) -> &THS_BGR

0x9fc - THS Bus Gating Reset Register

pub fn i2s_clk(&self, n: usize) -> &I2S_CLK

0xa10..0xa1c - I2S Clock Register

pub fn i2s0_clk(&self) -> &I2S_CLK

0xa10 - I2S Clock Register

pub fn i2s1_clk(&self) -> &I2S_CLK

0xa14 - I2S Clock Register

pub fn i2s2_clk(&self) -> &I2S_CLK

0xa18 - I2S Clock Register

pub fn i2s2_asrc_clk(&self) -> &I2S2_ASRC_CLK

0xa1c - I2S2_ASRC Clock Register

pub fn i2s_bgr(&self) -> &I2S_BGR

0xa20 - I2S Bus Gating Reset Register

pub fn owa_tx_clk(&self) -> &OWA_TX_CLK

0xa24 - OWA_TX Clock Register

pub fn owa_rx_clk(&self) -> &OWA_RX_CLK

0xa28 - OWA_RX Clock Register

pub fn owa_bgr(&self) -> &OWA_BGR

0xa2c - OWA Bus Gating Reset Register

pub fn dmic_clk(&self) -> &DMIC_CLK

0xa40 - DMIC Clock Register

pub fn dmic_bgr(&self) -> &DMIC_BGR

0xa4c - DMIC Bus Gating Reset Register

pub fn audio_codec_dac_clk(&self) -> &AUDIO_CODEC_DAC_CLK

0xa50 - AUDIO_CODEC_DAC Clock Register

pub fn audio_codec_adc_clk(&self) -> &AUDIO_CODEC_ADC_CLK

0xa54 - AUDIO_CODEC_ADC Clock Register

pub fn audio_codec_bgr(&self) -> &AUDIO_CODEC_BGR

0xa5c - AUDIO_CODEC Bus Gating Reset Register

pub fn usb0_clk(&self) -> &USB0_CLK

0xa70 - USB0 Clock Register

pub fn usb1_clk(&self) -> &USB1_CLK

0xa74 - USB1 Clock Register

pub fn usb_bgr(&self) -> &USB_BGR

0xa8c - USB Bus Gating Reset Register

pub fn lradc_bgr(&self) -> &LRADC_BGR

0xa9c - LRADC Bus Gating Reset Register

pub fn dpss_top_bgr(&self) -> &DPSS_TOP_BGR

0xabc - DPSS_TOP Bus Gating Reset Register

pub fn dsi_clk(&self) -> &DSI_CLK

0xb24 - DSI Clock Register

pub fn dsi_bgr(&self) -> &DSI_BGR

0xb4c - DSI Bus Gating Reset Register

pub fn tconlcd_clk(&self) -> &TCONLCD_CLK

0xb60 - TCONLCD Clock Register

pub fn tconlcd_bgr(&self) -> &TCONLCD_BGR

0xb7c - TCONLCD Bus Gating Reset Register

pub fn tcontv_clk(&self) -> &TCONTV_CLK

0xb80 - TCONTV Clock Register

pub fn tcontv_bgr(&self) -> &TCONTV_BGR

0xb9c - TCONTV Bus Gating Reset Register

pub fn lvds_bgr(&self) -> &LVDS_BGR

0xbac - LVDS Bus Gating Reset Register

pub fn tve_clk(&self) -> &TVE_CLK

0xbb0 - TVE Clock Register

pub fn tve_bgr(&self) -> &TVE_BGR

0xbbc - TVE Bus Gating Reset Register

pub fn tvd_clk(&self) -> &TVD_CLK

0xbc0 - TVD Clock Register

pub fn tvd_bgr(&self) -> &TVD_BGR

0xbdc - TVD Bus Gating Reset Register

pub fn ledc_clk(&self) -> &LEDC_CLK

0xbf0 - LEDC Clock Register

pub fn ledc_bgr(&self) -> &LEDC_BGR

0xbfc - LEDC Bus Gating Reset Register

pub fn csi_clk(&self) -> &CSI_CLK

0xc04 - CSI Clock Register

pub fn csi_master_clk(&self) -> &CSI_MASTER_CLK

0xc08 - CSI Master Clock Register

pub fn csi_bgr(&self) -> &CSI_BGR

0xc1c - CSI Bus Gating Reset Register

pub fn tpadc_clk(&self) -> &TPADC_CLK

0xc50 - TPADC Clock Register

pub fn tpadc_bgr(&self) -> &TPADC_BGR

0xc5c - TPADC Bus Gating Reset Register

pub fn dsp_clk(&self) -> &DSP_CLK

0xc70 - DSP Clock Register

pub fn dsp_bgr(&self) -> &DSP_BGR

0xc7c - DSP Bus Gating Reset Register

pub fn riscv_clk(&self) -> &RISCV_CLK

0xd00 - RISC-V Clock Register

pub fn riscv_gating(&self) -> &RISCV_GATING

0xd04 - RISC-V GATING Configuration Register

pub fn riscv_cfg_bgr(&self) -> &RISCV_CFG_BGR

0xd0c - RISC-V_CFG Bus Gating Reset Register

pub fn pll_lock_dbg_ctrl(&self) -> &PLL_LOCK_DBG_CTRL

0xf04 - PLL Lock Debug Control Register

pub fn fre_det_ctrl(&self) -> &FRE_DET_CTRL

0xf08 - Frequency Detect Control Register

pub fn fre_up_lim(&self) -> &FRE_UP_LIM

0xf0c - Frequency Up Limit Register

pub fn fre_down_lim(&self) -> &FRE_DOWN_LIM

0xf10 - Frequency Down Limit Register

pub fn ccu_fan_gate(&self) -> &CCU_FAN_GATE

0xf30 - CCU FANOUT CLOCK GATE Register

pub fn clk27m_fan(&self) -> &CLK27M_FAN

0xf34 - CLK27M FANOUT Register

pub fn pclk_fan(&self) -> &PCLK_FAN

0xf38 - PCLK FANOUT Register

pub fn ccu_fan(&self) -> &CCU_FAN

0xf3c - CCU FANOUT Register

Trait Implementations

impl Debug for CCU

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for CCU

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for CCU