Struct RISCV_CFG 

pub struct RISCV_CFG { /* private fields */ }

RISC-V System Configuration

Implementations

impl RISCV_CFG

pub const PTR: *const RegisterBlock

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn riscv_sta_add0(&self) -> &RISCV_STA_ADD0

0x04 - RISCV Start Address0 Register

pub fn riscv_sta_add1(&self) -> &RISCV_STA_ADD1

0x08 - RISCV Start Address1 Register

pub fn rf1p_cfg(&self) -> &RF1P_CFG

0x10 - RF1P Configuration Register

pub fn rom_cfg(&self) -> &ROM_CFG

0x1c - ROM Configuration Register

pub fn wakeup_en(&self) -> &WAKEUP_EN

0x20 - Wakeup Enable Register

pub fn wakeup_mask(&self, n: usize) -> &WAKEUP_MASK

0x24..0x38 - Wakeup Mask Register

pub fn ts_tmode_sel(&self) -> &TS_TMODE_SEL

0x40 - Timestamp Test Mode Select Register

pub fn sram_addr_twist(&self) -> &SRAM_ADDR_TWIST

0x44 - SRAM Address Twist Register

pub fn work_mode(&self) -> &WORK_MODE

0x48 - Work Mode Register

pub fn retite_pc0(&self) -> &RETITE_PC0

0x50 - Retire PC0 Register

pub fn retite_pc1(&self) -> &RETITE_PC1

0x54 - Retire PC1 Register

pub fn irq_mode(&self, n: usize) -> &IRQ_MODE

0x60..0x74 - IRQ Mode Register

pub fn riscv_axi_pmu_ctrl(&self) -> &RISCV_AXI_PMU_CTRL

0x104 - RISCV AXI PMU Control Register

pub fn riscv_axi_pmu_prd(&self) -> &RISCV_AXI_PMU_PRD

0x108 - RISCV AXI PMU Period Register

pub fn riscv_axi_pmu_lat_rd(&self) -> &RISCV_AXI_PMU_LAT_RD

0x10c - RISCV AXI PMU Read Latency Register

pub fn riscv_axi_pmu_lat_wr(&self) -> &RISCV_AXI_PMU_LAT_WR

0x110 - RISCV AXI PMU Write Latency Register

pub fn riscv_axi_pmu_req_rd(&self) -> &RISCV_AXI_PMU_REQ_RD

0x114 - RISCV AXI PMU Read Request Register

pub fn riscv_axi_pmu_req_wr(&self) -> &RISCV_AXI_PMU_REQ_WR

0x118 - RISCV AXI PMU Write Request Register

pub fn riscv_axi_pmu_bw_rd(&self) -> &RISCV_AXI_PMU_BW_RD

0x11c - RISCV AXI PMU Read Bandwidth Register

pub fn riscv_axi_pmu_bw_wr(&self) -> &RISCV_AXI_PMU_BW_WR

0x120 - RISCV AXI PMU Write Bandwidth Register

Trait Implementations

impl Debug for RISCV_CFG

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for RISCV_CFG

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for RISCV_CFG