RegisterBlock

cyt3bb_a::smif0

Struct RegisterBlock 

Source 
pub struct RegisterBlock {
Show 50 fields
    pub ctl: CTL,
    pub status: STATUS,
    pub int_clock_delay_tap_sel0: INT_CLOCK_DELAY_TAP_SEL0,
    pub int_clock_delay_tap_sel1: INT_CLOCK_DELAY_TAP_SEL1,
    pub dlp: DLP,
    pub dl_status0: DL_STATUS0,
    pub dl_status1: DL_STATUS1,
    pub delay_tap_sel: DELAY_TAP_SEL,
    pub tx_cmd_fifo_status: TX_CMD_FIFO_STATUS,
    pub tx_cmd_fifo_wr: TX_CMD_FIFO_WR,
    pub tx_data_fifo_ctl: TX_DATA_FIFO_CTL,
    pub tx_data_fifo_status: TX_DATA_FIFO_STATUS,
    pub tx_data_fifo_wr1: TX_DATA_FIFO_WR1,
    pub tx_data_fifo_wr2: TX_DATA_FIFO_WR2,
    pub tx_data_fifo_wr4: TX_DATA_FIFO_WR4,
    pub tx_data_fifo_wr1odd: TX_DATA_FIFO_WR1ODD,
    pub rx_data_mmio_fifo_ctl: RX_DATA_MMIO_FIFO_CTL,
    pub rx_data_mmio_fifo_status: RX_DATA_MMIO_FIFO_STATUS,
    pub rx_data_fifo_status: RX_DATA_FIFO_STATUS,
    pub rx_data_mmio_fifo_rd1: RX_DATA_MMIO_FIFO_RD1,
    pub rx_data_mmio_fifo_rd2: RX_DATA_MMIO_FIFO_RD2,
    pub rx_data_mmio_fifo_rd4: RX_DATA_MMIO_FIFO_RD4,
    pub rx_data_mmio_fifo_rd1_silent: RX_DATA_MMIO_FIFO_RD1_SILENT,
    pub slow_ca_ctl: SLOW_CA_CTL,
    pub slow_ca_cmd: SLOW_CA_CMD,
    pub fast_ca_ctl: FAST_CA_CTL,
    pub fast_ca_cmd: FAST_CA_CMD,
    pub crypto_cmd: CRYPTO_CMD,
    pub crypto_input0: CRYPTO_INPUT0,
    pub crypto_input1: CRYPTO_INPUT1,
    pub crypto_input2: CRYPTO_INPUT2,
    pub crypto_input3: CRYPTO_INPUT3,
    pub crypto_key0: CRYPTO_KEY0,
    pub crypto_key1: CRYPTO_KEY1,
    pub crypto_key2: CRYPTO_KEY2,
    pub crypto_key3: CRYPTO_KEY3,
    pub crypto_output0: CRYPTO_OUTPUT0,
    pub crypto_output1: CRYPTO_OUTPUT1,
    pub crypto_output2: CRYPTO_OUTPUT2,
    pub crypto_output3: CRYPTO_OUTPUT3,
    pub crc_cmd: CRC_CMD,
    pub crc_input0: CRC_INPUT0,
    pub crc_input1: CRC_INPUT1,
    pub crc_output: CRC_OUTPUT,
    pub intr: INTR,
    pub intr_set: INTR_SET,
    pub intr_mask: INTR_MASK,
    pub intr_masked: INTR_MASKED,
    pub device0: DEVICE,
    pub device1: DEVICE,
    /* private fields */

}
Expand description

Register block

Fields§

§ctl: CTL

0x00 - Control

§status: STATUS

0x04 - Status

§int_clock_delay_tap_sel0: INT_CLOCK_DELAY_TAP_SEL0

0x10 - Internal Clocking Delay Tap Select Register 0

§int_clock_delay_tap_sel1: INT_CLOCK_DELAY_TAP_SEL1

0x14 - Internal Clocking Delay Tap Select Register 1

§dlp: DLP

0x18 - Data Learning Pattern

§dl_status0: DL_STATUS0

0x20 - Data Learning Status Register 0

§dl_status1: DL_STATUS1

0x24 - Data Learning Status Register 1

§delay_tap_sel: DELAY_TAP_SEL

0x30 - Delay Tap Select Register

§tx_cmd_fifo_status: TX_CMD_FIFO_STATUS

0x44 - Transmitter command FIFO status

§tx_cmd_fifo_wr: TX_CMD_FIFO_WR

0x50 - Transmitter command FIFO write

§tx_data_fifo_ctl: TX_DATA_FIFO_CTL

0x80 - Transmitter data FIFO control

§tx_data_fifo_status: TX_DATA_FIFO_STATUS

0x84 - Transmitter data FIFO status

§tx_data_fifo_wr1: TX_DATA_FIFO_WR1

0x90 - Transmitter data FIFO write

§tx_data_fifo_wr2: TX_DATA_FIFO_WR2

0x94 - Transmitter data FIFO write

§tx_data_fifo_wr4: TX_DATA_FIFO_WR4

0x98 - Transmitter data FIFO write

§tx_data_fifo_wr1odd: TX_DATA_FIFO_WR1ODD

0x9c - Transmitter data FIFO write

§rx_data_mmio_fifo_ctl: RX_DATA_MMIO_FIFO_CTL

0xc0 - Receiver data MMIO FIFO control

§rx_data_mmio_fifo_status: RX_DATA_MMIO_FIFO_STATUS

0xc4 - Receiver data MMIO FIFO status

§rx_data_fifo_status: RX_DATA_FIFO_STATUS

0xc8 - Receiver data FIFO status

§rx_data_mmio_fifo_rd1: RX_DATA_MMIO_FIFO_RD1

0xd0 - Receiver data MMIO FIFO read

§rx_data_mmio_fifo_rd2: RX_DATA_MMIO_FIFO_RD2

0xd4 - Receiver data MMIO FIFO read

§rx_data_mmio_fifo_rd4: RX_DATA_MMIO_FIFO_RD4

0xd8 - Receiver data MMIO FIFO read

§rx_data_mmio_fifo_rd1_silent: RX_DATA_MMIO_FIFO_RD1_SILENT

0xe0 - Receiver data MMIO FIFO silent read

§slow_ca_ctl: SLOW_CA_CTL

0x100 - Slow cache control

§slow_ca_cmd: SLOW_CA_CMD

0x108 - Slow cache command

§fast_ca_ctl: FAST_CA_CTL

0x180 - Fast cache control

§fast_ca_cmd: FAST_CA_CMD

0x188 - Fast cache command

§crypto_cmd: CRYPTO_CMD

0x200 - Cryptography Command

§crypto_input0: CRYPTO_INPUT0

0x220 - Cryptography input 0

§crypto_input1: CRYPTO_INPUT1

0x224 - Cryptography input 1

§crypto_input2: CRYPTO_INPUT2

0x228 - Cryptography input 2

§crypto_input3: CRYPTO_INPUT3

0x22c - Cryptography input 3

§crypto_key0: CRYPTO_KEY0

0x240 - Cryptography key 0

§crypto_key1: CRYPTO_KEY1

0x244 - Cryptography key 1

§crypto_key2: CRYPTO_KEY2

0x248 - Cryptography key 2

§crypto_key3: CRYPTO_KEY3

0x24c - Cryptography key 3

§crypto_output0: CRYPTO_OUTPUT0

0x260 - Cryptography output 0

§crypto_output1: CRYPTO_OUTPUT1

0x264 - Cryptography output 1

§crypto_output2: CRYPTO_OUTPUT2

0x268 - Cryptography output 2

§crypto_output3: CRYPTO_OUTPUT3

0x26c - Cryptography output 3

§crc_cmd: CRC_CMD

0x300 - CRC Command

§crc_input0: CRC_INPUT0

0x320 - CRC input 0

§crc_input1: CRC_INPUT1

0x324 - CRC input 1

§crc_output: CRC_OUTPUT

0x340 - CRC output

§intr: INTR

0x7c0 - Interrupt register

§intr_set: INTR_SET

0x7c4 - Interrupt set register

§intr_mask: INTR_MASK

0x7c8 - Interrupt mask register

§intr_masked: INTR_MASKED

0x7cc - Interrupt masked register

§device0: DEVICE

0x800..0x878 - Device (only used in XIP mode)

§device1: DEVICE

0x880..0x8f8 - Device (only used in XIP mode)

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