pub struct RegisterBlock {Show 21 fields
pub timeout_ctl: Reg<TIMEOUT_CTL_SPEC>,
pub tr_cmd: Reg<TR_CMD_SPEC>,
pub div_cmd: Reg<DIV_CMD_SPEC>,
pub clock_ctl: [Reg<CLOCK_CTL_SPEC>; 256],
pub div_8_ctl: [Reg<DIV_8_CTL_SPEC>; 256],
pub div_16_ctl: [Reg<DIV_16_CTL_SPEC>; 256],
pub div_16_5_ctl: [Reg<DIV_16_5_CTL_SPEC>; 256],
pub div_24_5_ctl: [Reg<DIV_24_5_CTL_SPEC>; 255],
pub ecc_ctl: Reg<ECC_CTL_SPEC>,
pub gr0: GR,
pub gr1: GR,
pub gr2: GR,
pub gr3: GR,
pub gr4: GR,
pub gr5: GR,
pub gr6: GR,
pub gr7: GR,
pub gr8: GR,
pub gr9: GR,
pub tr_gr: [TR_GR; 11],
pub tr_1to1_gr: [TR_1TO1_GR; 9],
/* private fields */
}Expand description
Register block
Fields§
§timeout_ctl: Reg<TIMEOUT_CTL_SPEC>0x200 - Timeout control
tr_cmd: Reg<TR_CMD_SPEC>0x220 - Trigger command
div_cmd: Reg<DIV_CMD_SPEC>0x400 - Divider command
clock_ctl: [Reg<CLOCK_CTL_SPEC>; 256]0xc00..0x1000 - Clock control
div_8_ctl: [Reg<DIV_8_CTL_SPEC>; 256]0x1000..0x1400 - Divider control (for 8.0 divider)
div_16_ctl: [Reg<DIV_16_CTL_SPEC>; 256]0x1400..0x1800 - Divider control (for 16.0 divider)
div_16_5_ctl: [Reg<DIV_16_5_CTL_SPEC>; 256]0x1800..0x1c00 - Divider control (for 16.5 divider)
div_24_5_ctl: [Reg<DIV_24_5_CTL_SPEC>; 255]0x1c00..0x1ffc - Divider control (for 24.5 divider)
ecc_ctl: Reg<ECC_CTL_SPEC>0x2000 - ECC control
gr0: GR0x4000..0x4014 - Peripheral group structure
gr1: GR0x4020..0x4034 - Peripheral group structure
gr2: GR0x4040..0x4054 - Peripheral group structure
gr3: GR0x4060..0x4074 - Peripheral group structure
gr4: GR0x4080..0x4094 - Peripheral group structure
gr5: GR0x40a0..0x40b4 - Peripheral group structure
gr6: GR0x40c0..0x40d4 - Peripheral group structure
gr7: GR0x40e0..0x40f4 - Peripheral group structure
gr8: GR0x4100..0x4114 - Peripheral group structure
gr9: GR0x4120..0x4134 - Peripheral group structure
tr_gr: [TR_GR; 11]0x8000..0xac00 - Trigger group
tr_1to1_gr: [TR_1TO1_GR; 9]0xc000..0xe400 - Trigger 1-to-1 group