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RegisterBlock

cyt2b6::cpuss

Struct RegisterBlock 

Source 
pub struct RegisterBlock {
Show 61 fields
    pub identity: Reg<IDENTITY_SPEC>,
    pub cm4_status: Reg<CM4_STATUS_SPEC>,
    pub cm4_clock_ctl: Reg<CM4_CLOCK_CTL_SPEC>,
    pub cm4_ctl: Reg<CM4_CTL_SPEC>,
    pub cm4_int0_status: Reg<CM4_INT0_STATUS_SPEC>,
    pub cm4_int1_status: Reg<CM4_INT1_STATUS_SPEC>,
    pub cm4_int2_status: Reg<CM4_INT2_STATUS_SPEC>,
    pub cm4_int3_status: Reg<CM4_INT3_STATUS_SPEC>,
    pub cm4_int4_status: Reg<CM4_INT4_STATUS_SPEC>,
    pub cm4_int5_status: Reg<CM4_INT5_STATUS_SPEC>,
    pub cm4_int6_status: Reg<CM4_INT6_STATUS_SPEC>,
    pub cm4_int7_status: Reg<CM4_INT7_STATUS_SPEC>,
    pub cm4_vector_table_base: Reg<CM4_VECTOR_TABLE_BASE_SPEC>,
    pub cm4_nmi_ctl: [Reg<CM4_NMI_CTL_SPEC>; 4],
    pub udb_pwr_ctl: Reg<UDB_PWR_CTL_SPEC>,
    pub udb_pwr_delay_ctl: Reg<UDB_PWR_DELAY_CTL_SPEC>,
    pub cm0_ctl: Reg<CM0_CTL_SPEC>,
    pub cm0_status: Reg<CM0_STATUS_SPEC>,
    pub cm0_clock_ctl: Reg<CM0_CLOCK_CTL_SPEC>,
    pub cm0_int0_status: Reg<CM0_INT0_STATUS_SPEC>,
    pub cm0_int1_status: Reg<CM0_INT1_STATUS_SPEC>,
    pub cm0_int2_status: Reg<CM0_INT2_STATUS_SPEC>,
    pub cm0_int3_status: Reg<CM0_INT3_STATUS_SPEC>,
    pub cm0_int4_status: Reg<CM0_INT4_STATUS_SPEC>,
    pub cm0_int5_status: Reg<CM0_INT5_STATUS_SPEC>,
    pub cm0_int6_status: Reg<CM0_INT6_STATUS_SPEC>,
    pub cm0_int7_status: Reg<CM0_INT7_STATUS_SPEC>,
    pub cm0_vector_table_base: Reg<CM0_VECTOR_TABLE_BASE_SPEC>,
    pub cm0_nmi_ctl: [Reg<CM0_NMI_CTL_SPEC>; 4],
    pub cm4_pwr_ctl: Reg<CM4_PWR_CTL_SPEC>,
    pub cm4_pwr_delay_ctl: Reg<CM4_PWR_DELAY_CTL_SPEC>,
    pub ram0_ctl0: Reg<RAM0_CTL0_SPEC>,
    pub ram0_status: Reg<RAM0_STATUS_SPEC>,
    pub ram0_pwr_macro_ctl: [Reg<RAM0_PWR_MACRO_CTL_SPEC>; 16],
    pub ram1_ctl0: Reg<RAM1_CTL0_SPEC>,
    pub ram1_status: Reg<RAM1_STATUS_SPEC>,
    pub ram1_pwr_ctl: Reg<RAM1_PWR_CTL_SPEC>,
    pub ram2_ctl0: Reg<RAM2_CTL0_SPEC>,
    pub ram2_status: Reg<RAM2_STATUS_SPEC>,
    pub ram2_pwr_ctl: Reg<RAM2_PWR_CTL_SPEC>,
    pub ram_pwr_delay_ctl: Reg<RAM_PWR_DELAY_CTL_SPEC>,
    pub rom_ctl: Reg<ROM_CTL_SPEC>,
    pub ecc_ctl: Reg<ECC_CTL_SPEC>,
    pub product_id: Reg<PRODUCT_ID_SPEC>,
    pub dp_status: Reg<DP_STATUS_SPEC>,
    pub ap_ctl: Reg<AP_CTL_SPEC>,
    pub buff_ctl: Reg<BUFF_CTL_SPEC>,
    pub systick_ctl: Reg<SYSTICK_CTL_SPEC>,
    pub mbist_stat: Reg<MBIST_STAT_SPEC>,
    pub cal_sup_set: Reg<CAL_SUP_SET_SPEC>,
    pub cal_sup_clr: Reg<CAL_SUP_CLR_SPEC>,
    pub cm0_pc_ctl: Reg<CM0_PC_CTL_SPEC>,
    pub cm0_pc0_handler: Reg<CM0_PC0_HANDLER_SPEC>,
    pub cm0_pc1_handler: Reg<CM0_PC1_HANDLER_SPEC>,
    pub cm0_pc2_handler: Reg<CM0_PC2_HANDLER_SPEC>,
    pub cm0_pc3_handler: Reg<CM0_PC3_HANDLER_SPEC>,
    pub protection: Reg<PROTECTION_SPEC>,
    pub trim_rom_ctl: Reg<TRIM_ROM_CTL_SPEC>,
    pub trim_ram_ctl: Reg<TRIM_RAM_CTL_SPEC>,
    pub cm0_system_int_ctl: [Reg<CM0_SYSTEM_INT_CTL_SPEC>; 1023],
    pub cm4_system_int_ctl: [Reg<CM4_SYSTEM_INT_CTL_SPEC>; 1023],
    /* private fields */

}
Expand description

Register block

Fields§

§identity: Reg<IDENTITY_SPEC>

0x00 - Identity

§cm4_status: Reg<CM4_STATUS_SPEC>

0x04 - CM4 status

§cm4_clock_ctl: Reg<CM4_CLOCK_CTL_SPEC>

0x08 - CM4 clock control

§cm4_ctl: Reg<CM4_CTL_SPEC>

0x0c - CM4 control

§cm4_int0_status: Reg<CM4_INT0_STATUS_SPEC>

0x100 - CM4 interrupt 0 status

§cm4_int1_status: Reg<CM4_INT1_STATUS_SPEC>

0x104 - CM4 interrupt 1 status

§cm4_int2_status: Reg<CM4_INT2_STATUS_SPEC>

0x108 - CM4 interrupt 2 status

§cm4_int3_status: Reg<CM4_INT3_STATUS_SPEC>

0x10c - CM4 interrupt 3 status

§cm4_int4_status: Reg<CM4_INT4_STATUS_SPEC>

0x110 - CM4 interrupt 4 status

§cm4_int5_status: Reg<CM4_INT5_STATUS_SPEC>

0x114 - CM4 interrupt 5 status

§cm4_int6_status: Reg<CM4_INT6_STATUS_SPEC>

0x118 - CM4 interrupt 6 status

§cm4_int7_status: Reg<CM4_INT7_STATUS_SPEC>

0x11c - CM4 interrupt 7 status

§cm4_vector_table_base: Reg<CM4_VECTOR_TABLE_BASE_SPEC>

0x200 - CM4 vector table base

§cm4_nmi_ctl: [Reg<CM4_NMI_CTL_SPEC>; 4]

0x240..0x250 - CM4 NMI control

§udb_pwr_ctl: Reg<UDB_PWR_CTL_SPEC>

0x300 - UDB power control

§udb_pwr_delay_ctl: Reg<UDB_PWR_DELAY_CTL_SPEC>

0x304 - UDB power control

§cm0_ctl: Reg<CM0_CTL_SPEC>

0x1000 - CM0+ control

§cm0_status: Reg<CM0_STATUS_SPEC>

0x1004 - CM0+ status

§cm0_clock_ctl: Reg<CM0_CLOCK_CTL_SPEC>

0x1008 - CM0+ clock control

§cm0_int0_status: Reg<CM0_INT0_STATUS_SPEC>

0x1100 - CM0+ interrupt 0 status

§cm0_int1_status: Reg<CM0_INT1_STATUS_SPEC>

0x1104 - CM0+ interrupt 1 status

§cm0_int2_status: Reg<CM0_INT2_STATUS_SPEC>

0x1108 - CM0+ interrupt 2 status

§cm0_int3_status: Reg<CM0_INT3_STATUS_SPEC>

0x110c - CM0+ interrupt 3 status

§cm0_int4_status: Reg<CM0_INT4_STATUS_SPEC>

0x1110 - CM0+ interrupt 4 status

§cm0_int5_status: Reg<CM0_INT5_STATUS_SPEC>

0x1114 - CM0+ interrupt 5 status

§cm0_int6_status: Reg<CM0_INT6_STATUS_SPEC>

0x1118 - CM0+ interrupt 6 status

§cm0_int7_status: Reg<CM0_INT7_STATUS_SPEC>

0x111c - CM0+ interrupt 7 status

§cm0_vector_table_base: Reg<CM0_VECTOR_TABLE_BASE_SPEC>

0x1120 - CM0+ vector table base

§cm0_nmi_ctl: [Reg<CM0_NMI_CTL_SPEC>; 4]

0x1140..0x1150 - CM0+ NMI control

§cm4_pwr_ctl: Reg<CM4_PWR_CTL_SPEC>

0x1200 - CM4 power control

§cm4_pwr_delay_ctl: Reg<CM4_PWR_DELAY_CTL_SPEC>

0x1204 - CM4 power control

§ram0_ctl0: Reg<RAM0_CTL0_SPEC>

0x1300 - RAM 0 control

§ram0_status: Reg<RAM0_STATUS_SPEC>

0x1304 - RAM 0 status

§ram0_pwr_macro_ctl: [Reg<RAM0_PWR_MACRO_CTL_SPEC>; 16]

0x1340..0x1380 - RAM 0 power control

§ram1_ctl0: Reg<RAM1_CTL0_SPEC>

0x1380 - RAM 1 control

§ram1_status: Reg<RAM1_STATUS_SPEC>

0x1384 - RAM 1 status

§ram1_pwr_ctl: Reg<RAM1_PWR_CTL_SPEC>

0x1388 - RAM 1 power control

§ram2_ctl0: Reg<RAM2_CTL0_SPEC>

0x13a0 - RAM 2 control

§ram2_status: Reg<RAM2_STATUS_SPEC>

0x13a4 - RAM 2 status

§ram2_pwr_ctl: Reg<RAM2_PWR_CTL_SPEC>

0x13a8 - RAM 2 power control

§ram_pwr_delay_ctl: Reg<RAM_PWR_DELAY_CTL_SPEC>

0x13c0 - Power up delay used for all SRAM power domains

§rom_ctl: Reg<ROM_CTL_SPEC>

0x13c4 - ROM control

§ecc_ctl: Reg<ECC_CTL_SPEC>

0x13c8 - ECC control

§product_id: Reg<PRODUCT_ID_SPEC>

0x1400 - Product identifier and version (same as CoreSight RomTables)

§dp_status: Reg<DP_STATUS_SPEC>

0x1410 - Debug port status

§ap_ctl: Reg<AP_CTL_SPEC>

0x1414 - Access port control

§buff_ctl: Reg<BUFF_CTL_SPEC>

0x1500 - Buffer control

§systick_ctl: Reg<SYSTICK_CTL_SPEC>

0x1600 - SysTick timer control

§mbist_stat: Reg<MBIST_STAT_SPEC>

0x1704 - Memory BIST status

§cal_sup_set: Reg<CAL_SUP_SET_SPEC>

0x1800 - Calibration support set and read

§cal_sup_clr: Reg<CAL_SUP_CLR_SPEC>

0x1804 - Calibration support clear and reset

§cm0_pc_ctl: Reg<CM0_PC_CTL_SPEC>

0x2000 - CM0+ protection context control

§cm0_pc0_handler: Reg<CM0_PC0_HANDLER_SPEC>

0x2040 - CM0+ protection context 0 handler

§cm0_pc1_handler: Reg<CM0_PC1_HANDLER_SPEC>

0x2044 - CM0+ protection context 1 handler

§cm0_pc2_handler: Reg<CM0_PC2_HANDLER_SPEC>

0x2048 - CM0+ protection context 2 handler

§cm0_pc3_handler: Reg<CM0_PC3_HANDLER_SPEC>

0x204c - CM0+ protection context 3 handler

§protection: Reg<PROTECTION_SPEC>

0x20c4 - Protection status

§trim_rom_ctl: Reg<TRIM_ROM_CTL_SPEC>

0x2100 - ROM trim control

§trim_ram_ctl: Reg<TRIM_RAM_CTL_SPEC>

0x2104 - RAM trim control

§cm0_system_int_ctl: [Reg<CM0_SYSTEM_INT_CTL_SPEC>; 1023]

0x8000..0x8ffc - CM0+ system interrupt control

§cm4_system_int_ctl: [Reg<CM4_SYSTEM_INT_CTL_SPEC>; 1023]

0xa000..0xaffc - CM4 system interrupt control

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