Struct StageRing 

pub struct StageRing {
    pub stages_in_flight: NonZeroUsize,
    pub prefetch: Prefetch,
}

How a walk through shared memory holds its stages: a staged cube’s, or each plane’s own, whatever operands it stages.

One stage in flight fills a stage and contracts it, two cube barriers a step. Two fill the next stage before contracting this one, at twice the shared memory. Where the next stage waits while this one is contracted is prefetch. The tile DSL drives every depth through one schedule each, so neither is a kernel of its own. Who fills the stages is the microkernel’s own question.

Fields

stages_in_flight: NonZeroUsize

Stages the ring holds at once.

prefetch: Prefetch

Where the next stage’s loads wait while this one is contracted: in its own slot, the whole fill running before the contraction of the stage before it (the tile DSL’s Stages::pipelined), or in registers, each unit reading its share of the next stage before the contraction and writing it into its slot after (the tile DSL’s Stages::prefetched).

Implementations

impl StageRing

pub const SINGLE: Self

A stage filled and then contracted.

pub const DOUBLE: Self

The next stage filled while this one is contracted.

pub const TRIPLE: Self

The next two stages filled while this one is contracted: what a fill that runs beside the contraction, the TMA engine’s, keeps ahead of it.

pub const SINGLE_THROUGH_REGISTERS: Self

One stage, the next held in registers while it is contracted.

pub const DOUBLE_THROUGH_REGISTERS: Self

Two stages, the next held in registers while this one is contracted.

pub fn bytes(&self, stage_bytes: usize) -> usize

Bytes of shared memory the ring holds, one stage holding stage_bytes.

pub fn resolve( self, hw: &Hardware, operands: &[StagedOperand], units: usize, ) -> Self

The ring that fills stages of operands on a cube of units units: this one, prefetching into its slots where the tile DSL would refuse to hold the next stage in registers. A refusal is made at expansion, where it is a launch that writes nothing; so every setting runs on every problem, and where it resolves to another’s ring it compiles that one’s launch.

Asked before the operands’ widths are settled, so each operand’s share is its most over every width it could bind at: the powers of two up to the widest line hw reads.

An operand of an element no buffer stores, e2m1 or tf32, is read from words: the register prefetch, which reads a plain source at its own width, does not carry it, and its ring prefetches into its slots.

The tile DSL holds one stage ahead in registers, so a ring of more than two stages would leave the slots past the second idle; and it holds at most Prefetch::fits scalars a unit of every operand’s stage (StagedOperand::most_prefetched).

Trait Implementations

impl Clone for StageRing

fn clone(&self) -> Self

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for StageRing

impl Debug for StageRing

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Display for StageRing

Nothing for a single stage filled in its slot, so the settings that hold one keep their names.

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for StageRing

impl Hash for StageRing

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for StageRing

fn eq(&self, other: &Self) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for StageRing