zisk-pil 1.3.2-alpha

PIL2 definitions for the ZisK zkVM
//! Indexed (compact) Main packing, defined beside the autogenerated `MainTraceRow` without
//! touching `traces.rs`.
//!
//! The `@instr` columns are constant per `pc`, so they live once per instruction in a shared
//! table and a row keeps one index per lane instead. The column list mirrors `MainTraceRow`,
//! lane arrays included, so structural drift is a compile error.

// Fires inside the generated packed accessors, as in `traces.rs`.
#![allow(clippy::int_plus_one)]

use proofman_fields::PrimeField64;
use proofman_macros::indexed_trace_row;

use crate::{MainTraceRow, MainTraceRowOps, MainTraceRowPacked};

indexed_trace_row!(MainTraceRow<F> {
    a: [[u32; 2]; 4],
    b: [[u32; 2]; 4],
    c: [[u32; 2]; 4],
    flag: [bit; 4],
    pc: [u32; 4] @instr,
    a_src_imm: [bit; 4] @instr,
    a_src_mem: [bit; 4] @instr,
    a_offset_imm0: [u64; 4] @instr,
    a_imm1: [u32; 4] @instr,
    is_precompiled: [bit; 4] @instr,
    b_src_imm: [bit; 4] @instr,
    b_src_mem: [bit; 4] @instr,
    b_offset_imm0: [u64; 4] @instr,
    b_imm1: [u32; 4] @instr,
    b_src_ind: [bit; 4] @instr,
    ind_width: [ubit(4); 4] @instr,
    is_external_op: [bit; 4] @instr,
    op: [u8; 4] @instr,
    store_pc: [bit; 4] @instr,
    store_mem: [bit; 4] @instr,
    store_ind: [bit; 4] @instr,
    store_offset: [u64; 4] @instr,
    set_pc: [bit; 4] @instr,
    jmp_offset1: [u64; 4] @instr,
    jmp_offset2: [u64; 4] @instr,
    m32: [bit; 4] @instr,
    addr1: [u32; 4],
    a_reg_prev_mem_step: [ubit(38); 4],
    b_reg_prev_mem_step: [ubit(38); 4],
    store_reg_prev_mem_step: [ubit(38); 4],
    store_reg_prev_value: [[u32; 2]; 4],
    a_src_reg: [bit; 4] @instr,
    b_src_reg: [bit; 4] @instr,
    store_reg: [bit; 4] @instr,
});

// The invocation hardcodes the lane count; pin it so a changed `lanes_x_row` fails here.
const _: [(); crate::MAIN_LANES] =
    [(); MainTraceRowPackedIndexed::<proofman_fields::Goldilocks>::LANES];