1#[doc = "Register `USERCON` reader"]
2pub type R = crate::R<USERCON_SPEC>;
3#[doc = "Register `USERCON` writer"]
4pub type W = crate::W<USERCON_SPEC>;
5#[doc = "Field `DIP` reader - Disable Internal Pipelining"]
6pub type DIP_R = crate::BitReader;
7#[doc = "Field `DIP` writer - Disable Internal Pipelining"]
8pub type DIP_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Address Pins to GPIO Mode\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11#[repr(u16)]
12pub enum ADDIO_A {
13 #[doc = "0: Address Bit is required for addressing memory"]
14 VALUE1 = 0,
15 #[doc = "1: Address Bit is available for GPIO function"]
16 VALUE2 = 1,
17}
18impl From<ADDIO_A> for u16 {
19 #[inline(always)]
20 fn from(variant: ADDIO_A) -> Self {
21 variant as _
22 }
23}
24impl crate::FieldSpec for ADDIO_A {
25 type Ux = u16;
26}
27impl crate::IsEnum for ADDIO_A {}
28#[doc = "Field `ADDIO` reader - Address Pins to GPIO Mode"]
29pub type ADDIO_R = crate::FieldReader<ADDIO_A>;
30impl ADDIO_R {
31 #[doc = "Get enumerated values variant"]
32 #[inline(always)]
33 pub const fn variant(&self) -> Option<ADDIO_A> {
34 match self.bits {
35 0 => Some(ADDIO_A::VALUE1),
36 1 => Some(ADDIO_A::VALUE2),
37 _ => None,
38 }
39 }
40 #[doc = "Address Bit is required for addressing memory"]
41 #[inline(always)]
42 pub fn is_value1(&self) -> bool {
43 *self == ADDIO_A::VALUE1
44 }
45 #[doc = "Address Bit is available for GPIO function"]
46 #[inline(always)]
47 pub fn is_value2(&self) -> bool {
48 *self == ADDIO_A::VALUE2
49 }
50}
51#[doc = "Field `ADDIO` writer - Address Pins to GPIO Mode"]
52pub type ADDIO_W<'a, REG> = crate::FieldWriter<'a, REG, 9, ADDIO_A>;
53impl<'a, REG> ADDIO_W<'a, REG>
54where
55 REG: crate::Writable + crate::RegisterSpec,
56 REG::Ux: From<u16>,
57{
58 #[doc = "Address Bit is required for addressing memory"]
59 #[inline(always)]
60 pub fn value1(self) -> &'a mut crate::W<REG> {
61 self.variant(ADDIO_A::VALUE1)
62 }
63 #[doc = "Address Bit is available for GPIO function"]
64 #[inline(always)]
65 pub fn value2(self) -> &'a mut crate::W<REG> {
66 self.variant(ADDIO_A::VALUE2)
67 }
68}
69#[doc = "ADV Pin to GPIO Mode\n\nValue on reset: 0"]
70#[derive(Clone, Copy, Debug, PartialEq, Eq)]
71pub enum ADVIO_A {
72 #[doc = "0: ADV pin is required for controlling memory"]
73 VALUE1 = 0,
74 #[doc = "1: ADV pin is available for GPIO function"]
75 VALUE2 = 1,
76}
77impl From<ADVIO_A> for bool {
78 #[inline(always)]
79 fn from(variant: ADVIO_A) -> Self {
80 variant as u8 != 0
81 }
82}
83#[doc = "Field `ADVIO` reader - ADV Pin to GPIO Mode"]
84pub type ADVIO_R = crate::BitReader<ADVIO_A>;
85impl ADVIO_R {
86 #[doc = "Get enumerated values variant"]
87 #[inline(always)]
88 pub const fn variant(&self) -> ADVIO_A {
89 match self.bits {
90 false => ADVIO_A::VALUE1,
91 true => ADVIO_A::VALUE2,
92 }
93 }
94 #[doc = "ADV pin is required for controlling memory"]
95 #[inline(always)]
96 pub fn is_value1(&self) -> bool {
97 *self == ADVIO_A::VALUE1
98 }
99 #[doc = "ADV pin is available for GPIO function"]
100 #[inline(always)]
101 pub fn is_value2(&self) -> bool {
102 *self == ADVIO_A::VALUE2
103 }
104}
105#[doc = "Field `ADVIO` writer - ADV Pin to GPIO Mode"]
106pub type ADVIO_W<'a, REG> = crate::BitWriter<'a, REG, ADVIO_A>;
107impl<'a, REG> ADVIO_W<'a, REG>
108where
109 REG: crate::Writable + crate::RegisterSpec,
110{
111 #[doc = "ADV pin is required for controlling memory"]
112 #[inline(always)]
113 pub fn value1(self) -> &'a mut crate::W<REG> {
114 self.variant(ADVIO_A::VALUE1)
115 }
116 #[doc = "ADV pin is available for GPIO function"]
117 #[inline(always)]
118 pub fn value2(self) -> &'a mut crate::W<REG> {
119 self.variant(ADVIO_A::VALUE2)
120 }
121}
122impl R {
123 #[doc = "Bit 0 - Disable Internal Pipelining"]
124 #[inline(always)]
125 pub fn dip(&self) -> DIP_R {
126 DIP_R::new((self.bits & 1) != 0)
127 }
128 #[doc = "Bits 16:24 - Address Pins to GPIO Mode"]
129 #[inline(always)]
130 pub fn addio(&self) -> ADDIO_R {
131 ADDIO_R::new(((self.bits >> 16) & 0x01ff) as u16)
132 }
133 #[doc = "Bit 25 - ADV Pin to GPIO Mode"]
134 #[inline(always)]
135 pub fn advio(&self) -> ADVIO_R {
136 ADVIO_R::new(((self.bits >> 25) & 1) != 0)
137 }
138}
139impl W {
140 #[doc = "Bit 0 - Disable Internal Pipelining"]
141 #[inline(always)]
142 pub fn dip(&mut self) -> DIP_W<USERCON_SPEC> {
143 DIP_W::new(self, 0)
144 }
145 #[doc = "Bits 16:24 - Address Pins to GPIO Mode"]
146 #[inline(always)]
147 pub fn addio(&mut self) -> ADDIO_W<USERCON_SPEC> {
148 ADDIO_W::new(self, 16)
149 }
150 #[doc = "Bit 25 - ADV Pin to GPIO Mode"]
151 #[inline(always)]
152 pub fn advio(&mut self) -> ADVIO_W<USERCON_SPEC> {
153 ADVIO_W::new(self, 25)
154 }
155}
156#[doc = "EBU Test/Control Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`usercon::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usercon::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
157pub struct USERCON_SPEC;
158impl crate::RegisterSpec for USERCON_SPEC {
159 type Ux = u32;
160}
161#[doc = "`read()` method returns [`usercon::R`](R) reader structure"]
162impl crate::Readable for USERCON_SPEC {}
163#[doc = "`write(|w| ..)` method takes [`usercon::W`](W) writer structure"]
164impl crate::Writable for USERCON_SPEC {
165 type Safety = crate::Unsafe;
166 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
167 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
168}
169#[doc = "`reset()` method sets USERCON to value 0"]
170impl crate::Resettable for USERCON_SPEC {
171 const RESET_VALUE: u32 = 0;
172}