xmc4800/scu_interrupt/
srset.rs

1#[doc = "Register `SRSET` writer"]
2pub type W = crate::W<SRSET_SPEC>;
3#[doc = "WDT pre-warning Interrupt Set\n\nValue on reset: 0"]
4#[derive(Clone, Copy, Debug, PartialEq, Eq)]
5pub enum PRWARN_A {
6    #[doc = "0: No effect"]
7    VALUE1 = 0,
8    #[doc = "1: set the status bit"]
9    VALUE2 = 1,
10}
11impl From<PRWARN_A> for bool {
12    #[inline(always)]
13    fn from(variant: PRWARN_A) -> Self {
14        variant as u8 != 0
15    }
16}
17#[doc = "Field `PRWARN` writer - WDT pre-warning Interrupt Set"]
18pub type PRWARN_W<'a, REG> = crate::BitWriter<'a, REG, PRWARN_A>;
19impl<'a, REG> PRWARN_W<'a, REG>
20where
21    REG: crate::Writable + crate::RegisterSpec,
22{
23    #[doc = "No effect"]
24    #[inline(always)]
25    pub fn value1(self) -> &'a mut crate::W<REG> {
26        self.variant(PRWARN_A::VALUE1)
27    }
28    #[doc = "set the status bit"]
29    #[inline(always)]
30    pub fn value2(self) -> &'a mut crate::W<REG> {
31        self.variant(PRWARN_A::VALUE2)
32    }
33}
34#[doc = "RTC Periodic Interrupt Set\n\nValue on reset: 0"]
35#[derive(Clone, Copy, Debug, PartialEq, Eq)]
36pub enum PI_A {
37    #[doc = "0: No effect"]
38    VALUE1 = 0,
39    #[doc = "1: set the status bit"]
40    VALUE2 = 1,
41}
42impl From<PI_A> for bool {
43    #[inline(always)]
44    fn from(variant: PI_A) -> Self {
45        variant as u8 != 0
46    }
47}
48#[doc = "Field `PI` writer - RTC Periodic Interrupt Set"]
49pub type PI_W<'a, REG> = crate::BitWriter<'a, REG, PI_A>;
50impl<'a, REG> PI_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    #[doc = "No effect"]
55    #[inline(always)]
56    pub fn value1(self) -> &'a mut crate::W<REG> {
57        self.variant(PI_A::VALUE1)
58    }
59    #[doc = "set the status bit"]
60    #[inline(always)]
61    pub fn value2(self) -> &'a mut crate::W<REG> {
62        self.variant(PI_A::VALUE2)
63    }
64}
65#[doc = "RTC Alarm Interrupt Set\n\nValue on reset: 0"]
66#[derive(Clone, Copy, Debug, PartialEq, Eq)]
67pub enum AI_A {
68    #[doc = "0: No effect"]
69    VALUE1 = 0,
70    #[doc = "1: set the status bit"]
71    VALUE2 = 1,
72}
73impl From<AI_A> for bool {
74    #[inline(always)]
75    fn from(variant: AI_A) -> Self {
76        variant as u8 != 0
77    }
78}
79#[doc = "Field `AI` writer - RTC Alarm Interrupt Set"]
80pub type AI_W<'a, REG> = crate::BitWriter<'a, REG, AI_A>;
81impl<'a, REG> AI_W<'a, REG>
82where
83    REG: crate::Writable + crate::RegisterSpec,
84{
85    #[doc = "No effect"]
86    #[inline(always)]
87    pub fn value1(self) -> &'a mut crate::W<REG> {
88        self.variant(AI_A::VALUE1)
89    }
90    #[doc = "set the status bit"]
91    #[inline(always)]
92    pub fn value2(self) -> &'a mut crate::W<REG> {
93        self.variant(AI_A::VALUE2)
94    }
95}
96#[doc = "DLR Request Overrun Interrupt Set\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98pub enum DLROVR_A {
99    #[doc = "0: No effect"]
100    VALUE1 = 0,
101    #[doc = "1: set the status bit"]
102    VALUE2 = 1,
103}
104impl From<DLROVR_A> for bool {
105    #[inline(always)]
106    fn from(variant: DLROVR_A) -> Self {
107        variant as u8 != 0
108    }
109}
110#[doc = "Field `DLROVR` writer - DLR Request Overrun Interrupt Set"]
111pub type DLROVR_W<'a, REG> = crate::BitWriter<'a, REG, DLROVR_A>;
112impl<'a, REG> DLROVR_W<'a, REG>
113where
114    REG: crate::Writable + crate::RegisterSpec,
115{
116    #[doc = "No effect"]
117    #[inline(always)]
118    pub fn value1(self) -> &'a mut crate::W<REG> {
119        self.variant(DLROVR_A::VALUE1)
120    }
121    #[doc = "set the status bit"]
122    #[inline(always)]
123    pub fn value2(self) -> &'a mut crate::W<REG> {
124        self.variant(DLROVR_A::VALUE2)
125    }
126}
127#[doc = "HDCRCLR Mirror Register Update Set\n\nValue on reset: 0"]
128#[derive(Clone, Copy, Debug, PartialEq, Eq)]
129pub enum HDCRCLR_A {
130    #[doc = "0: No effect"]
131    VALUE1 = 0,
132    #[doc = "1: set the status bit"]
133    VALUE2 = 1,
134}
135impl From<HDCRCLR_A> for bool {
136    #[inline(always)]
137    fn from(variant: HDCRCLR_A) -> Self {
138        variant as u8 != 0
139    }
140}
141#[doc = "Field `HDCRCLR` writer - HDCRCLR Mirror Register Update Set"]
142pub type HDCRCLR_W<'a, REG> = crate::BitWriter<'a, REG, HDCRCLR_A>;
143impl<'a, REG> HDCRCLR_W<'a, REG>
144where
145    REG: crate::Writable + crate::RegisterSpec,
146{
147    #[doc = "No effect"]
148    #[inline(always)]
149    pub fn value1(self) -> &'a mut crate::W<REG> {
150        self.variant(HDCRCLR_A::VALUE1)
151    }
152    #[doc = "set the status bit"]
153    #[inline(always)]
154    pub fn value2(self) -> &'a mut crate::W<REG> {
155        self.variant(HDCRCLR_A::VALUE2)
156    }
157}
158#[doc = "HDCRSET Mirror Register Update Set\n\nValue on reset: 0"]
159#[derive(Clone, Copy, Debug, PartialEq, Eq)]
160pub enum HDCRSET_A {
161    #[doc = "0: No effect"]
162    VALUE1 = 0,
163    #[doc = "1: set the status bit"]
164    VALUE2 = 1,
165}
166impl From<HDCRSET_A> for bool {
167    #[inline(always)]
168    fn from(variant: HDCRSET_A) -> Self {
169        variant as u8 != 0
170    }
171}
172#[doc = "Field `HDCRSET` writer - HDCRSET Mirror Register Update Set"]
173pub type HDCRSET_W<'a, REG> = crate::BitWriter<'a, REG, HDCRSET_A>;
174impl<'a, REG> HDCRSET_W<'a, REG>
175where
176    REG: crate::Writable + crate::RegisterSpec,
177{
178    #[doc = "No effect"]
179    #[inline(always)]
180    pub fn value1(self) -> &'a mut crate::W<REG> {
181        self.variant(HDCRSET_A::VALUE1)
182    }
183    #[doc = "set the status bit"]
184    #[inline(always)]
185    pub fn value2(self) -> &'a mut crate::W<REG> {
186        self.variant(HDCRSET_A::VALUE2)
187    }
188}
189#[doc = "HDCR Mirror Register Update Set\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum HDCR_A {
192    #[doc = "0: No effect"]
193    VALUE1 = 0,
194    #[doc = "1: set the status bit"]
195    VALUE2 = 1,
196}
197impl From<HDCR_A> for bool {
198    #[inline(always)]
199    fn from(variant: HDCR_A) -> Self {
200        variant as u8 != 0
201    }
202}
203#[doc = "Field `HDCR` writer - HDCR Mirror Register Update Set"]
204pub type HDCR_W<'a, REG> = crate::BitWriter<'a, REG, HDCR_A>;
205impl<'a, REG> HDCR_W<'a, REG>
206where
207    REG: crate::Writable + crate::RegisterSpec,
208{
209    #[doc = "No effect"]
210    #[inline(always)]
211    pub fn value1(self) -> &'a mut crate::W<REG> {
212        self.variant(HDCR_A::VALUE1)
213    }
214    #[doc = "set the status bit"]
215    #[inline(always)]
216    pub fn value2(self) -> &'a mut crate::W<REG> {
217        self.variant(HDCR_A::VALUE2)
218    }
219}
220#[doc = "OSCSICTRL Mirror Register Update Set\n\nValue on reset: 0"]
221#[derive(Clone, Copy, Debug, PartialEq, Eq)]
222pub enum OSCSICTRL_A {
223    #[doc = "0: No effect"]
224    VALUE1 = 0,
225    #[doc = "1: set the status bit"]
226    VALUE2 = 1,
227}
228impl From<OSCSICTRL_A> for bool {
229    #[inline(always)]
230    fn from(variant: OSCSICTRL_A) -> Self {
231        variant as u8 != 0
232    }
233}
234#[doc = "Field `OSCSICTRL` writer - OSCSICTRL Mirror Register Update Set"]
235pub type OSCSICTRL_W<'a, REG> = crate::BitWriter<'a, REG, OSCSICTRL_A>;
236impl<'a, REG> OSCSICTRL_W<'a, REG>
237where
238    REG: crate::Writable + crate::RegisterSpec,
239{
240    #[doc = "No effect"]
241    #[inline(always)]
242    pub fn value1(self) -> &'a mut crate::W<REG> {
243        self.variant(OSCSICTRL_A::VALUE1)
244    }
245    #[doc = "set the status bit"]
246    #[inline(always)]
247    pub fn value2(self) -> &'a mut crate::W<REG> {
248        self.variant(OSCSICTRL_A::VALUE2)
249    }
250}
251#[doc = "OSCULCTRL Mirror Register Update Set\n\nValue on reset: 0"]
252#[derive(Clone, Copy, Debug, PartialEq, Eq)]
253pub enum OSCULCTRL_A {
254    #[doc = "0: No effect"]
255    VALUE1 = 0,
256    #[doc = "1: set the status bit"]
257    VALUE2 = 1,
258}
259impl From<OSCULCTRL_A> for bool {
260    #[inline(always)]
261    fn from(variant: OSCULCTRL_A) -> Self {
262        variant as u8 != 0
263    }
264}
265#[doc = "Field `OSCULCTRL` writer - OSCULCTRL Mirror Register Update Set"]
266pub type OSCULCTRL_W<'a, REG> = crate::BitWriter<'a, REG, OSCULCTRL_A>;
267impl<'a, REG> OSCULCTRL_W<'a, REG>
268where
269    REG: crate::Writable + crate::RegisterSpec,
270{
271    #[doc = "No effect"]
272    #[inline(always)]
273    pub fn value1(self) -> &'a mut crate::W<REG> {
274        self.variant(OSCULCTRL_A::VALUE1)
275    }
276    #[doc = "set the status bit"]
277    #[inline(always)]
278    pub fn value2(self) -> &'a mut crate::W<REG> {
279        self.variant(OSCULCTRL_A::VALUE2)
280    }
281}
282#[doc = "RTC CTR Mirror Register Update Set\n\nValue on reset: 0"]
283#[derive(Clone, Copy, Debug, PartialEq, Eq)]
284pub enum RTC_CTR_A {
285    #[doc = "0: No effect"]
286    VALUE1 = 0,
287    #[doc = "1: set the status bit"]
288    VALUE2 = 1,
289}
290impl From<RTC_CTR_A> for bool {
291    #[inline(always)]
292    fn from(variant: RTC_CTR_A) -> Self {
293        variant as u8 != 0
294    }
295}
296#[doc = "Field `RTC_CTR` writer - RTC CTR Mirror Register Update Set"]
297pub type RTC_CTR_W<'a, REG> = crate::BitWriter<'a, REG, RTC_CTR_A>;
298impl<'a, REG> RTC_CTR_W<'a, REG>
299where
300    REG: crate::Writable + crate::RegisterSpec,
301{
302    #[doc = "No effect"]
303    #[inline(always)]
304    pub fn value1(self) -> &'a mut crate::W<REG> {
305        self.variant(RTC_CTR_A::VALUE1)
306    }
307    #[doc = "set the status bit"]
308    #[inline(always)]
309    pub fn value2(self) -> &'a mut crate::W<REG> {
310        self.variant(RTC_CTR_A::VALUE2)
311    }
312}
313#[doc = "RTC ATIM0 Mirror Register Update Set\n\nValue on reset: 0"]
314#[derive(Clone, Copy, Debug, PartialEq, Eq)]
315pub enum RTC_ATIM0_A {
316    #[doc = "0: No effect"]
317    VALUE1 = 0,
318    #[doc = "1: set the status bit"]
319    VALUE2 = 1,
320}
321impl From<RTC_ATIM0_A> for bool {
322    #[inline(always)]
323    fn from(variant: RTC_ATIM0_A) -> Self {
324        variant as u8 != 0
325    }
326}
327#[doc = "Field `RTC_ATIM0` writer - RTC ATIM0 Mirror Register Update Set"]
328pub type RTC_ATIM0_W<'a, REG> = crate::BitWriter<'a, REG, RTC_ATIM0_A>;
329impl<'a, REG> RTC_ATIM0_W<'a, REG>
330where
331    REG: crate::Writable + crate::RegisterSpec,
332{
333    #[doc = "No effect"]
334    #[inline(always)]
335    pub fn value1(self) -> &'a mut crate::W<REG> {
336        self.variant(RTC_ATIM0_A::VALUE1)
337    }
338    #[doc = "set the status bit"]
339    #[inline(always)]
340    pub fn value2(self) -> &'a mut crate::W<REG> {
341        self.variant(RTC_ATIM0_A::VALUE2)
342    }
343}
344#[doc = "RTC ATIM1 Mirror Register Update Set\n\nValue on reset: 0"]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum RTC_ATIM1_A {
347    #[doc = "0: No effect"]
348    VALUE1 = 0,
349    #[doc = "1: set the status bit"]
350    VALUE2 = 1,
351}
352impl From<RTC_ATIM1_A> for bool {
353    #[inline(always)]
354    fn from(variant: RTC_ATIM1_A) -> Self {
355        variant as u8 != 0
356    }
357}
358#[doc = "Field `RTC_ATIM1` writer - RTC ATIM1 Mirror Register Update Set"]
359pub type RTC_ATIM1_W<'a, REG> = crate::BitWriter<'a, REG, RTC_ATIM1_A>;
360impl<'a, REG> RTC_ATIM1_W<'a, REG>
361where
362    REG: crate::Writable + crate::RegisterSpec,
363{
364    #[doc = "No effect"]
365    #[inline(always)]
366    pub fn value1(self) -> &'a mut crate::W<REG> {
367        self.variant(RTC_ATIM1_A::VALUE1)
368    }
369    #[doc = "set the status bit"]
370    #[inline(always)]
371    pub fn value2(self) -> &'a mut crate::W<REG> {
372        self.variant(RTC_ATIM1_A::VALUE2)
373    }
374}
375#[doc = "RTC TIM0 Mirror Register Update Set\n\nValue on reset: 0"]
376#[derive(Clone, Copy, Debug, PartialEq, Eq)]
377pub enum RTC_TIM0_A {
378    #[doc = "0: No effect"]
379    VALUE1 = 0,
380    #[doc = "1: set the status bit"]
381    VALUE2 = 1,
382}
383impl From<RTC_TIM0_A> for bool {
384    #[inline(always)]
385    fn from(variant: RTC_TIM0_A) -> Self {
386        variant as u8 != 0
387    }
388}
389#[doc = "Field `RTC_TIM0` writer - RTC TIM0 Mirror Register Update Set"]
390pub type RTC_TIM0_W<'a, REG> = crate::BitWriter<'a, REG, RTC_TIM0_A>;
391impl<'a, REG> RTC_TIM0_W<'a, REG>
392where
393    REG: crate::Writable + crate::RegisterSpec,
394{
395    #[doc = "No effect"]
396    #[inline(always)]
397    pub fn value1(self) -> &'a mut crate::W<REG> {
398        self.variant(RTC_TIM0_A::VALUE1)
399    }
400    #[doc = "set the status bit"]
401    #[inline(always)]
402    pub fn value2(self) -> &'a mut crate::W<REG> {
403        self.variant(RTC_TIM0_A::VALUE2)
404    }
405}
406#[doc = "RTC TIM1 Mirror Register Update Set\n\nValue on reset: 0"]
407#[derive(Clone, Copy, Debug, PartialEq, Eq)]
408pub enum RTC_TIM1_A {
409    #[doc = "0: No effect"]
410    VALUE1 = 0,
411    #[doc = "1: set the status bit"]
412    VALUE2 = 1,
413}
414impl From<RTC_TIM1_A> for bool {
415    #[inline(always)]
416    fn from(variant: RTC_TIM1_A) -> Self {
417        variant as u8 != 0
418    }
419}
420#[doc = "Field `RTC_TIM1` writer - RTC TIM1 Mirror Register Update Set"]
421pub type RTC_TIM1_W<'a, REG> = crate::BitWriter<'a, REG, RTC_TIM1_A>;
422impl<'a, REG> RTC_TIM1_W<'a, REG>
423where
424    REG: crate::Writable + crate::RegisterSpec,
425{
426    #[doc = "No effect"]
427    #[inline(always)]
428    pub fn value1(self) -> &'a mut crate::W<REG> {
429        self.variant(RTC_TIM1_A::VALUE1)
430    }
431    #[doc = "set the status bit"]
432    #[inline(always)]
433    pub fn value2(self) -> &'a mut crate::W<REG> {
434        self.variant(RTC_TIM1_A::VALUE2)
435    }
436}
437#[doc = "Retention Memory Mirror Register Update Set\n\nValue on reset: 0"]
438#[derive(Clone, Copy, Debug, PartialEq, Eq)]
439pub enum RMX_A {
440    #[doc = "0: No effect"]
441    VALUE1 = 0,
442    #[doc = "1: set the status bit"]
443    VALUE2 = 1,
444}
445impl From<RMX_A> for bool {
446    #[inline(always)]
447    fn from(variant: RMX_A) -> Self {
448        variant as u8 != 0
449    }
450}
451#[doc = "Field `RMX` writer - Retention Memory Mirror Register Update Set"]
452pub type RMX_W<'a, REG> = crate::BitWriter<'a, REG, RMX_A>;
453impl<'a, REG> RMX_W<'a, REG>
454where
455    REG: crate::Writable + crate::RegisterSpec,
456{
457    #[doc = "No effect"]
458    #[inline(always)]
459    pub fn value1(self) -> &'a mut crate::W<REG> {
460        self.variant(RMX_A::VALUE1)
461    }
462    #[doc = "set the status bit"]
463    #[inline(always)]
464    pub fn value2(self) -> &'a mut crate::W<REG> {
465        self.variant(RMX_A::VALUE2)
466    }
467}
468impl W {
469    #[doc = "Bit 0 - WDT pre-warning Interrupt Set"]
470    #[inline(always)]
471    pub fn prwarn(&mut self) -> PRWARN_W<SRSET_SPEC> {
472        PRWARN_W::new(self, 0)
473    }
474    #[doc = "Bit 1 - RTC Periodic Interrupt Set"]
475    #[inline(always)]
476    pub fn pi(&mut self) -> PI_W<SRSET_SPEC> {
477        PI_W::new(self, 1)
478    }
479    #[doc = "Bit 2 - RTC Alarm Interrupt Set"]
480    #[inline(always)]
481    pub fn ai(&mut self) -> AI_W<SRSET_SPEC> {
482        AI_W::new(self, 2)
483    }
484    #[doc = "Bit 3 - DLR Request Overrun Interrupt Set"]
485    #[inline(always)]
486    pub fn dlrovr(&mut self) -> DLROVR_W<SRSET_SPEC> {
487        DLROVR_W::new(self, 3)
488    }
489    #[doc = "Bit 17 - HDCRCLR Mirror Register Update Set"]
490    #[inline(always)]
491    pub fn hdcrclr(&mut self) -> HDCRCLR_W<SRSET_SPEC> {
492        HDCRCLR_W::new(self, 17)
493    }
494    #[doc = "Bit 18 - HDCRSET Mirror Register Update Set"]
495    #[inline(always)]
496    pub fn hdcrset(&mut self) -> HDCRSET_W<SRSET_SPEC> {
497        HDCRSET_W::new(self, 18)
498    }
499    #[doc = "Bit 19 - HDCR Mirror Register Update Set"]
500    #[inline(always)]
501    pub fn hdcr(&mut self) -> HDCR_W<SRSET_SPEC> {
502        HDCR_W::new(self, 19)
503    }
504    #[doc = "Bit 21 - OSCSICTRL Mirror Register Update Set"]
505    #[inline(always)]
506    pub fn oscsictrl(&mut self) -> OSCSICTRL_W<SRSET_SPEC> {
507        OSCSICTRL_W::new(self, 21)
508    }
509    #[doc = "Bit 23 - OSCULCTRL Mirror Register Update Set"]
510    #[inline(always)]
511    pub fn osculctrl(&mut self) -> OSCULCTRL_W<SRSET_SPEC> {
512        OSCULCTRL_W::new(self, 23)
513    }
514    #[doc = "Bit 24 - RTC CTR Mirror Register Update Set"]
515    #[inline(always)]
516    pub fn rtc_ctr(&mut self) -> RTC_CTR_W<SRSET_SPEC> {
517        RTC_CTR_W::new(self, 24)
518    }
519    #[doc = "Bit 25 - RTC ATIM0 Mirror Register Update Set"]
520    #[inline(always)]
521    pub fn rtc_atim0(&mut self) -> RTC_ATIM0_W<SRSET_SPEC> {
522        RTC_ATIM0_W::new(self, 25)
523    }
524    #[doc = "Bit 26 - RTC ATIM1 Mirror Register Update Set"]
525    #[inline(always)]
526    pub fn rtc_atim1(&mut self) -> RTC_ATIM1_W<SRSET_SPEC> {
527        RTC_ATIM1_W::new(self, 26)
528    }
529    #[doc = "Bit 27 - RTC TIM0 Mirror Register Update Set"]
530    #[inline(always)]
531    pub fn rtc_tim0(&mut self) -> RTC_TIM0_W<SRSET_SPEC> {
532        RTC_TIM0_W::new(self, 27)
533    }
534    #[doc = "Bit 28 - RTC TIM1 Mirror Register Update Set"]
535    #[inline(always)]
536    pub fn rtc_tim1(&mut self) -> RTC_TIM1_W<SRSET_SPEC> {
537        RTC_TIM1_W::new(self, 28)
538    }
539    #[doc = "Bit 29 - Retention Memory Mirror Register Update Set"]
540    #[inline(always)]
541    pub fn rmx(&mut self) -> RMX_W<SRSET_SPEC> {
542        RMX_W::new(self, 29)
543    }
544}
545#[doc = "SCU Service Request Set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`srset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
546pub struct SRSET_SPEC;
547impl crate::RegisterSpec for SRSET_SPEC {
548    type Ux = u32;
549}
550#[doc = "`write(|w| ..)` method takes [`srset::W`](W) writer structure"]
551impl crate::Writable for SRSET_SPEC {
552    type Safety = crate::Unsafe;
553    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
554    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
555}
556#[doc = "`reset()` method sets SRSET to value 0"]
557impl crate::Resettable for SRSET_SPEC {
558    const RESET_VALUE: u32 = 0;
559}
xmc4800/scu_interrupt/srset.rs

xmc4800/scu_interrupt/
srset.rs
