xmc4800/port6/
omr.rs

1#[doc = "Register `OMR` writer"]
2pub type W = crate::W<OMR_SPEC>;
3#[doc = "Field `PS0` writer - Port n Set Bit 0"]
4pub type PS0_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `PS1` writer - Port n Set Bit 1"]
6pub type PS1_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `PS2` writer - Port n Set Bit 2"]
8pub type PS2_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PS3` writer - Port n Set Bit 3"]
10pub type PS3_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `PS4` writer - Port n Set Bit 4"]
12pub type PS4_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PS5` writer - Port n Set Bit 5"]
14pub type PS5_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `PS6` writer - Port n Set Bit 6"]
16pub type PS6_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PS7` writer - Port n Set Bit 7"]
18pub type PS7_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `PS8` writer - Port n Set Bit 8"]
20pub type PS8_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `PS9` writer - Port n Set Bit 9"]
22pub type PS9_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `PS10` writer - Port n Set Bit 10"]
24pub type PS10_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PS11` writer - Port n Set Bit 11"]
26pub type PS11_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `PS12` writer - Port n Set Bit 12"]
28pub type PS12_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `PS13` writer - Port n Set Bit 13"]
30pub type PS13_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `PS14` writer - Port n Set Bit 14"]
32pub type PS14_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `PS15` writer - Port n Set Bit 15"]
34pub type PS15_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `PR0` writer - Port n Reset Bit 0"]
36pub type PR0_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `PR1` writer - Port n Reset Bit 1"]
38pub type PR1_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `PR2` writer - Port n Reset Bit 2"]
40pub type PR2_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `PR3` writer - Port n Reset Bit 3"]
42pub type PR3_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `PR4` writer - Port n Reset Bit 4"]
44pub type PR4_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `PR5` writer - Port n Reset Bit 5"]
46pub type PR5_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `PR6` writer - Port n Reset Bit 6"]
48pub type PR6_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `PR7` writer - Port n Reset Bit 7"]
50pub type PR7_W<'a, REG> = crate::BitWriter<'a, REG>;
51#[doc = "Field `PR8` writer - Port n Reset Bit 8"]
52pub type PR8_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `PR9` writer - Port n Reset Bit 9"]
54pub type PR9_W<'a, REG> = crate::BitWriter<'a, REG>;
55#[doc = "Field `PR10` writer - Port n Reset Bit 10"]
56pub type PR10_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `PR11` writer - Port n Reset Bit 11"]
58pub type PR11_W<'a, REG> = crate::BitWriter<'a, REG>;
59#[doc = "Field `PR12` writer - Port n Reset Bit 12"]
60pub type PR12_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `PR13` writer - Port n Reset Bit 13"]
62pub type PR13_W<'a, REG> = crate::BitWriter<'a, REG>;
63#[doc = "Field `PR14` writer - Port n Reset Bit 14"]
64pub type PR14_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `PR15` writer - Port n Reset Bit 15"]
66pub type PR15_W<'a, REG> = crate::BitWriter<'a, REG>;
67impl W {
68    #[doc = "Bit 0 - Port n Set Bit 0"]
69    #[inline(always)]
70    pub fn ps0(&mut self) -> PS0_W<OMR_SPEC> {
71        PS0_W::new(self, 0)
72    }
73    #[doc = "Bit 1 - Port n Set Bit 1"]
74    #[inline(always)]
75    pub fn ps1(&mut self) -> PS1_W<OMR_SPEC> {
76        PS1_W::new(self, 1)
77    }
78    #[doc = "Bit 2 - Port n Set Bit 2"]
79    #[inline(always)]
80    pub fn ps2(&mut self) -> PS2_W<OMR_SPEC> {
81        PS2_W::new(self, 2)
82    }
83    #[doc = "Bit 3 - Port n Set Bit 3"]
84    #[inline(always)]
85    pub fn ps3(&mut self) -> PS3_W<OMR_SPEC> {
86        PS3_W::new(self, 3)
87    }
88    #[doc = "Bit 4 - Port n Set Bit 4"]
89    #[inline(always)]
90    pub fn ps4(&mut self) -> PS4_W<OMR_SPEC> {
91        PS4_W::new(self, 4)
92    }
93    #[doc = "Bit 5 - Port n Set Bit 5"]
94    #[inline(always)]
95    pub fn ps5(&mut self) -> PS5_W<OMR_SPEC> {
96        PS5_W::new(self, 5)
97    }
98    #[doc = "Bit 6 - Port n Set Bit 6"]
99    #[inline(always)]
100    pub fn ps6(&mut self) -> PS6_W<OMR_SPEC> {
101        PS6_W::new(self, 6)
102    }
103    #[doc = "Bit 7 - Port n Set Bit 7"]
104    #[inline(always)]
105    pub fn ps7(&mut self) -> PS7_W<OMR_SPEC> {
106        PS7_W::new(self, 7)
107    }
108    #[doc = "Bit 8 - Port n Set Bit 8"]
109    #[inline(always)]
110    pub fn ps8(&mut self) -> PS8_W<OMR_SPEC> {
111        PS8_W::new(self, 8)
112    }
113    #[doc = "Bit 9 - Port n Set Bit 9"]
114    #[inline(always)]
115    pub fn ps9(&mut self) -> PS9_W<OMR_SPEC> {
116        PS9_W::new(self, 9)
117    }
118    #[doc = "Bit 10 - Port n Set Bit 10"]
119    #[inline(always)]
120    pub fn ps10(&mut self) -> PS10_W<OMR_SPEC> {
121        PS10_W::new(self, 10)
122    }
123    #[doc = "Bit 11 - Port n Set Bit 11"]
124    #[inline(always)]
125    pub fn ps11(&mut self) -> PS11_W<OMR_SPEC> {
126        PS11_W::new(self, 11)
127    }
128    #[doc = "Bit 12 - Port n Set Bit 12"]
129    #[inline(always)]
130    pub fn ps12(&mut self) -> PS12_W<OMR_SPEC> {
131        PS12_W::new(self, 12)
132    }
133    #[doc = "Bit 13 - Port n Set Bit 13"]
134    #[inline(always)]
135    pub fn ps13(&mut self) -> PS13_W<OMR_SPEC> {
136        PS13_W::new(self, 13)
137    }
138    #[doc = "Bit 14 - Port n Set Bit 14"]
139    #[inline(always)]
140    pub fn ps14(&mut self) -> PS14_W<OMR_SPEC> {
141        PS14_W::new(self, 14)
142    }
143    #[doc = "Bit 15 - Port n Set Bit 15"]
144    #[inline(always)]
145    pub fn ps15(&mut self) -> PS15_W<OMR_SPEC> {
146        PS15_W::new(self, 15)
147    }
148    #[doc = "Bit 16 - Port n Reset Bit 0"]
149    #[inline(always)]
150    pub fn pr0(&mut self) -> PR0_W<OMR_SPEC> {
151        PR0_W::new(self, 16)
152    }
153    #[doc = "Bit 17 - Port n Reset Bit 1"]
154    #[inline(always)]
155    pub fn pr1(&mut self) -> PR1_W<OMR_SPEC> {
156        PR1_W::new(self, 17)
157    }
158    #[doc = "Bit 18 - Port n Reset Bit 2"]
159    #[inline(always)]
160    pub fn pr2(&mut self) -> PR2_W<OMR_SPEC> {
161        PR2_W::new(self, 18)
162    }
163    #[doc = "Bit 19 - Port n Reset Bit 3"]
164    #[inline(always)]
165    pub fn pr3(&mut self) -> PR3_W<OMR_SPEC> {
166        PR3_W::new(self, 19)
167    }
168    #[doc = "Bit 20 - Port n Reset Bit 4"]
169    #[inline(always)]
170    pub fn pr4(&mut self) -> PR4_W<OMR_SPEC> {
171        PR4_W::new(self, 20)
172    }
173    #[doc = "Bit 21 - Port n Reset Bit 5"]
174    #[inline(always)]
175    pub fn pr5(&mut self) -> PR5_W<OMR_SPEC> {
176        PR5_W::new(self, 21)
177    }
178    #[doc = "Bit 22 - Port n Reset Bit 6"]
179    #[inline(always)]
180    pub fn pr6(&mut self) -> PR6_W<OMR_SPEC> {
181        PR6_W::new(self, 22)
182    }
183    #[doc = "Bit 23 - Port n Reset Bit 7"]
184    #[inline(always)]
185    pub fn pr7(&mut self) -> PR7_W<OMR_SPEC> {
186        PR7_W::new(self, 23)
187    }
188    #[doc = "Bit 24 - Port n Reset Bit 8"]
189    #[inline(always)]
190    pub fn pr8(&mut self) -> PR8_W<OMR_SPEC> {
191        PR8_W::new(self, 24)
192    }
193    #[doc = "Bit 25 - Port n Reset Bit 9"]
194    #[inline(always)]
195    pub fn pr9(&mut self) -> PR9_W<OMR_SPEC> {
196        PR9_W::new(self, 25)
197    }
198    #[doc = "Bit 26 - Port n Reset Bit 10"]
199    #[inline(always)]
200    pub fn pr10(&mut self) -> PR10_W<OMR_SPEC> {
201        PR10_W::new(self, 26)
202    }
203    #[doc = "Bit 27 - Port n Reset Bit 11"]
204    #[inline(always)]
205    pub fn pr11(&mut self) -> PR11_W<OMR_SPEC> {
206        PR11_W::new(self, 27)
207    }
208    #[doc = "Bit 28 - Port n Reset Bit 12"]
209    #[inline(always)]
210    pub fn pr12(&mut self) -> PR12_W<OMR_SPEC> {
211        PR12_W::new(self, 28)
212    }
213    #[doc = "Bit 29 - Port n Reset Bit 13"]
214    #[inline(always)]
215    pub fn pr13(&mut self) -> PR13_W<OMR_SPEC> {
216        PR13_W::new(self, 29)
217    }
218    #[doc = "Bit 30 - Port n Reset Bit 14"]
219    #[inline(always)]
220    pub fn pr14(&mut self) -> PR14_W<OMR_SPEC> {
221        PR14_W::new(self, 30)
222    }
223    #[doc = "Bit 31 - Port n Reset Bit 15"]
224    #[inline(always)]
225    pub fn pr15(&mut self) -> PR15_W<OMR_SPEC> {
226        PR15_W::new(self, 31)
227    }
228}
229#[doc = "Port 6 Output Modification Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`omr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
230pub struct OMR_SPEC;
231impl crate::RegisterSpec for OMR_SPEC {
232    type Ux = u32;
233}
234#[doc = "`write(|w| ..)` method takes [`omr::W`](W) writer structure"]
235impl crate::Writable for OMR_SPEC {
236    type Safety = crate::Unsafe;
237    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
238    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
239}
240#[doc = "`reset()` method sets OMR to value 0"]
241impl crate::Resettable for OMR_SPEC {
242    const RESET_VALUE: u32 = 0;
243}