xmc4800/ebu/
buswcon3.rs

1#[doc = "Register `BUSWCON3` reader"]
2pub type R = crate::R<BUSWCON3_SPEC>;
3#[doc = "Register `BUSWCON3` writer"]
4pub type W = crate::W<BUSWCON3_SPEC>;
5#[doc = "Burst Length for Synchronous Burst\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum FETBLEN_A {
9    #[doc = "0: 1 data access (default after reset)."]
10    VALUE1 = 0,
11    #[doc = "1: 2 data accesses."]
12    VALUE2 = 1,
13    #[doc = "2: 4 data accesses."]
14    VALUE3 = 2,
15    #[doc = "3: 8 data accesses."]
16    VALUE4 = 3,
17}
18impl From<FETBLEN_A> for u8 {
19    #[inline(always)]
20    fn from(variant: FETBLEN_A) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for FETBLEN_A {
25    type Ux = u8;
26}
27impl crate::IsEnum for FETBLEN_A {}
28#[doc = "Field `FETBLEN` reader - Burst Length for Synchronous Burst"]
29pub type FETBLEN_R = crate::FieldReader<FETBLEN_A>;
30impl FETBLEN_R {
31    #[doc = "Get enumerated values variant"]
32    #[inline(always)]
33    pub const fn variant(&self) -> Option<FETBLEN_A> {
34        match self.bits {
35            0 => Some(FETBLEN_A::VALUE1),
36            1 => Some(FETBLEN_A::VALUE2),
37            2 => Some(FETBLEN_A::VALUE3),
38            3 => Some(FETBLEN_A::VALUE4),
39            _ => None,
40        }
41    }
42    #[doc = "1 data access (default after reset)."]
43    #[inline(always)]
44    pub fn is_value1(&self) -> bool {
45        *self == FETBLEN_A::VALUE1
46    }
47    #[doc = "2 data accesses."]
48    #[inline(always)]
49    pub fn is_value2(&self) -> bool {
50        *self == FETBLEN_A::VALUE2
51    }
52    #[doc = "4 data accesses."]
53    #[inline(always)]
54    pub fn is_value3(&self) -> bool {
55        *self == FETBLEN_A::VALUE3
56    }
57    #[doc = "8 data accesses."]
58    #[inline(always)]
59    pub fn is_value4(&self) -> bool {
60        *self == FETBLEN_A::VALUE4
61    }
62}
63#[doc = "Field `FETBLEN` writer - Burst Length for Synchronous Burst"]
64pub type FETBLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3, FETBLEN_A>;
65impl<'a, REG> FETBLEN_W<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "1 data access (default after reset)."]
71    #[inline(always)]
72    pub fn value1(self) -> &'a mut crate::W<REG> {
73        self.variant(FETBLEN_A::VALUE1)
74    }
75    #[doc = "2 data accesses."]
76    #[inline(always)]
77    pub fn value2(self) -> &'a mut crate::W<REG> {
78        self.variant(FETBLEN_A::VALUE2)
79    }
80    #[doc = "4 data accesses."]
81    #[inline(always)]
82    pub fn value3(self) -> &'a mut crate::W<REG> {
83        self.variant(FETBLEN_A::VALUE3)
84    }
85    #[doc = "8 data accesses."]
86    #[inline(always)]
87    pub fn value4(self) -> &'a mut crate::W<REG> {
88        self.variant(FETBLEN_A::VALUE4)
89    }
90}
91#[doc = "Synchronous burst buffer mode select\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq, Eq)]
93pub enum FBBMSEL_A {
94    #[doc = "0: Burst buffer length defined by value in FETBLEN (default after reset)."]
95    VALUE1 = 0,
96    #[doc = "1: Continuous mode. All data required for transaction transferred in single burst"]
97    VALUE2 = 1,
98}
99impl From<FBBMSEL_A> for bool {
100    #[inline(always)]
101    fn from(variant: FBBMSEL_A) -> Self {
102        variant as u8 != 0
103    }
104}
105#[doc = "Field `FBBMSEL` reader - Synchronous burst buffer mode select"]
106pub type FBBMSEL_R = crate::BitReader<FBBMSEL_A>;
107impl FBBMSEL_R {
108    #[doc = "Get enumerated values variant"]
109    #[inline(always)]
110    pub const fn variant(&self) -> FBBMSEL_A {
111        match self.bits {
112            false => FBBMSEL_A::VALUE1,
113            true => FBBMSEL_A::VALUE2,
114        }
115    }
116    #[doc = "Burst buffer length defined by value in FETBLEN (default after reset)."]
117    #[inline(always)]
118    pub fn is_value1(&self) -> bool {
119        *self == FBBMSEL_A::VALUE1
120    }
121    #[doc = "Continuous mode. All data required for transaction transferred in single burst"]
122    #[inline(always)]
123    pub fn is_value2(&self) -> bool {
124        *self == FBBMSEL_A::VALUE2
125    }
126}
127#[doc = "Field `FBBMSEL` writer - Synchronous burst buffer mode select"]
128pub type FBBMSEL_W<'a, REG> = crate::BitWriter<'a, REG, FBBMSEL_A>;
129impl<'a, REG> FBBMSEL_W<'a, REG>
130where
131    REG: crate::Writable + crate::RegisterSpec,
132{
133    #[doc = "Burst buffer length defined by value in FETBLEN (default after reset)."]
134    #[inline(always)]
135    pub fn value1(self) -> &'a mut crate::W<REG> {
136        self.variant(FBBMSEL_A::VALUE1)
137    }
138    #[doc = "Continuous mode. All data required for transaction transferred in single burst"]
139    #[inline(always)]
140    pub fn value2(self) -> &'a mut crate::W<REG> {
141        self.variant(FBBMSEL_A::VALUE2)
142    }
143}
144#[doc = "Field `NAA` reader - Enable flash non-array access workaround"]
145pub type NAA_R = crate::BitReader;
146#[doc = "Early Chip Select for Synchronous Burst\n\nValue on reset: 1"]
147#[derive(Clone, Copy, Debug, PartialEq, Eq)]
148pub enum ECSE_A {
149    #[doc = "0: CS is delayed."]
150    VALUE1 = 0,
151    #[doc = "1: CS is not delayed."]
152    VALUE2 = 1,
153}
154impl From<ECSE_A> for bool {
155    #[inline(always)]
156    fn from(variant: ECSE_A) -> Self {
157        variant as u8 != 0
158    }
159}
160#[doc = "Field `ECSE` reader - Early Chip Select for Synchronous Burst"]
161pub type ECSE_R = crate::BitReader<ECSE_A>;
162impl ECSE_R {
163    #[doc = "Get enumerated values variant"]
164    #[inline(always)]
165    pub const fn variant(&self) -> ECSE_A {
166        match self.bits {
167            false => ECSE_A::VALUE1,
168            true => ECSE_A::VALUE2,
169        }
170    }
171    #[doc = "CS is delayed."]
172    #[inline(always)]
173    pub fn is_value1(&self) -> bool {
174        *self == ECSE_A::VALUE1
175    }
176    #[doc = "CS is not delayed."]
177    #[inline(always)]
178    pub fn is_value2(&self) -> bool {
179        *self == ECSE_A::VALUE2
180    }
181}
182#[doc = "Field `ECSE` writer - Early Chip Select for Synchronous Burst"]
183pub type ECSE_W<'a, REG> = crate::BitWriter<'a, REG, ECSE_A>;
184impl<'a, REG> ECSE_W<'a, REG>
185where
186    REG: crate::Writable + crate::RegisterSpec,
187{
188    #[doc = "CS is delayed."]
189    #[inline(always)]
190    pub fn value1(self) -> &'a mut crate::W<REG> {
191        self.variant(ECSE_A::VALUE1)
192    }
193    #[doc = "CS is not delayed."]
194    #[inline(always)]
195    pub fn value2(self) -> &'a mut crate::W<REG> {
196        self.variant(ECSE_A::VALUE2)
197    }
198}
199#[doc = "Early Burst Signal Enable for Synchronous Burst\n\nValue on reset: 1"]
200#[derive(Clone, Copy, Debug, PartialEq, Eq)]
201pub enum EBSE_A {
202    #[doc = "0: ADV is delayed."]
203    VALUE1 = 0,
204    #[doc = "1: ADV is not delayed."]
205    VALUE2 = 1,
206}
207impl From<EBSE_A> for bool {
208    #[inline(always)]
209    fn from(variant: EBSE_A) -> Self {
210        variant as u8 != 0
211    }
212}
213#[doc = "Field `EBSE` reader - Early Burst Signal Enable for Synchronous Burst"]
214pub type EBSE_R = crate::BitReader<EBSE_A>;
215impl EBSE_R {
216    #[doc = "Get enumerated values variant"]
217    #[inline(always)]
218    pub const fn variant(&self) -> EBSE_A {
219        match self.bits {
220            false => EBSE_A::VALUE1,
221            true => EBSE_A::VALUE2,
222        }
223    }
224    #[doc = "ADV is delayed."]
225    #[inline(always)]
226    pub fn is_value1(&self) -> bool {
227        *self == EBSE_A::VALUE1
228    }
229    #[doc = "ADV is not delayed."]
230    #[inline(always)]
231    pub fn is_value2(&self) -> bool {
232        *self == EBSE_A::VALUE2
233    }
234}
235#[doc = "Field `EBSE` writer - Early Burst Signal Enable for Synchronous Burst"]
236pub type EBSE_W<'a, REG> = crate::BitWriter<'a, REG, EBSE_A>;
237impl<'a, REG> EBSE_W<'a, REG>
238where
239    REG: crate::Writable + crate::RegisterSpec,
240{
241    #[doc = "ADV is delayed."]
242    #[inline(always)]
243    pub fn value1(self) -> &'a mut crate::W<REG> {
244        self.variant(EBSE_A::VALUE1)
245    }
246    #[doc = "ADV is not delayed."]
247    #[inline(always)]
248    pub fn value2(self) -> &'a mut crate::W<REG> {
249        self.variant(EBSE_A::VALUE2)
250    }
251}
252#[doc = "Reversed polarity at WAIT\n\nValue on reset: 0"]
253#[derive(Clone, Copy, Debug, PartialEq, Eq)]
254pub enum WAITINV_A {
255    #[doc = "0: input at WAIT pin is active low (default after reset)."]
256    VALUE1 = 0,
257    #[doc = "1: input at WAIT pin is active high."]
258    VALUE2 = 1,
259}
260impl From<WAITINV_A> for bool {
261    #[inline(always)]
262    fn from(variant: WAITINV_A) -> Self {
263        variant as u8 != 0
264    }
265}
266#[doc = "Field `WAITINV` reader - Reversed polarity at WAIT"]
267pub type WAITINV_R = crate::BitReader<WAITINV_A>;
268impl WAITINV_R {
269    #[doc = "Get enumerated values variant"]
270    #[inline(always)]
271    pub const fn variant(&self) -> WAITINV_A {
272        match self.bits {
273            false => WAITINV_A::VALUE1,
274            true => WAITINV_A::VALUE2,
275        }
276    }
277    #[doc = "input at WAIT pin is active low (default after reset)."]
278    #[inline(always)]
279    pub fn is_value1(&self) -> bool {
280        *self == WAITINV_A::VALUE1
281    }
282    #[doc = "input at WAIT pin is active high."]
283    #[inline(always)]
284    pub fn is_value2(&self) -> bool {
285        *self == WAITINV_A::VALUE2
286    }
287}
288#[doc = "Field `WAITINV` writer - Reversed polarity at WAIT"]
289pub type WAITINV_W<'a, REG> = crate::BitWriter<'a, REG, WAITINV_A>;
290impl<'a, REG> WAITINV_W<'a, REG>
291where
292    REG: crate::Writable + crate::RegisterSpec,
293{
294    #[doc = "input at WAIT pin is active low (default after reset)."]
295    #[inline(always)]
296    pub fn value1(self) -> &'a mut crate::W<REG> {
297        self.variant(WAITINV_A::VALUE1)
298    }
299    #[doc = "input at WAIT pin is active high."]
300    #[inline(always)]
301    pub fn value2(self) -> &'a mut crate::W<REG> {
302        self.variant(WAITINV_A::VALUE2)
303    }
304}
305#[doc = "Byte Control Signal Control\n\nValue on reset: 1"]
306#[derive(Clone, Copy, Debug, PartialEq, Eq)]
307#[repr(u8)]
308pub enum BCGEN_A {
309    #[doc = "0: Byte control signals follow chip select timing."]
310    VALUE1 = 0,
311    #[doc = "1: Byte control signals follow control signal timing (RD, RD/WR) (default after reset)."]
312    VALUE2 = 1,
313    #[doc = "2: Byte control signals follow write enable signal timing (RD/WR only)."]
314    VALUE3 = 2,
315}
316impl From<BCGEN_A> for u8 {
317    #[inline(always)]
318    fn from(variant: BCGEN_A) -> Self {
319        variant as _
320    }
321}
322impl crate::FieldSpec for BCGEN_A {
323    type Ux = u8;
324}
325impl crate::IsEnum for BCGEN_A {}
326#[doc = "Field `BCGEN` reader - Byte Control Signal Control"]
327pub type BCGEN_R = crate::FieldReader<BCGEN_A>;
328impl BCGEN_R {
329    #[doc = "Get enumerated values variant"]
330    #[inline(always)]
331    pub const fn variant(&self) -> Option<BCGEN_A> {
332        match self.bits {
333            0 => Some(BCGEN_A::VALUE1),
334            1 => Some(BCGEN_A::VALUE2),
335            2 => Some(BCGEN_A::VALUE3),
336            _ => None,
337        }
338    }
339    #[doc = "Byte control signals follow chip select timing."]
340    #[inline(always)]
341    pub fn is_value1(&self) -> bool {
342        *self == BCGEN_A::VALUE1
343    }
344    #[doc = "Byte control signals follow control signal timing (RD, RD/WR) (default after reset)."]
345    #[inline(always)]
346    pub fn is_value2(&self) -> bool {
347        *self == BCGEN_A::VALUE2
348    }
349    #[doc = "Byte control signals follow write enable signal timing (RD/WR only)."]
350    #[inline(always)]
351    pub fn is_value3(&self) -> bool {
352        *self == BCGEN_A::VALUE3
353    }
354}
355#[doc = "Field `BCGEN` writer - Byte Control Signal Control"]
356pub type BCGEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, BCGEN_A>;
357impl<'a, REG> BCGEN_W<'a, REG>
358where
359    REG: crate::Writable + crate::RegisterSpec,
360    REG::Ux: From<u8>,
361{
362    #[doc = "Byte control signals follow chip select timing."]
363    #[inline(always)]
364    pub fn value1(self) -> &'a mut crate::W<REG> {
365        self.variant(BCGEN_A::VALUE1)
366    }
367    #[doc = "Byte control signals follow control signal timing (RD, RD/WR) (default after reset)."]
368    #[inline(always)]
369    pub fn value2(self) -> &'a mut crate::W<REG> {
370        self.variant(BCGEN_A::VALUE2)
371    }
372    #[doc = "Byte control signals follow write enable signal timing (RD/WR only)."]
373    #[inline(always)]
374    pub fn value3(self) -> &'a mut crate::W<REG> {
375        self.variant(BCGEN_A::VALUE3)
376    }
377}
378#[doc = "Field `PORTW` reader - Device Addressing Mode"]
379pub type PORTW_R = crate::FieldReader;
380#[doc = "Field `WAIT` reader - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,"]
381pub type WAIT_R = crate::FieldReader;
382#[doc = "Field `WAIT` writer - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,"]
383pub type WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
384#[doc = "Asynchronous Address phase:\n\nValue on reset: 0"]
385#[derive(Clone, Copy, Debug, PartialEq, Eq)]
386pub enum AAP_A {
387    #[doc = "0: Clock is enabled at beginning of access."]
388    VALUE1 = 0,
389    #[doc = "1: Clock is enabled at after address phase."]
390    VALUE2 = 1,
391}
392impl From<AAP_A> for bool {
393    #[inline(always)]
394    fn from(variant: AAP_A) -> Self {
395        variant as u8 != 0
396    }
397}
398#[doc = "Field `AAP` reader - Asynchronous Address phase:"]
399pub type AAP_R = crate::BitReader<AAP_A>;
400impl AAP_R {
401    #[doc = "Get enumerated values variant"]
402    #[inline(always)]
403    pub const fn variant(&self) -> AAP_A {
404        match self.bits {
405            false => AAP_A::VALUE1,
406            true => AAP_A::VALUE2,
407        }
408    }
409    #[doc = "Clock is enabled at beginning of access."]
410    #[inline(always)]
411    pub fn is_value1(&self) -> bool {
412        *self == AAP_A::VALUE1
413    }
414    #[doc = "Clock is enabled at after address phase."]
415    #[inline(always)]
416    pub fn is_value2(&self) -> bool {
417        *self == AAP_A::VALUE2
418    }
419}
420#[doc = "Field `AAP` writer - Asynchronous Address phase:"]
421pub type AAP_W<'a, REG> = crate::BitWriter<'a, REG, AAP_A>;
422impl<'a, REG> AAP_W<'a, REG>
423where
424    REG: crate::Writable + crate::RegisterSpec,
425{
426    #[doc = "Clock is enabled at beginning of access."]
427    #[inline(always)]
428    pub fn value1(self) -> &'a mut crate::W<REG> {
429        self.variant(AAP_A::VALUE1)
430    }
431    #[doc = "Clock is enabled at after address phase."]
432    #[inline(always)]
433    pub fn value2(self) -> &'a mut crate::W<REG> {
434        self.variant(AAP_A::VALUE2)
435    }
436}
437#[doc = "Lock Chip Select\n\nValue on reset: 0"]
438#[derive(Clone, Copy, Debug, PartialEq, Eq)]
439pub enum LOCKCS_A {
440    #[doc = "0: Chip Select cannot be locked (default after reset)."]
441    VALUE1 = 0,
442    #[doc = "1: Chip Select will be automatically locked when written to from the processor data port."]
443    VALUE2 = 1,
444}
445impl From<LOCKCS_A> for bool {
446    #[inline(always)]
447    fn from(variant: LOCKCS_A) -> Self {
448        variant as u8 != 0
449    }
450}
451#[doc = "Field `LOCKCS` reader - Lock Chip Select"]
452pub type LOCKCS_R = crate::BitReader<LOCKCS_A>;
453impl LOCKCS_R {
454    #[doc = "Get enumerated values variant"]
455    #[inline(always)]
456    pub const fn variant(&self) -> LOCKCS_A {
457        match self.bits {
458            false => LOCKCS_A::VALUE1,
459            true => LOCKCS_A::VALUE2,
460        }
461    }
462    #[doc = "Chip Select cannot be locked (default after reset)."]
463    #[inline(always)]
464    pub fn is_value1(&self) -> bool {
465        *self == LOCKCS_A::VALUE1
466    }
467    #[doc = "Chip Select will be automatically locked when written to from the processor data port."]
468    #[inline(always)]
469    pub fn is_value2(&self) -> bool {
470        *self == LOCKCS_A::VALUE2
471    }
472}
473#[doc = "Field `LOCKCS` writer - Lock Chip Select"]
474pub type LOCKCS_W<'a, REG> = crate::BitWriter<'a, REG, LOCKCS_A>;
475impl<'a, REG> LOCKCS_W<'a, REG>
476where
477    REG: crate::Writable + crate::RegisterSpec,
478{
479    #[doc = "Chip Select cannot be locked (default after reset)."]
480    #[inline(always)]
481    pub fn value1(self) -> &'a mut crate::W<REG> {
482        self.variant(LOCKCS_A::VALUE1)
483    }
484    #[doc = "Chip Select will be automatically locked when written to from the processor data port."]
485    #[inline(always)]
486    pub fn value2(self) -> &'a mut crate::W<REG> {
487        self.variant(LOCKCS_A::VALUE2)
488    }
489}
490#[doc = "Field `AGEN` reader - Device Type for Region"]
491pub type AGEN_R = crate::FieldReader;
492#[doc = "Field `AGEN` writer - Device Type for Region"]
493pub type AGEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
494impl R {
495    #[doc = "Bits 0:2 - Burst Length for Synchronous Burst"]
496    #[inline(always)]
497    pub fn fetblen(&self) -> FETBLEN_R {
498        FETBLEN_R::new((self.bits & 7) as u8)
499    }
500    #[doc = "Bit 3 - Synchronous burst buffer mode select"]
501    #[inline(always)]
502    pub fn fbbmsel(&self) -> FBBMSEL_R {
503        FBBMSEL_R::new(((self.bits >> 3) & 1) != 0)
504    }
505    #[doc = "Bit 7 - Enable flash non-array access workaround"]
506    #[inline(always)]
507    pub fn naa(&self) -> NAA_R {
508        NAA_R::new(((self.bits >> 7) & 1) != 0)
509    }
510    #[doc = "Bit 16 - Early Chip Select for Synchronous Burst"]
511    #[inline(always)]
512    pub fn ecse(&self) -> ECSE_R {
513        ECSE_R::new(((self.bits >> 16) & 1) != 0)
514    }
515    #[doc = "Bit 17 - Early Burst Signal Enable for Synchronous Burst"]
516    #[inline(always)]
517    pub fn ebse(&self) -> EBSE_R {
518        EBSE_R::new(((self.bits >> 17) & 1) != 0)
519    }
520    #[doc = "Bit 19 - Reversed polarity at WAIT"]
521    #[inline(always)]
522    pub fn waitinv(&self) -> WAITINV_R {
523        WAITINV_R::new(((self.bits >> 19) & 1) != 0)
524    }
525    #[doc = "Bits 20:21 - Byte Control Signal Control"]
526    #[inline(always)]
527    pub fn bcgen(&self) -> BCGEN_R {
528        BCGEN_R::new(((self.bits >> 20) & 3) as u8)
529    }
530    #[doc = "Bits 22:23 - Device Addressing Mode"]
531    #[inline(always)]
532    pub fn portw(&self) -> PORTW_R {
533        PORTW_R::new(((self.bits >> 22) & 3) as u8)
534    }
535    #[doc = "Bits 24:25 - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,"]
536    #[inline(always)]
537    pub fn wait(&self) -> WAIT_R {
538        WAIT_R::new(((self.bits >> 24) & 3) as u8)
539    }
540    #[doc = "Bit 26 - Asynchronous Address phase:"]
541    #[inline(always)]
542    pub fn aap(&self) -> AAP_R {
543        AAP_R::new(((self.bits >> 26) & 1) != 0)
544    }
545    #[doc = "Bit 27 - Lock Chip Select"]
546    #[inline(always)]
547    pub fn lockcs(&self) -> LOCKCS_R {
548        LOCKCS_R::new(((self.bits >> 27) & 1) != 0)
549    }
550    #[doc = "Bits 28:31 - Device Type for Region"]
551    #[inline(always)]
552    pub fn agen(&self) -> AGEN_R {
553        AGEN_R::new(((self.bits >> 28) & 0x0f) as u8)
554    }
555}
556impl W {
557    #[doc = "Bits 0:2 - Burst Length for Synchronous Burst"]
558    #[inline(always)]
559    pub fn fetblen(&mut self) -> FETBLEN_W<BUSWCON3_SPEC> {
560        FETBLEN_W::new(self, 0)
561    }
562    #[doc = "Bit 3 - Synchronous burst buffer mode select"]
563    #[inline(always)]
564    pub fn fbbmsel(&mut self) -> FBBMSEL_W<BUSWCON3_SPEC> {
565        FBBMSEL_W::new(self, 3)
566    }
567    #[doc = "Bit 16 - Early Chip Select for Synchronous Burst"]
568    #[inline(always)]
569    pub fn ecse(&mut self) -> ECSE_W<BUSWCON3_SPEC> {
570        ECSE_W::new(self, 16)
571    }
572    #[doc = "Bit 17 - Early Burst Signal Enable for Synchronous Burst"]
573    #[inline(always)]
574    pub fn ebse(&mut self) -> EBSE_W<BUSWCON3_SPEC> {
575        EBSE_W::new(self, 17)
576    }
577    #[doc = "Bit 19 - Reversed polarity at WAIT"]
578    #[inline(always)]
579    pub fn waitinv(&mut self) -> WAITINV_W<BUSWCON3_SPEC> {
580        WAITINV_W::new(self, 19)
581    }
582    #[doc = "Bits 20:21 - Byte Control Signal Control"]
583    #[inline(always)]
584    pub fn bcgen(&mut self) -> BCGEN_W<BUSWCON3_SPEC> {
585        BCGEN_W::new(self, 20)
586    }
587    #[doc = "Bits 24:25 - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,"]
588    #[inline(always)]
589    pub fn wait(&mut self) -> WAIT_W<BUSWCON3_SPEC> {
590        WAIT_W::new(self, 24)
591    }
592    #[doc = "Bit 26 - Asynchronous Address phase:"]
593    #[inline(always)]
594    pub fn aap(&mut self) -> AAP_W<BUSWCON3_SPEC> {
595        AAP_W::new(self, 26)
596    }
597    #[doc = "Bit 27 - Lock Chip Select"]
598    #[inline(always)]
599    pub fn lockcs(&mut self) -> LOCKCS_W<BUSWCON3_SPEC> {
600        LOCKCS_W::new(self, 27)
601    }
602    #[doc = "Bits 28:31 - Device Type for Region"]
603    #[inline(always)]
604    pub fn agen(&mut self) -> AGEN_W<BUSWCON3_SPEC> {
605        AGEN_W::new(self, 28)
606    }
607}
608#[doc = "EBU Bus Write Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`buswcon3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`buswcon3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
609pub struct BUSWCON3_SPEC;
610impl crate::RegisterSpec for BUSWCON3_SPEC {
611    type Ux = u32;
612}
613#[doc = "`read()` method returns [`buswcon3::R`](R) reader structure"]
614impl crate::Readable for BUSWCON3_SPEC {}
615#[doc = "`write(|w| ..)` method takes [`buswcon3::W`](W) writer structure"]
616impl crate::Writable for BUSWCON3_SPEC {
617    type Safety = crate::Unsafe;
618    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
619    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
620}
621#[doc = "`reset()` method sets BUSWCON3 to value 0x00d3_0000"]
622impl crate::Resettable for BUSWCON3_SPEC {
623    const RESET_VALUE: u32 = 0x00d3_0000;
624}
xmc4800/ebu/buswcon3.rs

xmc4800/ebu/
buswcon3.rs
