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#[doc = "Register `CTR` reader"]
pub struct R(crate::R<CTR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CTR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CTR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CTR` writer"]
pub struct W(crate::W<CTR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CTR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CTR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `FCM` reader - Force CRC Mismatch"]
pub struct FCM_R(crate::FieldReader<bool, bool>);
impl FCM_R {
pub(crate) fn new(bits: bool) -> Self {
FCM_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for FCM_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `FCM` writer - Force CRC Mismatch"]
pub struct FCM_W<'a> {
w: &'a mut W,
}
impl<'a> FCM_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
#[doc = "Field `FRM_CFG` reader - Force CFG Register Mismatch"]
pub struct FRM_CFG_R(crate::FieldReader<bool, bool>);
impl FRM_CFG_R {
pub(crate) fn new(bits: bool) -> Self {
FRM_CFG_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for FRM_CFG_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `FRM_CFG` writer - Force CFG Register Mismatch"]
pub struct FRM_CFG_W<'a> {
w: &'a mut W,
}
impl<'a> FRM_CFG_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
self.w
}
}
#[doc = "Field `FRM_CHECK` reader - Force Check Register Mismatch"]
pub struct FRM_CHECK_R(crate::FieldReader<bool, bool>);
impl FRM_CHECK_R {
pub(crate) fn new(bits: bool) -> Self {
FRM_CHECK_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for FRM_CHECK_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `FRM_CHECK` writer - Force Check Register Mismatch"]
pub struct FRM_CHECK_W<'a> {
w: &'a mut W,
}
impl<'a> FRM_CHECK_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
self.w
}
}
impl R {
#[doc = "Bit 0 - Force CRC Mismatch"]
#[inline(always)]
pub fn fcm(&self) -> FCM_R {
FCM_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - Force CFG Register Mismatch"]
#[inline(always)]
pub fn frm_cfg(&self) -> FRM_CFG_R {
FRM_CFG_R::new(((self.bits >> 1) & 0x01) != 0)
}
#[doc = "Bit 2 - Force Check Register Mismatch"]
#[inline(always)]
pub fn frm_check(&self) -> FRM_CHECK_R {
FRM_CHECK_R::new(((self.bits >> 2) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 0 - Force CRC Mismatch"]
#[inline(always)]
pub fn fcm(&mut self) -> FCM_W {
FCM_W { w: self }
}
#[doc = "Bit 1 - Force CFG Register Mismatch"]
#[inline(always)]
pub fn frm_cfg(&mut self) -> FRM_CFG_W {
FRM_CFG_W { w: self }
}
#[doc = "Bit 2 - Force Check Register Mismatch"]
#[inline(always)]
pub fn frm_check(&mut self) -> FRM_CHECK_W {
FRM_CHECK_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CRC Test Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctr](index.html) module"]
pub struct CTR_SPEC;
impl crate::RegisterSpec for CTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ctr::R](R) reader structure"]
impl crate::Readable for CTR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctr::W](W) writer structure"]
impl crate::Writable for CTR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CTR to value 0"]
impl crate::Resettable for CTR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}