xmc4800 0.14.0

XMC peripheral library for XMC4800 generated from SVD
Documentation 
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#[doc = "Register `ECATCLKCR` reader"]
pub type R = crate::R<ECATCLKCR_SPEC>;
#[doc = "Register `ECATCLKCR` writer"]
pub type W = crate::W<ECATCLKCR_SPEC>;
#[doc = "Field `ECADIV` reader - EtherCAT Clock Divider Value"]
pub type ECADIV_R = crate::FieldReader;
#[doc = "Field `ECADIV` writer - EtherCAT Clock Divider Value"]
pub type ECADIV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "EtherCAT Clock Selection Value\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ECATSEL_A {
    #[doc = "0: fPLLUSBclock"]
    VALUE1 = 0,
    #[doc = "1: fPLLclock"]
    VALUE2 = 1,
}
impl From<ECATSEL_A> for bool {
    #[inline(always)]
    fn from(variant: ECATSEL_A) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `ECATSEL` reader - EtherCAT Clock Selection Value"]
pub type ECATSEL_R = crate::BitReader<ECATSEL_A>;
impl ECATSEL_R {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub const fn variant(&self) -> ECATSEL_A {
        match self.bits {
            false => ECATSEL_A::VALUE1,
            true => ECATSEL_A::VALUE2,
        }
    }
    #[doc = "fPLLUSBclock"]
    #[inline(always)]
    pub fn is_value1(&self) -> bool {
        *self == ECATSEL_A::VALUE1
    }
    #[doc = "fPLLclock"]
    #[inline(always)]
    pub fn is_value2(&self) -> bool {
        *self == ECATSEL_A::VALUE2
    }
}
#[doc = "Field `ECATSEL` writer - EtherCAT Clock Selection Value"]
pub type ECATSEL_W<'a, REG> = crate::BitWriter<'a, REG, ECATSEL_A>;
impl<'a, REG> ECATSEL_W<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    #[doc = "fPLLUSBclock"]
    #[inline(always)]
    pub fn value1(self) -> &'a mut crate::W<REG> {
        self.variant(ECATSEL_A::VALUE1)
    }
    #[doc = "fPLLclock"]
    #[inline(always)]
    pub fn value2(self) -> &'a mut crate::W<REG> {
        self.variant(ECATSEL_A::VALUE2)
    }
}
impl R {
    #[doc = "Bits 0:1 - EtherCAT Clock Divider Value"]
    #[inline(always)]
    pub fn ecadiv(&self) -> ECADIV_R {
        ECADIV_R::new((self.bits & 3) as u8)
    }
    #[doc = "Bit 16 - EtherCAT Clock Selection Value"]
    #[inline(always)]
    pub fn ecatsel(&self) -> ECATSEL_R {
        ECATSEL_R::new(((self.bits >> 16) & 1) != 0)
    }
}
impl W {
    #[doc = "Bits 0:1 - EtherCAT Clock Divider Value"]
    #[inline(always)]
    pub fn ecadiv(&mut self) -> ECADIV_W<'_, ECATCLKCR_SPEC> {
        ECADIV_W::new(self, 0)
    }
    #[doc = "Bit 16 - EtherCAT Clock Selection Value"]
    #[inline(always)]
    pub fn ecatsel(&mut self) -> ECATSEL_W<'_, ECATCLKCR_SPEC> {
        ECATSEL_W::new(self, 16)
    }
}
#[doc = "EtherCAT Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ecatclkcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ecatclkcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ECATCLKCR_SPEC;
impl crate::RegisterSpec for ECATCLKCR_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`ecatclkcr::R`](R) reader structure"]
impl crate::Readable for ECATCLKCR_SPEC {}
#[doc = "`write(|w| ..)` method takes [`ecatclkcr::W`](W) writer structure"]
impl crate::Writable for ECATCLKCR_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ECATCLKCR to value 0"]
impl crate::Resettable for ECATCLKCR_SPEC {}