#![doc = "Peripheral access API for XMC4800 microcontrollers (generated using svd2rust v0.37.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
#![cfg_attr(docsrs, feature(doc_cfg))]
#[doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 6;
#[allow(unused_imports)]
use generic::*;
#[doc = r"Common register and bit access and modify traits"]
pub mod generic;
#[cfg(feature = "rt")]
extern "C" {
fn SCU_0();
fn ERU0_0();
fn ERU0_1();
fn ERU0_2();
fn ERU0_3();
fn ERU1_0();
fn ERU1_1();
fn ERU1_2();
fn ERU1_3();
fn PMU0_0();
fn VADC0_C0_0();
fn VADC0_C0_1();
fn VADC0_C0_2();
fn VADC0_C0_3();
fn VADC0_G0_0();
fn VADC0_G0_1();
fn VADC0_G0_2();
fn VADC0_G0_3();
fn VADC0_G1_0();
fn VADC0_G1_1();
fn VADC0_G1_2();
fn VADC0_G1_3();
fn VADC0_G2_0();
fn VADC0_G2_1();
fn VADC0_G2_2();
fn VADC0_G2_3();
fn VADC0_G3_0();
fn VADC0_G3_1();
fn VADC0_G3_2();
fn VADC0_G3_3();
fn DSD0_M_0();
fn DSD0_M_1();
fn DSD0_M_2();
fn DSD0_M_3();
fn DSD0_A_4();
fn DSD0_A_5();
fn DSD0_A_6();
fn DSD0_A_7();
fn DAC0_0();
fn DAC0_1();
fn CCU40_0();
fn CCU40_1();
fn CCU40_2();
fn CCU40_3();
fn CCU41_0();
fn CCU41_1();
fn CCU41_2();
fn CCU41_3();
fn CCU42_0();
fn CCU42_1();
fn CCU42_2();
fn CCU42_3();
fn CCU43_0();
fn CCU43_1();
fn CCU43_2();
fn CCU43_3();
fn CCU80_0();
fn CCU80_1();
fn CCU80_2();
fn CCU80_3();
fn CCU81_0();
fn CCU81_1();
fn CCU81_2();
fn CCU81_3();
fn POSIF0_0();
fn POSIF0_1();
fn POSIF1_0();
fn POSIF1_1();
fn CAN0_0();
fn CAN0_1();
fn CAN0_2();
fn CAN0_3();
fn CAN0_4();
fn CAN0_5();
fn CAN0_6();
fn CAN0_7();
fn USIC0_0();
fn USIC0_1();
fn USIC0_2();
fn USIC0_3();
fn USIC0_4();
fn USIC0_5();
fn USIC1_0();
fn USIC1_1();
fn USIC1_2();
fn USIC1_3();
fn USIC1_4();
fn USIC1_5();
fn USIC2_0();
fn USIC2_1();
fn USIC2_2();
fn USIC2_3();
fn USIC2_4();
fn USIC2_5();
fn LEDTS0_0();
fn FCE0_0();
fn GPDMA0_0();
fn SDMMC0_0();
fn USB0_0();
fn ETH0_0();
fn ECAT0_0();
fn GPDMA1_0();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
_handler: unsafe extern "C" fn(),
_reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 111] = [
Vector { _handler: SCU_0 },
Vector { _handler: ERU0_0 },
Vector { _handler: ERU0_1 },
Vector { _handler: ERU0_2 },
Vector { _handler: ERU0_3 },
Vector { _handler: ERU1_0 },
Vector { _handler: ERU1_1 },
Vector { _handler: ERU1_2 },
Vector { _handler: ERU1_3 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: PMU0_0 },
Vector { _reserved: 0 },
Vector { _handler: VADC0_C0_0 },
Vector { _handler: VADC0_C0_1 },
Vector { _handler: VADC0_C0_2 },
Vector { _handler: VADC0_C0_3 },
Vector { _handler: VADC0_G0_0 },
Vector { _handler: VADC0_G0_1 },
Vector { _handler: VADC0_G0_2 },
Vector { _handler: VADC0_G0_3 },
Vector { _handler: VADC0_G1_0 },
Vector { _handler: VADC0_G1_1 },
Vector { _handler: VADC0_G1_2 },
Vector { _handler: VADC0_G1_3 },
Vector { _handler: VADC0_G2_0 },
Vector { _handler: VADC0_G2_1 },
Vector { _handler: VADC0_G2_2 },
Vector { _handler: VADC0_G2_3 },
Vector { _handler: VADC0_G3_0 },
Vector { _handler: VADC0_G3_1 },
Vector { _handler: VADC0_G3_2 },
Vector { _handler: VADC0_G3_3 },
Vector { _handler: DSD0_M_0 },
Vector { _handler: DSD0_M_1 },
Vector { _handler: DSD0_M_2 },
Vector { _handler: DSD0_M_3 },
Vector { _handler: DSD0_A_4 },
Vector { _handler: DSD0_A_5 },
Vector { _handler: DSD0_A_6 },
Vector { _handler: DSD0_A_7 },
Vector { _handler: DAC0_0 },
Vector { _handler: DAC0_1 },
Vector { _handler: CCU40_0 },
Vector { _handler: CCU40_1 },
Vector { _handler: CCU40_2 },
Vector { _handler: CCU40_3 },
Vector { _handler: CCU41_0 },
Vector { _handler: CCU41_1 },
Vector { _handler: CCU41_2 },
Vector { _handler: CCU41_3 },
Vector { _handler: CCU42_0 },
Vector { _handler: CCU42_1 },
Vector { _handler: CCU42_2 },
Vector { _handler: CCU42_3 },
Vector { _handler: CCU43_0 },
Vector { _handler: CCU43_1 },
Vector { _handler: CCU43_2 },
Vector { _handler: CCU43_3 },
Vector { _handler: CCU80_0 },
Vector { _handler: CCU80_1 },
Vector { _handler: CCU80_2 },
Vector { _handler: CCU80_3 },
Vector { _handler: CCU81_0 },
Vector { _handler: CCU81_1 },
Vector { _handler: CCU81_2 },
Vector { _handler: CCU81_3 },
Vector { _handler: POSIF0_0 },
Vector { _handler: POSIF0_1 },
Vector { _handler: POSIF1_0 },
Vector { _handler: POSIF1_1 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: CAN0_0 },
Vector { _handler: CAN0_1 },
Vector { _handler: CAN0_2 },
Vector { _handler: CAN0_3 },
Vector { _handler: CAN0_4 },
Vector { _handler: CAN0_5 },
Vector { _handler: CAN0_6 },
Vector { _handler: CAN0_7 },
Vector { _handler: USIC0_0 },
Vector { _handler: USIC0_1 },
Vector { _handler: USIC0_2 },
Vector { _handler: USIC0_3 },
Vector { _handler: USIC0_4 },
Vector { _handler: USIC0_5 },
Vector { _handler: USIC1_0 },
Vector { _handler: USIC1_1 },
Vector { _handler: USIC1_2 },
Vector { _handler: USIC1_3 },
Vector { _handler: USIC1_4 },
Vector { _handler: USIC1_5 },
Vector { _handler: USIC2_0 },
Vector { _handler: USIC2_1 },
Vector { _handler: USIC2_2 },
Vector { _handler: USIC2_3 },
Vector { _handler: USIC2_4 },
Vector { _handler: USIC2_5 },
Vector { _handler: LEDTS0_0 },
Vector { _reserved: 0 },
Vector { _handler: FCE0_0 },
Vector { _handler: GPDMA0_0 },
Vector { _handler: SDMMC0_0 },
Vector { _handler: USB0_0 },
Vector { _handler: ETH0_0 },
Vector { _handler: ECAT0_0 },
Vector { _handler: GPDMA1_0 },
];
#[doc = r"Enumeration of all the interrupts."]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
#[doc = "0 - System Control"]
SCU_0 = 0,
#[doc = "1 - External Request Unit 0"]
ERU0_0 = 1,
#[doc = "2 - External Request Unit 0"]
ERU0_1 = 2,
#[doc = "3 - External Request Unit 0"]
ERU0_2 = 3,
#[doc = "4 - External Request Unit 0"]
ERU0_3 = 4,
#[doc = "5 - External Request Unit 1"]
ERU1_0 = 5,
#[doc = "6 - External Request Unit 1"]
ERU1_1 = 6,
#[doc = "7 - External Request Unit 1"]
ERU1_2 = 7,
#[doc = "8 - External Request Unit 1"]
ERU1_3 = 8,
#[doc = "12 - Program Management Unit"]
PMU0_0 = 12,
#[doc = "14 - Analog to Digital Converter Common Block 0"]
VADC0_C0_0 = 14,
#[doc = "15 - Analog to Digital Converter Common Block 0"]
VADC0_C0_1 = 15,
#[doc = "16 - Analog to Digital Converter Common Block 0"]
VADC0_C0_2 = 16,
#[doc = "17 - Analog to Digital Converter Common Block 0"]
VADC0_C0_3 = 17,
#[doc = "18 - Analog to Digital Converter Group 0"]
VADC0_G0_0 = 18,
#[doc = "19 - Analog to Digital Converter Group 0"]
VADC0_G0_1 = 19,
#[doc = "20 - Analog to Digital Converter Group 0"]
VADC0_G0_2 = 20,
#[doc = "21 - Analog to Digital Converter Group 0"]
VADC0_G0_3 = 21,
#[doc = "22 - Analog to Digital Converter Group 1"]
VADC0_G1_0 = 22,
#[doc = "23 - Analog to Digital Converter Group 1"]
VADC0_G1_1 = 23,
#[doc = "24 - Analog to Digital Converter Group 1"]
VADC0_G1_2 = 24,
#[doc = "25 - Analog to Digital Converter Group 1"]
VADC0_G1_3 = 25,
#[doc = "26 - Analog to Digital Converter Group 2"]
VADC0_G2_0 = 26,
#[doc = "27 - Analog to Digital Converter Group 2"]
VADC0_G2_1 = 27,
#[doc = "28 - Analog to Digital Converter Group 2"]
VADC0_G2_2 = 28,
#[doc = "29 - Analog to Digital Converter Group 2"]
VADC0_G2_3 = 29,
#[doc = "30 - Analog to Digital Converter Group 3"]
VADC0_G3_0 = 30,
#[doc = "31 - Analog to Digital Converter Group 3"]
VADC0_G3_1 = 31,
#[doc = "32 - Analog to Digital Converter Group 3"]
VADC0_G3_2 = 32,
#[doc = "33 - Analog to Digital Converter Group 3"]
VADC0_G3_3 = 33,
#[doc = "34 - Delta Sigma Demodulator Main"]
DSD0_M_0 = 34,
#[doc = "35 - Delta Sigma Demodulator Main"]
DSD0_M_1 = 35,
#[doc = "36 - Delta Sigma Demodulator Main"]
DSD0_M_2 = 36,
#[doc = "37 - Delta Sigma Demodulator Main"]
DSD0_M_3 = 37,
#[doc = "38 - Delta Sigma Demodulator Auxiliary"]
DSD0_A_4 = 38,
#[doc = "39 - Delta Sigma Demodulator Auxiliary"]
DSD0_A_5 = 39,
#[doc = "40 - Delta Sigma Demodulator Auxiliary"]
DSD0_A_6 = 40,
#[doc = "41 - Delta Sigma Demodulator Auxiliary"]
DSD0_A_7 = 41,
#[doc = "42 - Digital to Analog Converter"]
DAC0_0 = 42,
#[doc = "43 - Digital to Analog Converter"]
DAC0_1 = 43,
#[doc = "44 - Capture Compare Unit 4 (Module 0)"]
CCU40_0 = 44,
#[doc = "45 - Capture Compare Unit 4 (Module 0)"]
CCU40_1 = 45,
#[doc = "46 - Capture Compare Unit 4 (Module 0)"]
CCU40_2 = 46,
#[doc = "47 - Capture Compare Unit 4 (Module 0)"]
CCU40_3 = 47,
#[doc = "48 - Capture Compare Unit 4 (Module 1)"]
CCU41_0 = 48,
#[doc = "49 - Capture Compare Unit 4 (Module 1)"]
CCU41_1 = 49,
#[doc = "50 - Capture Compare Unit 4 (Module 1)"]
CCU41_2 = 50,
#[doc = "51 - Capture Compare Unit 4 (Module 1)"]
CCU41_3 = 51,
#[doc = "52 - Capture Compare Unit 4 (Module 2)"]
CCU42_0 = 52,
#[doc = "53 - Capture Compare Unit 4 (Module 2)"]
CCU42_1 = 53,
#[doc = "54 - Capture Compare Unit 4 (Module 2)"]
CCU42_2 = 54,
#[doc = "55 - Capture Compare Unit 4 (Module 2)"]
CCU42_3 = 55,
#[doc = "56 - Capture Compare Unit 4 (Module 3)"]
CCU43_0 = 56,
#[doc = "57 - Capture Compare Unit 4 (Module 3)"]
CCU43_1 = 57,
#[doc = "58 - Capture Compare Unit 4 (Module 3)"]
CCU43_2 = 58,
#[doc = "59 - Capture Compare Unit 4 (Module 3)"]
CCU43_3 = 59,
#[doc = "60 - Capture Compare Unit 8 (Module 0)"]
CCU80_0 = 60,
#[doc = "61 - Capture Compare Unit 8 (Module 0)"]
CCU80_1 = 61,
#[doc = "62 - Capture Compare Unit 8 (Module 0)"]
CCU80_2 = 62,
#[doc = "63 - Capture Compare Unit 8 (Module 0)"]
CCU80_3 = 63,
#[doc = "64 - Capture Compare Unit 8 (Module 1)"]
CCU81_0 = 64,
#[doc = "65 - Capture Compare Unit 8 (Module 1)"]
CCU81_1 = 65,
#[doc = "66 - Capture Compare Unit 8 (Module 1)"]
CCU81_2 = 66,
#[doc = "67 - Capture Compare Unit 8 (Module 1)"]
CCU81_3 = 67,
#[doc = "68 - Position Interface (Module 0)"]
POSIF0_0 = 68,
#[doc = "69 - Position Interface (Module 0)"]
POSIF0_1 = 69,
#[doc = "70 - Position Interface (Module 1)"]
POSIF1_0 = 70,
#[doc = "71 - Position Interface (Module 1)"]
POSIF1_1 = 71,
#[doc = "76 - MultiCAN"]
CAN0_0 = 76,
#[doc = "77 - MultiCAN"]
CAN0_1 = 77,
#[doc = "78 - MultiCAN"]
CAN0_2 = 78,
#[doc = "79 - MultiCAN"]
CAN0_3 = 79,
#[doc = "80 - MultiCAN"]
CAN0_4 = 80,
#[doc = "81 - MultiCAN"]
CAN0_5 = 81,
#[doc = "82 - MultiCAN"]
CAN0_6 = 82,
#[doc = "83 - MultiCAN"]
CAN0_7 = 83,
#[doc = "84 - Universal Serial Interface Channel (Module 0)"]
USIC0_0 = 84,
#[doc = "85 - Universal Serial Interface Channel (Module 0)"]
USIC0_1 = 85,
#[doc = "86 - Universal Serial Interface Channel (Module 0)"]
USIC0_2 = 86,
#[doc = "87 - Universal Serial Interface Channel (Module 0)"]
USIC0_3 = 87,
#[doc = "88 - Universal Serial Interface Channel (Module 0)"]
USIC0_4 = 88,
#[doc = "89 - Universal Serial Interface Channel (Module 0)"]
USIC0_5 = 89,
#[doc = "90 - Universal Serial Interface Channel (Module 1)"]
USIC1_0 = 90,
#[doc = "91 - Universal Serial Interface Channel (Module 1)"]
USIC1_1 = 91,
#[doc = "92 - Universal Serial Interface Channel (Module 1)"]
USIC1_2 = 92,
#[doc = "93 - Universal Serial Interface Channel (Module 1)"]
USIC1_3 = 93,
#[doc = "94 - Universal Serial Interface Channel (Module 1)"]
USIC1_4 = 94,
#[doc = "95 - Universal Serial Interface Channel (Module 1)"]
USIC1_5 = 95,
#[doc = "96 - Universal Serial Interface Channel (Module 2)"]
USIC2_0 = 96,
#[doc = "97 - Universal Serial Interface Channel (Module 2)"]
USIC2_1 = 97,
#[doc = "98 - Universal Serial Interface Channel (Module 2)"]
USIC2_2 = 98,
#[doc = "99 - Universal Serial Interface Channel (Module 2)"]
USIC2_3 = 99,
#[doc = "100 - Universal Serial Interface Channel (Module 2)"]
USIC2_4 = 100,
#[doc = "101 - Universal Serial Interface Channel (Module 2)"]
USIC2_5 = 101,
#[doc = "102 - LED and Touch Sense Control Unit (Module 0)"]
LEDTS0_0 = 102,
#[doc = "104 - Flexible CRC Engine"]
FCE0_0 = 104,
#[doc = "105 - General Purpose DMA Unit 0"]
GPDMA0_0 = 105,
#[doc = "106 - Multi Media Card Interface"]
SDMMC0_0 = 106,
#[doc = "107 - Universal Serial Bus (Module 0)"]
USB0_0 = 107,
#[doc = "108 - Ethernet (Module 0)"]
ETH0_0 = 108,
#[doc = "109 - EtherCAT (Module 0)"]
ECAT0_0 = 109,
#[doc = "110 - General Purpose DMA Unit 1"]
GPDMA1_0 = 110,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
#[inline(always)]
fn number(self) -> u16 {
self as u16
}
}
#[doc = "Cortex-M4 Private Peripheral Block"]
pub type PPB = crate::Periph<ppb::RegisterBlock, 0xe000_e000>;
impl core::fmt::Debug for PPB {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PPB").finish()
}
}
#[doc = "Cortex-M4 Private Peripheral Block"]
pub mod ppb;
#[doc = "DMA Line Router"]
pub type DLR = crate::Periph<dlr::RegisterBlock, 0x5000_4900>;
impl core::fmt::Debug for DLR {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DLR").finish()
}
}
#[doc = "DMA Line Router"]
pub mod dlr;
#[doc = "Event Request Unit 0"]
pub type ERU0 = crate::Periph<eru0::RegisterBlock, 0x5000_4800>;
impl core::fmt::Debug for ERU0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ERU0").finish()
}
}
#[doc = "Event Request Unit 0"]
pub mod eru0;
#[doc = "Event Request Unit 1"]
pub type ERU1 = crate::Periph<eru0::RegisterBlock, 0x4004_4000>;
impl core::fmt::Debug for ERU1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ERU1").finish()
}
}
#[doc = "Event Request Unit 1"]
pub use self::eru0 as eru1;
#[doc = "General Purpose DMA Unit 0"]
pub type GPDMA0 = crate::Periph<gpdma0::RegisterBlock, 0x5001_42c0>;
impl core::fmt::Debug for GPDMA0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA0").finish()
}
}
#[doc = "General Purpose DMA Unit 0"]
pub mod gpdma0;
#[doc = "General Purpose DMA Unit 0"]
pub type GPDMA0_CH0 = crate::Periph<gpdma0_ch0::RegisterBlock, 0x5001_4000>;
impl core::fmt::Debug for GPDMA0_CH0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA0_CH0").finish()
}
}
#[doc = "General Purpose DMA Unit 0"]
pub mod gpdma0_ch0;
#[doc = "General Purpose DMA Unit 0"]
pub type GPDMA0_CH1 = crate::Periph<gpdma0_ch0::RegisterBlock, 0x5001_4058>;
impl core::fmt::Debug for GPDMA0_CH1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA0_CH1").finish()
}
}
#[doc = "General Purpose DMA Unit 0"]
pub use self::gpdma0_ch0 as gpdma0_ch1;
#[doc = "General Purpose DMA Unit 0"]
pub type GPDMA0_CH2 = crate::Periph<gpdma0_ch2::RegisterBlock, 0x5001_40b0>;
impl core::fmt::Debug for GPDMA0_CH2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA0_CH2").finish()
}
}
#[doc = "General Purpose DMA Unit 0"]
pub mod gpdma0_ch2;
#[doc = "General Purpose DMA Unit 0"]
pub type GPDMA0_CH3 = crate::Periph<gpdma0_ch2::RegisterBlock, 0x5001_4108>;
impl core::fmt::Debug for GPDMA0_CH3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA0_CH3").finish()
}
}
#[doc = "General Purpose DMA Unit 0"]
pub use self::gpdma0_ch2 as gpdma0_ch3;
#[doc = "General Purpose DMA Unit 0"]
pub type GPDMA0_CH4 = crate::Periph<gpdma0_ch2::RegisterBlock, 0x5001_4160>;
impl core::fmt::Debug for GPDMA0_CH4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA0_CH4").finish()
}
}
#[doc = "General Purpose DMA Unit 0"]
pub use self::gpdma0_ch2 as gpdma0_ch4;
#[doc = "General Purpose DMA Unit 0"]
pub type GPDMA0_CH5 = crate::Periph<gpdma0_ch2::RegisterBlock, 0x5001_41b8>;
impl core::fmt::Debug for GPDMA0_CH5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA0_CH5").finish()
}
}
#[doc = "General Purpose DMA Unit 0"]
pub use self::gpdma0_ch2 as gpdma0_ch5;
#[doc = "General Purpose DMA Unit 0"]
pub type GPDMA0_CH6 = crate::Periph<gpdma0_ch2::RegisterBlock, 0x5001_4210>;
impl core::fmt::Debug for GPDMA0_CH6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA0_CH6").finish()
}
}
#[doc = "General Purpose DMA Unit 0"]
pub use self::gpdma0_ch2 as gpdma0_ch6;
#[doc = "General Purpose DMA Unit 0"]
pub type GPDMA0_CH7 = crate::Periph<gpdma0_ch2::RegisterBlock, 0x5001_4268>;
impl core::fmt::Debug for GPDMA0_CH7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA0_CH7").finish()
}
}
#[doc = "General Purpose DMA Unit 0"]
pub use self::gpdma0_ch2 as gpdma0_ch7;
#[doc = "General Purpose DMA Unit 1"]
pub type GPDMA1 = crate::Periph<gpdma1::RegisterBlock, 0x5001_82c0>;
impl core::fmt::Debug for GPDMA1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA1").finish()
}
}
#[doc = "General Purpose DMA Unit 1"]
pub mod gpdma1;
#[doc = "General Purpose DMA Unit 1"]
pub type GPDMA1_CH0 = crate::Periph<gpdma1_ch0::RegisterBlock, 0x5001_8000>;
impl core::fmt::Debug for GPDMA1_CH0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA1_CH0").finish()
}
}
#[doc = "General Purpose DMA Unit 1"]
pub mod gpdma1_ch0;
#[doc = "General Purpose DMA Unit 1"]
pub type GPDMA1_CH1 = crate::Periph<gpdma1_ch0::RegisterBlock, 0x5001_8058>;
impl core::fmt::Debug for GPDMA1_CH1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA1_CH1").finish()
}
}
#[doc = "General Purpose DMA Unit 1"]
pub use self::gpdma1_ch0 as gpdma1_ch1;
#[doc = "General Purpose DMA Unit 1"]
pub type GPDMA1_CH2 = crate::Periph<gpdma1_ch0::RegisterBlock, 0x5001_80b0>;
impl core::fmt::Debug for GPDMA1_CH2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA1_CH2").finish()
}
}
#[doc = "General Purpose DMA Unit 1"]
pub use self::gpdma1_ch0 as gpdma1_ch2;
#[doc = "General Purpose DMA Unit 1"]
pub type GPDMA1_CH3 = crate::Periph<gpdma1_ch0::RegisterBlock, 0x5001_8108>;
impl core::fmt::Debug for GPDMA1_CH3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPDMA1_CH3").finish()
}
}
#[doc = "General Purpose DMA Unit 1"]
pub use self::gpdma1_ch0 as gpdma1_ch3;
#[doc = "Flexible CRC Engine"]
pub type FCE = crate::Periph<fce::RegisterBlock, 0x5002_0000>;
impl core::fmt::Debug for FCE {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FCE").finish()
}
}
#[doc = "Flexible CRC Engine"]
pub mod fce;
#[doc = "Flexible CRC Engine"]
pub type FCE_KE0 = crate::Periph<fce_ke0::RegisterBlock, 0x5002_0020>;
impl core::fmt::Debug for FCE_KE0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FCE_KE0").finish()
}
}
#[doc = "Flexible CRC Engine"]
pub mod fce_ke0;
#[doc = "Flexible CRC Engine"]
pub type FCE_KE1 = crate::Periph<fce_ke0::RegisterBlock, 0x5002_0040>;
impl core::fmt::Debug for FCE_KE1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FCE_KE1").finish()
}
}
#[doc = "Flexible CRC Engine"]
pub use self::fce_ke0 as fce_ke1;
#[doc = "Flexible CRC Engine"]
pub type FCE_KE2 = crate::Periph<fce_ke0::RegisterBlock, 0x5002_0060>;
impl core::fmt::Debug for FCE_KE2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FCE_KE2").finish()
}
}
#[doc = "Flexible CRC Engine"]
pub use self::fce_ke0 as fce_ke2;
#[doc = "Flexible CRC Engine"]
pub type FCE_KE3 = crate::Periph<fce_ke0::RegisterBlock, 0x5002_0080>;
impl core::fmt::Debug for FCE_KE3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FCE_KE3").finish()
}
}
#[doc = "Flexible CRC Engine"]
pub use self::fce_ke0 as fce_ke3;
#[doc = "Peripheral Bridge AHB 0"]
pub type PBA0 = crate::Periph<pba0::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for PBA0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PBA0").finish()
}
}
#[doc = "Peripheral Bridge AHB 0"]
pub mod pba0;
#[doc = "Peripheral Bridge AHB 1"]
pub type PBA1 = crate::Periph<pba0::RegisterBlock, 0x4800_0000>;
impl core::fmt::Debug for PBA1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PBA1").finish()
}
}
#[doc = "Peripheral Bridge AHB 1"]
pub use self::pba0 as pba1;
#[doc = "Flash Memory Controller"]
pub type FLASH0 = crate::Periph<flash0::RegisterBlock, 0x5800_1000>;
impl core::fmt::Debug for FLASH0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH0").finish()
}
}
#[doc = "Flash Memory Controller"]
pub mod flash0;
#[doc = "Prefetch Unit"]
pub type PREF = crate::Periph<pref::RegisterBlock, 0x5800_4000>;
impl core::fmt::Debug for PREF {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PREF").finish()
}
}
#[doc = "Prefetch Unit"]
pub mod pref;
#[doc = "Program Management Unit"]
pub type PMU0 = crate::Periph<pmu0::RegisterBlock, 0x5800_0508>;
impl core::fmt::Debug for PMU0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PMU0").finish()
}
}
#[doc = "Program Management Unit"]
pub mod pmu0;
#[doc = "Watch Dog Timer"]
pub type WDT = crate::Periph<wdt::RegisterBlock, 0x5000_8000>;
impl core::fmt::Debug for WDT {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WDT").finish()
}
}
#[doc = "Watch Dog Timer"]
pub mod wdt;
#[doc = "Real Time Clock"]
pub type RTC = crate::Periph<rtc::RegisterBlock, 0x5000_4a00>;
impl core::fmt::Debug for RTC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RTC").finish()
}
}
#[doc = "Real Time Clock"]
pub mod rtc;
#[doc = "System Control Unit"]
pub type SCU_CLK = crate::Periph<scu_clk::RegisterBlock, 0x5000_4600>;
impl core::fmt::Debug for SCU_CLK {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SCU_CLK").finish()
}
}
#[doc = "System Control Unit"]
pub mod scu_clk;
#[doc = "System Control Unit"]
pub type SCU_OSC = crate::Periph<scu_osc::RegisterBlock, 0x5000_4700>;
impl core::fmt::Debug for SCU_OSC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SCU_OSC").finish()
}
}
#[doc = "System Control Unit"]
pub mod scu_osc;
#[doc = "System Control Unit"]
pub type SCU_PLL = crate::Periph<scu_pll::RegisterBlock, 0x5000_4710>;
impl core::fmt::Debug for SCU_PLL {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SCU_PLL").finish()
}
}
#[doc = "System Control Unit"]
pub mod scu_pll;
#[doc = "System Control Unit"]
pub type SCU_GENERAL = crate::Periph<scu_general::RegisterBlock, 0x5000_4000>;
impl core::fmt::Debug for SCU_GENERAL {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SCU_GENERAL").finish()
}
}
#[doc = "System Control Unit"]
pub mod scu_general;
#[doc = "System Control Unit"]
pub type SCU_INTERRUPT = crate::Periph<scu_interrupt::RegisterBlock, 0x5000_4074>;
impl core::fmt::Debug for SCU_INTERRUPT {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SCU_INTERRUPT").finish()
}
}
#[doc = "System Control Unit"]
pub mod scu_interrupt;
#[doc = "System Control Unit"]
pub type SCU_PARITY = crate::Periph<scu_parity::RegisterBlock, 0x5000_413c>;
impl core::fmt::Debug for SCU_PARITY {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SCU_PARITY").finish()
}
}
#[doc = "System Control Unit"]
pub mod scu_parity;
#[doc = "System Control Unit"]
pub type SCU_TRAP = crate::Periph<scu_trap::RegisterBlock, 0x5000_4160>;
impl core::fmt::Debug for SCU_TRAP {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SCU_TRAP").finish()
}
}
#[doc = "System Control Unit"]
pub mod scu_trap;
#[doc = "System Control Unit"]
pub type SCU_HIBERNATE = crate::Periph<scu_hibernate::RegisterBlock, 0x5000_4300>;
impl core::fmt::Debug for SCU_HIBERNATE {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SCU_HIBERNATE").finish()
}
}
#[doc = "System Control Unit"]
pub mod scu_hibernate;
#[doc = "System Control Unit"]
pub type SCU_POWER = crate::Periph<scu_power::RegisterBlock, 0x5000_4200>;
impl core::fmt::Debug for SCU_POWER {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SCU_POWER").finish()
}
}
#[doc = "System Control Unit"]
pub mod scu_power;
#[doc = "System Control Unit"]
pub type SCU_RESET = crate::Periph<scu_reset::RegisterBlock, 0x5000_4400>;
impl core::fmt::Debug for SCU_RESET {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SCU_RESET").finish()
}
}
#[doc = "System Control Unit"]
pub mod scu_reset;
#[doc = "LED and Touch Sense Unit 0"]
pub type LEDTS0 = crate::Periph<ledts0::RegisterBlock, 0x4801_0000>;
impl core::fmt::Debug for LEDTS0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("LEDTS0").finish()
}
}
#[doc = "LED and Touch Sense Unit 0"]
pub mod ledts0;
#[doc = "SD and Multimediacard Control Register"]
pub type SDMMC_CON = crate::Periph<sdmmc_con::RegisterBlock, 0x5000_40b4>;
impl core::fmt::Debug for SDMMC_CON {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SDMMC_CON").finish()
}
}
#[doc = "SD and Multimediacard Control Register"]
pub mod sdmmc_con;
#[doc = "SD and Multimediacard Interface"]
pub type SDMMC = crate::Periph<sdmmc::RegisterBlock, 0x4801_c000>;
impl core::fmt::Debug for SDMMC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SDMMC").finish()
}
}
#[doc = "SD and Multimediacard Interface"]
pub mod sdmmc;
#[doc = "External Bus Unit"]
pub type EBU = crate::Periph<ebu::RegisterBlock, 0x5800_8000>;
impl core::fmt::Debug for EBU {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EBU").finish()
}
}
#[doc = "External Bus Unit"]
pub mod ebu;
#[doc = "Ethernet Control Register"]
pub type ETH0_CON = crate::Periph<eth0_con::RegisterBlock, 0x5000_4040>;
impl core::fmt::Debug for ETH0_CON {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ETH0_CON").finish()
}
}
#[doc = "Ethernet Control Register"]
pub mod eth0_con;
#[doc = "Ethernet Unit 0"]
pub type ETH0 = crate::Periph<eth0::RegisterBlock, 0x5000_c000>;
impl core::fmt::Debug for ETH0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ETH0").finish()
}
}
#[doc = "Ethernet Unit 0"]
pub mod eth0;
#[doc = "EtherCAT 0 Control Register"]
pub type ECAT0_CON = crate::Periph<ecat0_con::RegisterBlock, 0x5000_41b0>;
impl core::fmt::Debug for ECAT0_CON {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_CON").finish()
}
}
#[doc = "EtherCAT 0 Control Register"]
pub mod ecat0_con;
#[doc = "EtherCAT 0"]
pub type ECAT0 = crate::Periph<ecat0::RegisterBlock, 0x5401_0000>;
impl core::fmt::Debug for ECAT0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0").finish()
}
}
#[doc = "EtherCAT 0"]
pub mod ecat0;
#[doc = "EtherCAT 0"]
pub type ECAT0_FMMU0 = crate::Periph<ecat0_fmmu0::RegisterBlock, 0x5401_0600>;
impl core::fmt::Debug for ECAT0_FMMU0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_FMMU0").finish()
}
}
#[doc = "EtherCAT 0"]
pub mod ecat0_fmmu0;
#[doc = "EtherCAT 0"]
pub type ECAT0_FMMU1 = crate::Periph<ecat0_fmmu0::RegisterBlock, 0x5401_0610>;
impl core::fmt::Debug for ECAT0_FMMU1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_FMMU1").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_fmmu0 as ecat0_fmmu1;
#[doc = "EtherCAT 0"]
pub type ECAT0_FMMU2 = crate::Periph<ecat0_fmmu0::RegisterBlock, 0x5401_0620>;
impl core::fmt::Debug for ECAT0_FMMU2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_FMMU2").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_fmmu0 as ecat0_fmmu2;
#[doc = "EtherCAT 0"]
pub type ECAT0_FMMU3 = crate::Periph<ecat0_fmmu0::RegisterBlock, 0x5401_0630>;
impl core::fmt::Debug for ECAT0_FMMU3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_FMMU3").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_fmmu0 as ecat0_fmmu3;
#[doc = "EtherCAT 0"]
pub type ECAT0_FMMU4 = crate::Periph<ecat0_fmmu0::RegisterBlock, 0x5401_0640>;
impl core::fmt::Debug for ECAT0_FMMU4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_FMMU4").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_fmmu0 as ecat0_fmmu4;
#[doc = "EtherCAT 0"]
pub type ECAT0_FMMU5 = crate::Periph<ecat0_fmmu0::RegisterBlock, 0x5401_0650>;
impl core::fmt::Debug for ECAT0_FMMU5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_FMMU5").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_fmmu0 as ecat0_fmmu5;
#[doc = "EtherCAT 0"]
pub type ECAT0_FMMU6 = crate::Periph<ecat0_fmmu0::RegisterBlock, 0x5401_0660>;
impl core::fmt::Debug for ECAT0_FMMU6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_FMMU6").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_fmmu0 as ecat0_fmmu6;
#[doc = "EtherCAT 0"]
pub type ECAT0_FMMU7 = crate::Periph<ecat0_fmmu0::RegisterBlock, 0x5401_0670>;
impl core::fmt::Debug for ECAT0_FMMU7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_FMMU7").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_fmmu0 as ecat0_fmmu7;
#[doc = "EtherCAT 0"]
pub type ECAT0_SM0 = crate::Periph<ecat0_sm0::RegisterBlock, 0x5401_0800>;
impl core::fmt::Debug for ECAT0_SM0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_SM0").finish()
}
}
#[doc = "EtherCAT 0"]
pub mod ecat0_sm0;
#[doc = "EtherCAT 0"]
pub type ECAT0_SM1 = crate::Periph<ecat0_sm0::RegisterBlock, 0x5401_0808>;
impl core::fmt::Debug for ECAT0_SM1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_SM1").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_sm0 as ecat0_sm1;
#[doc = "EtherCAT 0"]
pub type ECAT0_SM2 = crate::Periph<ecat0_sm0::RegisterBlock, 0x5401_0810>;
impl core::fmt::Debug for ECAT0_SM2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_SM2").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_sm0 as ecat0_sm2;
#[doc = "EtherCAT 0"]
pub type ECAT0_SM3 = crate::Periph<ecat0_sm0::RegisterBlock, 0x5401_0818>;
impl core::fmt::Debug for ECAT0_SM3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_SM3").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_sm0 as ecat0_sm3;
#[doc = "EtherCAT 0"]
pub type ECAT0_SM4 = crate::Periph<ecat0_sm0::RegisterBlock, 0x5401_0820>;
impl core::fmt::Debug for ECAT0_SM4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_SM4").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_sm0 as ecat0_sm4;
#[doc = "EtherCAT 0"]
pub type ECAT0_SM5 = crate::Periph<ecat0_sm0::RegisterBlock, 0x5401_0828>;
impl core::fmt::Debug for ECAT0_SM5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_SM5").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_sm0 as ecat0_sm5;
#[doc = "EtherCAT 0"]
pub type ECAT0_SM6 = crate::Periph<ecat0_sm0::RegisterBlock, 0x5401_0830>;
impl core::fmt::Debug for ECAT0_SM6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_SM6").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_sm0 as ecat0_sm6;
#[doc = "EtherCAT 0"]
pub type ECAT0_SM7 = crate::Periph<ecat0_sm0::RegisterBlock, 0x5401_0838>;
impl core::fmt::Debug for ECAT0_SM7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ECAT0_SM7").finish()
}
}
#[doc = "EtherCAT 0"]
pub use self::ecat0_sm0 as ecat0_sm7;
#[doc = "Universal Serial Bus"]
pub type USB0 = crate::Periph<usb0::RegisterBlock, 0x5004_0000>;
impl core::fmt::Debug for USB0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0").finish()
}
}
#[doc = "Universal Serial Bus"]
pub mod usb0;
#[doc = "Universal Serial Bus"]
pub type USB0_EP0 = crate::Periph<usb0_ep0::RegisterBlock, 0x5004_0900>;
impl core::fmt::Debug for USB0_EP0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_EP0").finish()
}
}
#[doc = "Universal Serial Bus"]
pub mod usb0_ep0;
#[doc = "Universal Serial Bus"]
pub type USB0_EP1 = crate::Periph<usb0_ep1::RegisterBlock, 0x5004_0920>;
impl core::fmt::Debug for USB0_EP1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_EP1").finish()
}
}
#[doc = "Universal Serial Bus"]
pub mod usb0_ep1;
#[doc = "Universal Serial Bus"]
pub type USB0_EP2 = crate::Periph<usb0_ep1::RegisterBlock, 0x5004_0940>;
impl core::fmt::Debug for USB0_EP2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_EP2").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ep1 as usb0_ep2;
#[doc = "Universal Serial Bus"]
pub type USB0_EP3 = crate::Periph<usb0_ep1::RegisterBlock, 0x5004_0960>;
impl core::fmt::Debug for USB0_EP3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_EP3").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ep1 as usb0_ep3;
#[doc = "Universal Serial Bus"]
pub type USB0_EP4 = crate::Periph<usb0_ep1::RegisterBlock, 0x5004_0980>;
impl core::fmt::Debug for USB0_EP4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_EP4").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ep1 as usb0_ep4;
#[doc = "Universal Serial Bus"]
pub type USB0_EP5 = crate::Periph<usb0_ep1::RegisterBlock, 0x5004_09a0>;
impl core::fmt::Debug for USB0_EP5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_EP5").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ep1 as usb0_ep5;
#[doc = "Universal Serial Bus"]
pub type USB0_EP6 = crate::Periph<usb0_ep1::RegisterBlock, 0x5004_09c0>;
impl core::fmt::Debug for USB0_EP6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_EP6").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ep1 as usb0_ep6;
#[doc = "Universal Serial Bus"]
pub type USB0_CH0 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_0500>;
impl core::fmt::Debug for USB0_CH0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH0").finish()
}
}
#[doc = "Universal Serial Bus"]
pub mod usb0_ch0;
#[doc = "Universal Serial Bus"]
pub type USB0_CH1 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_0520>;
impl core::fmt::Debug for USB0_CH1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH1").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch1;
#[doc = "Universal Serial Bus"]
pub type USB0_CH2 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_0540>;
impl core::fmt::Debug for USB0_CH2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH2").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch2;
#[doc = "Universal Serial Bus"]
pub type USB0_CH3 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_0560>;
impl core::fmt::Debug for USB0_CH3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH3").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch3;
#[doc = "Universal Serial Bus"]
pub type USB0_CH4 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_0580>;
impl core::fmt::Debug for USB0_CH4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH4").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch4;
#[doc = "Universal Serial Bus"]
pub type USB0_CH5 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_05a0>;
impl core::fmt::Debug for USB0_CH5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH5").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch5;
#[doc = "Universal Serial Bus"]
pub type USB0_CH6 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_05c0>;
impl core::fmt::Debug for USB0_CH6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH6").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch6;
#[doc = "Universal Serial Bus"]
pub type USB0_CH7 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_05e0>;
impl core::fmt::Debug for USB0_CH7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH7").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch7;
#[doc = "Universal Serial Bus"]
pub type USB0_CH8 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_0600>;
impl core::fmt::Debug for USB0_CH8 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH8").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch8;
#[doc = "Universal Serial Bus"]
pub type USB0_CH9 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_0620>;
impl core::fmt::Debug for USB0_CH9 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH9").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch9;
#[doc = "Universal Serial Bus"]
pub type USB0_CH10 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_0640>;
impl core::fmt::Debug for USB0_CH10 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH10").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch10;
#[doc = "Universal Serial Bus"]
pub type USB0_CH11 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_0660>;
impl core::fmt::Debug for USB0_CH11 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH11").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch11;
#[doc = "Universal Serial Bus"]
pub type USB0_CH12 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_0680>;
impl core::fmt::Debug for USB0_CH12 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH12").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch12;
#[doc = "Universal Serial Bus"]
pub type USB0_CH13 = crate::Periph<usb0_ch0::RegisterBlock, 0x5004_06a0>;
impl core::fmt::Debug for USB0_CH13 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB0_CH13").finish()
}
}
#[doc = "Universal Serial Bus"]
pub use self::usb0_ch0 as usb0_ch13;
#[doc = "Universal Serial Interface Controller 0"]
pub type USIC0 = crate::Periph<usic0::RegisterBlock, 0x4003_0008>;
impl core::fmt::Debug for USIC0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USIC0").finish()
}
}
#[doc = "Universal Serial Interface Controller 0"]
pub mod usic0;
#[doc = "Universal Serial Interface Controller 1"]
pub type USIC1 = crate::Periph<usic0::RegisterBlock, 0x4802_0008>;
impl core::fmt::Debug for USIC1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USIC1").finish()
}
}
#[doc = "Universal Serial Interface Controller 1"]
pub use self::usic0 as usic1;
#[doc = "Universal Serial Interface Controller 2"]
pub type USIC2 = crate::Periph<usic0::RegisterBlock, 0x4802_4008>;
impl core::fmt::Debug for USIC2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USIC2").finish()
}
}
#[doc = "Universal Serial Interface Controller 2"]
pub use self::usic0 as usic2;
#[doc = "Universal Serial Interface Controller 0"]
pub type USIC0_CH0 = crate::Periph<usic0_ch0::RegisterBlock, 0x4003_0000>;
impl core::fmt::Debug for USIC0_CH0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USIC0_CH0").finish()
}
}
#[doc = "Universal Serial Interface Controller 0"]
pub mod usic0_ch0;
#[doc = "Universal Serial Interface Controller 0"]
pub type USIC0_CH1 = crate::Periph<usic0_ch0::RegisterBlock, 0x4003_0200>;
impl core::fmt::Debug for USIC0_CH1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USIC0_CH1").finish()
}
}
#[doc = "Universal Serial Interface Controller 0"]
pub use self::usic0_ch0 as usic0_ch1;
#[doc = "Universal Serial Interface Controller 0"]
pub type USIC1_CH0 = crate::Periph<usic0_ch0::RegisterBlock, 0x4802_0000>;
impl core::fmt::Debug for USIC1_CH0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USIC1_CH0").finish()
}
}
#[doc = "Universal Serial Interface Controller 0"]
pub use self::usic0_ch0 as usic1_ch0;
#[doc = "Universal Serial Interface Controller 0"]
pub type USIC1_CH1 = crate::Periph<usic0_ch0::RegisterBlock, 0x4802_0200>;
impl core::fmt::Debug for USIC1_CH1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USIC1_CH1").finish()
}
}
#[doc = "Universal Serial Interface Controller 0"]
pub use self::usic0_ch0 as usic1_ch1;
#[doc = "Universal Serial Interface Controller 0"]
pub type USIC2_CH0 = crate::Periph<usic0_ch0::RegisterBlock, 0x4802_4000>;
impl core::fmt::Debug for USIC2_CH0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USIC2_CH0").finish()
}
}
#[doc = "Universal Serial Interface Controller 0"]
pub use self::usic0_ch0 as usic2_ch0;
#[doc = "Universal Serial Interface Controller 0"]
pub type USIC2_CH1 = crate::Periph<usic0_ch0::RegisterBlock, 0x4802_4200>;
impl core::fmt::Debug for USIC2_CH1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USIC2_CH1").finish()
}
}
#[doc = "Universal Serial Interface Controller 0"]
pub use self::usic0_ch0 as usic2_ch1;
#[doc = "Controller Area Networks"]
pub type CAN = crate::Periph<can::RegisterBlock, 0x4801_4000>;
impl core::fmt::Debug for CAN {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN").finish()
}
}
#[doc = "Controller Area Networks"]
pub mod can;
#[doc = "Controller Area Networks"]
pub type CAN_NODE0 = crate::Periph<can_node0::RegisterBlock, 0x4801_4200>;
impl core::fmt::Debug for CAN_NODE0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN_NODE0").finish()
}
}
#[doc = "Controller Area Networks"]
pub mod can_node0;
#[doc = "Controller Area Networks"]
pub type CAN_NODE1 = crate::Periph<can_node0::RegisterBlock, 0x4801_4300>;
impl core::fmt::Debug for CAN_NODE1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN_NODE1").finish()
}
}
#[doc = "Controller Area Networks"]
pub use self::can_node0 as can_node1;
#[doc = "Controller Area Networks"]
pub type CAN_NODE2 = crate::Periph<can_node0::RegisterBlock, 0x4801_4400>;
impl core::fmt::Debug for CAN_NODE2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN_NODE2").finish()
}
}
#[doc = "Controller Area Networks"]
pub use self::can_node0 as can_node2;
#[doc = "Controller Area Networks"]
pub type CAN_NODE3 = crate::Periph<can_node0::RegisterBlock, 0x4801_4500>;
impl core::fmt::Debug for CAN_NODE3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN_NODE3").finish()
}
}
#[doc = "Controller Area Networks"]
pub use self::can_node0 as can_node3;
#[doc = "Controller Area Networks"]
pub type CAN_NODE4 = crate::Periph<can_node0::RegisterBlock, 0x4801_4600>;
impl core::fmt::Debug for CAN_NODE4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN_NODE4").finish()
}
}
#[doc = "Controller Area Networks"]
pub use self::can_node0 as can_node4;
#[doc = "Controller Area Networks"]
pub type CAN_NODE5 = crate::Periph<can_node0::RegisterBlock, 0x4801_4700>;
impl core::fmt::Debug for CAN_NODE5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN_NODE5").finish()
}
}
#[doc = "Controller Area Networks"]
pub use self::can_node0 as can_node5;
#[doc = "Controller Area Networks"]
pub type CAN_MO = crate::Periph<can_mo::RegisterBlock, 0x4801_5000>;
impl core::fmt::Debug for CAN_MO {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CAN_MO").finish()
}
}
#[doc = "Controller Area Networks"]
pub mod can_mo;
#[doc = "Analog to Digital Converter"]
pub type VADC = crate::Periph<vadc::RegisterBlock, 0x4000_4000>;
impl core::fmt::Debug for VADC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("VADC").finish()
}
}
#[doc = "Analog to Digital Converter"]
pub mod vadc;
#[doc = "Analog to Digital Converter"]
pub type VADC_G0 = crate::Periph<vadc_g0::RegisterBlock, 0x4000_4400>;
impl core::fmt::Debug for VADC_G0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("VADC_G0").finish()
}
}
#[doc = "Analog to Digital Converter"]
pub mod vadc_g0;
#[doc = "Analog to Digital Converter"]
pub type VADC_G1 = crate::Periph<vadc_g0::RegisterBlock, 0x4000_4800>;
impl core::fmt::Debug for VADC_G1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("VADC_G1").finish()
}
}
#[doc = "Analog to Digital Converter"]
pub use self::vadc_g0 as vadc_g1;
#[doc = "Analog to Digital Converter"]
pub type VADC_G2 = crate::Periph<vadc_g0::RegisterBlock, 0x4000_4c00>;
impl core::fmt::Debug for VADC_G2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("VADC_G2").finish()
}
}
#[doc = "Analog to Digital Converter"]
pub use self::vadc_g0 as vadc_g2;
#[doc = "Analog to Digital Converter"]
pub type VADC_G3 = crate::Periph<vadc_g0::RegisterBlock, 0x4000_5000>;
impl core::fmt::Debug for VADC_G3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("VADC_G3").finish()
}
}
#[doc = "Analog to Digital Converter"]
pub use self::vadc_g0 as vadc_g3;
#[doc = "Delta Sigma Demodulator"]
pub type DSD = crate::Periph<dsd::RegisterBlock, 0x4000_8000>;
impl core::fmt::Debug for DSD {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DSD").finish()
}
}
#[doc = "Delta Sigma Demodulator"]
pub mod dsd;
#[doc = "Delta Sigma Demodulator"]
pub type DSD_CH0 = crate::Periph<dsd_ch0::RegisterBlock, 0x4000_8100>;
impl core::fmt::Debug for DSD_CH0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DSD_CH0").finish()
}
}
#[doc = "Delta Sigma Demodulator"]
pub mod dsd_ch0;
#[doc = "Delta Sigma Demodulator"]
pub type DSD_CH1 = crate::Periph<dsd_ch0::RegisterBlock, 0x4000_8200>;
impl core::fmt::Debug for DSD_CH1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DSD_CH1").finish()
}
}
#[doc = "Delta Sigma Demodulator"]
pub use self::dsd_ch0 as dsd_ch1;
#[doc = "Delta Sigma Demodulator"]
pub type DSD_CH2 = crate::Periph<dsd_ch0::RegisterBlock, 0x4000_8300>;
impl core::fmt::Debug for DSD_CH2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DSD_CH2").finish()
}
}
#[doc = "Delta Sigma Demodulator"]
pub use self::dsd_ch0 as dsd_ch2;
#[doc = "Delta Sigma Demodulator"]
pub type DSD_CH3 = crate::Periph<dsd_ch0::RegisterBlock, 0x4000_8400>;
impl core::fmt::Debug for DSD_CH3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DSD_CH3").finish()
}
}
#[doc = "Delta Sigma Demodulator"]
pub use self::dsd_ch0 as dsd_ch3;
#[doc = "Digital to Analog Converter"]
pub type DAC = crate::Periph<dac::RegisterBlock, 0x4801_8000>;
impl core::fmt::Debug for DAC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DAC").finish()
}
}
#[doc = "Digital to Analog Converter"]
pub mod dac;
#[doc = "Capture Compare Unit 4 - Unit 0"]
pub type CCU40 = crate::Periph<ccu40::RegisterBlock, 0x4000_c000>;
impl core::fmt::Debug for CCU40 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU40").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 0"]
pub mod ccu40;
#[doc = "Capture Compare Unit 4 - Unit 1"]
pub type CCU41 = crate::Periph<ccu40::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for CCU41 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU41").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 1"]
pub use self::ccu40 as ccu41;
#[doc = "Capture Compare Unit 4 - Unit 2"]
pub type CCU42 = crate::Periph<ccu40::RegisterBlock, 0x4001_4000>;
impl core::fmt::Debug for CCU42 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU42").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 2"]
pub use self::ccu40 as ccu42;
#[doc = "Capture Compare Unit 4 - Unit 3"]
pub type CCU43 = crate::Periph<ccu40::RegisterBlock, 0x4800_4000>;
impl core::fmt::Debug for CCU43 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU43").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 3"]
pub use self::ccu40 as ccu43;
#[doc = "Capture Compare Unit 4 - Unit 0"]
pub type CCU40_CC40 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4000_c100>;
impl core::fmt::Debug for CCU40_CC40 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU40_CC40").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 0"]
pub mod ccu40_cc40;
#[doc = "Capture Compare Unit 4 - Unit 0"]
pub type CCU40_CC41 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4000_c200>;
impl core::fmt::Debug for CCU40_CC41 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU40_CC41").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 0"]
pub use self::ccu40_cc40 as ccu40_cc41;
#[doc = "Capture Compare Unit 4 - Unit 0"]
pub type CCU40_CC42 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4000_c300>;
impl core::fmt::Debug for CCU40_CC42 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU40_CC42").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 0"]
pub use self::ccu40_cc40 as ccu40_cc42;
#[doc = "Capture Compare Unit 4 - Unit 0"]
pub type CCU40_CC43 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4000_c400>;
impl core::fmt::Debug for CCU40_CC43 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU40_CC43").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 0"]
pub use self::ccu40_cc40 as ccu40_cc43;
#[doc = "Capture Compare Unit 4 - Unit 1"]
pub type CCU41_CC40 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4001_0100>;
impl core::fmt::Debug for CCU41_CC40 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU41_CC40").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 1"]
pub use self::ccu40_cc40 as ccu41_cc40;
#[doc = "Capture Compare Unit 4 - Unit 1"]
pub type CCU41_CC41 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4001_0200>;
impl core::fmt::Debug for CCU41_CC41 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU41_CC41").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 1"]
pub use self::ccu40_cc40 as ccu41_cc41;
#[doc = "Capture Compare Unit 4 - Unit 1"]
pub type CCU41_CC42 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4001_0300>;
impl core::fmt::Debug for CCU41_CC42 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU41_CC42").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 1"]
pub use self::ccu40_cc40 as ccu41_cc42;
#[doc = "Capture Compare Unit 4 - Unit 1"]
pub type CCU41_CC43 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4001_0400>;
impl core::fmt::Debug for CCU41_CC43 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU41_CC43").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 1"]
pub use self::ccu40_cc40 as ccu41_cc43;
#[doc = "Capture Compare Unit 4 - Unit 2"]
pub type CCU42_CC40 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4001_4100>;
impl core::fmt::Debug for CCU42_CC40 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU42_CC40").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 2"]
pub use self::ccu40_cc40 as ccu42_cc40;
#[doc = "Capture Compare Unit 4 - Unit 2"]
pub type CCU42_CC41 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4001_4200>;
impl core::fmt::Debug for CCU42_CC41 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU42_CC41").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 2"]
pub use self::ccu40_cc40 as ccu42_cc41;
#[doc = "Capture Compare Unit 4 - Unit 2"]
pub type CCU42_CC42 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4001_4300>;
impl core::fmt::Debug for CCU42_CC42 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU42_CC42").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 2"]
pub use self::ccu40_cc40 as ccu42_cc42;
#[doc = "Capture Compare Unit 4 - Unit 2"]
pub type CCU42_CC43 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4001_4400>;
impl core::fmt::Debug for CCU42_CC43 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU42_CC43").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 2"]
pub use self::ccu40_cc40 as ccu42_cc43;
#[doc = "Capture Compare Unit 4 - Unit 3"]
pub type CCU43_CC40 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4800_4100>;
impl core::fmt::Debug for CCU43_CC40 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU43_CC40").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 3"]
pub use self::ccu40_cc40 as ccu43_cc40;
#[doc = "Capture Compare Unit 4 - Unit 3"]
pub type CCU43_CC41 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4800_4200>;
impl core::fmt::Debug for CCU43_CC41 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU43_CC41").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 3"]
pub use self::ccu40_cc40 as ccu43_cc41;
#[doc = "Capture Compare Unit 4 - Unit 3"]
pub type CCU43_CC42 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4800_4300>;
impl core::fmt::Debug for CCU43_CC42 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU43_CC42").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 3"]
pub use self::ccu40_cc40 as ccu43_cc42;
#[doc = "Capture Compare Unit 4 - Unit 3"]
pub type CCU43_CC43 = crate::Periph<ccu40_cc40::RegisterBlock, 0x4800_4400>;
impl core::fmt::Debug for CCU43_CC43 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU43_CC43").finish()
}
}
#[doc = "Capture Compare Unit 4 - Unit 3"]
pub use self::ccu40_cc40 as ccu43_cc43;
#[doc = "Capture Compare Unit 8 - Unit 0"]
pub type CCU80 = crate::Periph<ccu80::RegisterBlock, 0x4002_0000>;
impl core::fmt::Debug for CCU80 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU80").finish()
}
}
#[doc = "Capture Compare Unit 8 - Unit 0"]
pub mod ccu80;
#[doc = "Capture Compare Unit 8 - Unit 1"]
pub type CCU81 = crate::Periph<ccu80::RegisterBlock, 0x4002_4000>;
impl core::fmt::Debug for CCU81 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU81").finish()
}
}
#[doc = "Capture Compare Unit 8 - Unit 1"]
pub use self::ccu80 as ccu81;
#[doc = "Capture Compare Unit 8 - Unit 0"]
pub type CCU80_CC80 = crate::Periph<ccu80_cc80::RegisterBlock, 0x4002_0100>;
impl core::fmt::Debug for CCU80_CC80 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU80_CC80").finish()
}
}
#[doc = "Capture Compare Unit 8 - Unit 0"]
pub mod ccu80_cc80;
#[doc = "Capture Compare Unit 8 - Unit 0"]
pub type CCU80_CC81 = crate::Periph<ccu80_cc80::RegisterBlock, 0x4002_0200>;
impl core::fmt::Debug for CCU80_CC81 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU80_CC81").finish()
}
}
#[doc = "Capture Compare Unit 8 - Unit 0"]
pub use self::ccu80_cc80 as ccu80_cc81;
#[doc = "Capture Compare Unit 8 - Unit 0"]
pub type CCU80_CC82 = crate::Periph<ccu80_cc80::RegisterBlock, 0x4002_0300>;
impl core::fmt::Debug for CCU80_CC82 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU80_CC82").finish()
}
}
#[doc = "Capture Compare Unit 8 - Unit 0"]
pub use self::ccu80_cc80 as ccu80_cc82;
#[doc = "Capture Compare Unit 8 - Unit 0"]
pub type CCU80_CC83 = crate::Periph<ccu80_cc80::RegisterBlock, 0x4002_0400>;
impl core::fmt::Debug for CCU80_CC83 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU80_CC83").finish()
}
}
#[doc = "Capture Compare Unit 8 - Unit 0"]
pub use self::ccu80_cc80 as ccu80_cc83;
#[doc = "Capture Compare Unit 8 - Unit 1"]
pub type CCU81_CC80 = crate::Periph<ccu80_cc80::RegisterBlock, 0x4002_4100>;
impl core::fmt::Debug for CCU81_CC80 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU81_CC80").finish()
}
}
#[doc = "Capture Compare Unit 8 - Unit 1"]
pub use self::ccu80_cc80 as ccu81_cc80;
#[doc = "Capture Compare Unit 8 - Unit 1"]
pub type CCU81_CC81 = crate::Periph<ccu80_cc80::RegisterBlock, 0x4002_4200>;
impl core::fmt::Debug for CCU81_CC81 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU81_CC81").finish()
}
}
#[doc = "Capture Compare Unit 8 - Unit 1"]
pub use self::ccu80_cc80 as ccu81_cc81;
#[doc = "Capture Compare Unit 8 - Unit 1"]
pub type CCU81_CC82 = crate::Periph<ccu80_cc80::RegisterBlock, 0x4002_4300>;
impl core::fmt::Debug for CCU81_CC82 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU81_CC82").finish()
}
}
#[doc = "Capture Compare Unit 8 - Unit 1"]
pub use self::ccu80_cc80 as ccu81_cc82;
#[doc = "Capture Compare Unit 8 - Unit 1"]
pub type CCU81_CC83 = crate::Periph<ccu80_cc80::RegisterBlock, 0x4002_4400>;
impl core::fmt::Debug for CCU81_CC83 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CCU81_CC83").finish()
}
}
#[doc = "Capture Compare Unit 8 - Unit 1"]
pub use self::ccu80_cc80 as ccu81_cc83;
#[doc = "Position Interface 0"]
pub type POSIF0 = crate::Periph<posif0::RegisterBlock, 0x4002_8000>;
impl core::fmt::Debug for POSIF0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("POSIF0").finish()
}
}
#[doc = "Position Interface 0"]
pub mod posif0;
#[doc = "Position Interface 1"]
pub type POSIF1 = crate::Periph<posif0::RegisterBlock, 0x4002_c000>;
impl core::fmt::Debug for POSIF1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("POSIF1").finish()
}
}
#[doc = "Position Interface 1"]
pub use self::posif0 as posif1;
#[doc = "Port 0"]
pub type PORT0 = crate::Periph<port0::RegisterBlock, 0x4802_8000>;
impl core::fmt::Debug for PORT0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PORT0").finish()
}
}
#[doc = "Port 0"]
pub mod port0;
#[doc = "Port 1"]
pub type PORT1 = crate::Periph<port1::RegisterBlock, 0x4802_8100>;
impl core::fmt::Debug for PORT1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PORT1").finish()
}
}
#[doc = "Port 1"]
pub mod port1;
#[doc = "Port 2"]
pub type PORT2 = crate::Periph<port2::RegisterBlock, 0x4802_8200>;
impl core::fmt::Debug for PORT2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PORT2").finish()
}
}
#[doc = "Port 2"]
pub mod port2;
#[doc = "Port 3"]
pub type PORT3 = crate::Periph<port3::RegisterBlock, 0x4802_8300>;
impl core::fmt::Debug for PORT3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PORT3").finish()
}
}
#[doc = "Port 3"]
pub mod port3;
#[doc = "Port 4"]
pub type PORT4 = crate::Periph<port4::RegisterBlock, 0x4802_8400>;
impl core::fmt::Debug for PORT4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PORT4").finish()
}
}
#[doc = "Port 4"]
pub mod port4;
#[doc = "Port 5"]
pub type PORT5 = crate::Periph<port5::RegisterBlock, 0x4802_8500>;
impl core::fmt::Debug for PORT5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PORT5").finish()
}
}
#[doc = "Port 5"]
pub mod port5;
#[doc = "Port 6"]
pub type PORT6 = crate::Periph<port6::RegisterBlock, 0x4802_8600>;
impl core::fmt::Debug for PORT6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PORT6").finish()
}
}
#[doc = "Port 6"]
pub mod port6;
#[doc = "Port 7"]
pub type PORT7 = crate::Periph<port7::RegisterBlock, 0x4802_8700>;
impl core::fmt::Debug for PORT7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PORT7").finish()
}
}
#[doc = "Port 7"]
pub mod port7;
#[doc = "Port 8"]
pub type PORT8 = crate::Periph<port8::RegisterBlock, 0x4802_8800>;
impl core::fmt::Debug for PORT8 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PORT8").finish()
}
}
#[doc = "Port 8"]
pub mod port8;
#[doc = "Port 9"]
pub type PORT9 = crate::Periph<port9::RegisterBlock, 0x4802_8900>;
impl core::fmt::Debug for PORT9 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PORT9").finish()
}
}
#[doc = "Port 9"]
pub mod port9;
#[doc = "Port 14"]
pub type PORT14 = crate::Periph<port14::RegisterBlock, 0x4802_8e00>;
impl core::fmt::Debug for PORT14 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PORT14").finish()
}
}
#[doc = "Port 14"]
pub mod port14;
#[doc = "Port 15"]
pub type PORT15 = crate::Periph<port15::RegisterBlock, 0x4802_8f00>;
impl core::fmt::Debug for PORT15 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PORT15").finish()
}
}
#[doc = "Port 15"]
pub mod port15;
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals."]
#[allow(non_snake_case)]
pub struct Peripherals {
#[doc = "PPB"]
pub PPB: PPB,
#[doc = "DLR"]
pub DLR: DLR,
#[doc = "ERU0"]
pub ERU0: ERU0,
#[doc = "ERU1"]
pub ERU1: ERU1,
#[doc = "GPDMA0"]
pub GPDMA0: GPDMA0,
#[doc = "GPDMA0_CH0"]
pub GPDMA0_CH0: GPDMA0_CH0,
#[doc = "GPDMA0_CH1"]
pub GPDMA0_CH1: GPDMA0_CH1,
#[doc = "GPDMA0_CH2"]
pub GPDMA0_CH2: GPDMA0_CH2,
#[doc = "GPDMA0_CH3"]
pub GPDMA0_CH3: GPDMA0_CH3,
#[doc = "GPDMA0_CH4"]
pub GPDMA0_CH4: GPDMA0_CH4,
#[doc = "GPDMA0_CH5"]
pub GPDMA0_CH5: GPDMA0_CH5,
#[doc = "GPDMA0_CH6"]
pub GPDMA0_CH6: GPDMA0_CH6,
#[doc = "GPDMA0_CH7"]
pub GPDMA0_CH7: GPDMA0_CH7,
#[doc = "GPDMA1"]
pub GPDMA1: GPDMA1,
#[doc = "GPDMA1_CH0"]
pub GPDMA1_CH0: GPDMA1_CH0,
#[doc = "GPDMA1_CH1"]
pub GPDMA1_CH1: GPDMA1_CH1,
#[doc = "GPDMA1_CH2"]
pub GPDMA1_CH2: GPDMA1_CH2,
#[doc = "GPDMA1_CH3"]
pub GPDMA1_CH3: GPDMA1_CH3,
#[doc = "FCE"]
pub FCE: FCE,
#[doc = "FCE_KE0"]
pub FCE_KE0: FCE_KE0,
#[doc = "FCE_KE1"]
pub FCE_KE1: FCE_KE1,
#[doc = "FCE_KE2"]
pub FCE_KE2: FCE_KE2,
#[doc = "FCE_KE3"]
pub FCE_KE3: FCE_KE3,
#[doc = "PBA0"]
pub PBA0: PBA0,
#[doc = "PBA1"]
pub PBA1: PBA1,
#[doc = "FLASH0"]
pub FLASH0: FLASH0,
#[doc = "PREF"]
pub PREF: PREF,
#[doc = "PMU0"]
pub PMU0: PMU0,
#[doc = "WDT"]
pub WDT: WDT,
#[doc = "RTC"]
pub RTC: RTC,
#[doc = "SCU_CLK"]
pub SCU_CLK: SCU_CLK,
#[doc = "SCU_OSC"]
pub SCU_OSC: SCU_OSC,
#[doc = "SCU_PLL"]
pub SCU_PLL: SCU_PLL,
#[doc = "SCU_GENERAL"]
pub SCU_GENERAL: SCU_GENERAL,
#[doc = "SCU_INTERRUPT"]
pub SCU_INTERRUPT: SCU_INTERRUPT,
#[doc = "SCU_PARITY"]
pub SCU_PARITY: SCU_PARITY,
#[doc = "SCU_TRAP"]
pub SCU_TRAP: SCU_TRAP,
#[doc = "SCU_HIBERNATE"]
pub SCU_HIBERNATE: SCU_HIBERNATE,
#[doc = "SCU_POWER"]
pub SCU_POWER: SCU_POWER,
#[doc = "SCU_RESET"]
pub SCU_RESET: SCU_RESET,
#[doc = "LEDTS0"]
pub LEDTS0: LEDTS0,
#[doc = "SDMMC_CON"]
pub SDMMC_CON: SDMMC_CON,
#[doc = "SDMMC"]
pub SDMMC: SDMMC,
#[doc = "EBU"]
pub EBU: EBU,
#[doc = "ETH0_CON"]
pub ETH0_CON: ETH0_CON,
#[doc = "ETH0"]
pub ETH0: ETH0,
#[doc = "ECAT0_CON"]
pub ECAT0_CON: ECAT0_CON,
#[doc = "ECAT0"]
pub ECAT0: ECAT0,
#[doc = "ECAT0_FMMU0"]
pub ECAT0_FMMU0: ECAT0_FMMU0,
#[doc = "ECAT0_FMMU1"]
pub ECAT0_FMMU1: ECAT0_FMMU1,
#[doc = "ECAT0_FMMU2"]
pub ECAT0_FMMU2: ECAT0_FMMU2,
#[doc = "ECAT0_FMMU3"]
pub ECAT0_FMMU3: ECAT0_FMMU3,
#[doc = "ECAT0_FMMU4"]
pub ECAT0_FMMU4: ECAT0_FMMU4,
#[doc = "ECAT0_FMMU5"]
pub ECAT0_FMMU5: ECAT0_FMMU5,
#[doc = "ECAT0_FMMU6"]
pub ECAT0_FMMU6: ECAT0_FMMU6,
#[doc = "ECAT0_FMMU7"]
pub ECAT0_FMMU7: ECAT0_FMMU7,
#[doc = "ECAT0_SM0"]
pub ECAT0_SM0: ECAT0_SM0,
#[doc = "ECAT0_SM1"]
pub ECAT0_SM1: ECAT0_SM1,
#[doc = "ECAT0_SM2"]
pub ECAT0_SM2: ECAT0_SM2,
#[doc = "ECAT0_SM3"]
pub ECAT0_SM3: ECAT0_SM3,
#[doc = "ECAT0_SM4"]
pub ECAT0_SM4: ECAT0_SM4,
#[doc = "ECAT0_SM5"]
pub ECAT0_SM5: ECAT0_SM5,
#[doc = "ECAT0_SM6"]
pub ECAT0_SM6: ECAT0_SM6,
#[doc = "ECAT0_SM7"]
pub ECAT0_SM7: ECAT0_SM7,
#[doc = "USB0"]
pub USB0: USB0,
#[doc = "USB0_EP0"]
pub USB0_EP0: USB0_EP0,
#[doc = "USB0_EP1"]
pub USB0_EP1: USB0_EP1,
#[doc = "USB0_EP2"]
pub USB0_EP2: USB0_EP2,
#[doc = "USB0_EP3"]
pub USB0_EP3: USB0_EP3,
#[doc = "USB0_EP4"]
pub USB0_EP4: USB0_EP4,
#[doc = "USB0_EP5"]
pub USB0_EP5: USB0_EP5,
#[doc = "USB0_EP6"]
pub USB0_EP6: USB0_EP6,
#[doc = "USB0_CH0"]
pub USB0_CH0: USB0_CH0,
#[doc = "USB0_CH1"]
pub USB0_CH1: USB0_CH1,
#[doc = "USB0_CH2"]
pub USB0_CH2: USB0_CH2,
#[doc = "USB0_CH3"]
pub USB0_CH3: USB0_CH3,
#[doc = "USB0_CH4"]
pub USB0_CH4: USB0_CH4,
#[doc = "USB0_CH5"]
pub USB0_CH5: USB0_CH5,
#[doc = "USB0_CH6"]
pub USB0_CH6: USB0_CH6,
#[doc = "USB0_CH7"]
pub USB0_CH7: USB0_CH7,
#[doc = "USB0_CH8"]
pub USB0_CH8: USB0_CH8,
#[doc = "USB0_CH9"]
pub USB0_CH9: USB0_CH9,
#[doc = "USB0_CH10"]
pub USB0_CH10: USB0_CH10,
#[doc = "USB0_CH11"]
pub USB0_CH11: USB0_CH11,
#[doc = "USB0_CH12"]
pub USB0_CH12: USB0_CH12,
#[doc = "USB0_CH13"]
pub USB0_CH13: USB0_CH13,
#[doc = "USIC0"]
pub USIC0: USIC0,
#[doc = "USIC1"]
pub USIC1: USIC1,
#[doc = "USIC2"]
pub USIC2: USIC2,
#[doc = "USIC0_CH0"]
pub USIC0_CH0: USIC0_CH0,
#[doc = "USIC0_CH1"]
pub USIC0_CH1: USIC0_CH1,
#[doc = "USIC1_CH0"]
pub USIC1_CH0: USIC1_CH0,
#[doc = "USIC1_CH1"]
pub USIC1_CH1: USIC1_CH1,
#[doc = "USIC2_CH0"]
pub USIC2_CH0: USIC2_CH0,
#[doc = "USIC2_CH1"]
pub USIC2_CH1: USIC2_CH1,
#[doc = "CAN"]
pub CAN: CAN,
#[doc = "CAN_NODE0"]
pub CAN_NODE0: CAN_NODE0,
#[doc = "CAN_NODE1"]
pub CAN_NODE1: CAN_NODE1,
#[doc = "CAN_NODE2"]
pub CAN_NODE2: CAN_NODE2,
#[doc = "CAN_NODE3"]
pub CAN_NODE3: CAN_NODE3,
#[doc = "CAN_NODE4"]
pub CAN_NODE4: CAN_NODE4,
#[doc = "CAN_NODE5"]
pub CAN_NODE5: CAN_NODE5,
#[doc = "CAN_MO"]
pub CAN_MO: CAN_MO,
#[doc = "VADC"]
pub VADC: VADC,
#[doc = "VADC_G0"]
pub VADC_G0: VADC_G0,
#[doc = "VADC_G1"]
pub VADC_G1: VADC_G1,
#[doc = "VADC_G2"]
pub VADC_G2: VADC_G2,
#[doc = "VADC_G3"]
pub VADC_G3: VADC_G3,
#[doc = "DSD"]
pub DSD: DSD,
#[doc = "DSD_CH0"]
pub DSD_CH0: DSD_CH0,
#[doc = "DSD_CH1"]
pub DSD_CH1: DSD_CH1,
#[doc = "DSD_CH2"]
pub DSD_CH2: DSD_CH2,
#[doc = "DSD_CH3"]
pub DSD_CH3: DSD_CH3,
#[doc = "DAC"]
pub DAC: DAC,
#[doc = "CCU40"]
pub CCU40: CCU40,
#[doc = "CCU41"]
pub CCU41: CCU41,
#[doc = "CCU42"]
pub CCU42: CCU42,
#[doc = "CCU43"]
pub CCU43: CCU43,
#[doc = "CCU40_CC40"]
pub CCU40_CC40: CCU40_CC40,
#[doc = "CCU40_CC41"]
pub CCU40_CC41: CCU40_CC41,
#[doc = "CCU40_CC42"]
pub CCU40_CC42: CCU40_CC42,
#[doc = "CCU40_CC43"]
pub CCU40_CC43: CCU40_CC43,
#[doc = "CCU41_CC40"]
pub CCU41_CC40: CCU41_CC40,
#[doc = "CCU41_CC41"]
pub CCU41_CC41: CCU41_CC41,
#[doc = "CCU41_CC42"]
pub CCU41_CC42: CCU41_CC42,
#[doc = "CCU41_CC43"]
pub CCU41_CC43: CCU41_CC43,
#[doc = "CCU42_CC40"]
pub CCU42_CC40: CCU42_CC40,
#[doc = "CCU42_CC41"]
pub CCU42_CC41: CCU42_CC41,
#[doc = "CCU42_CC42"]
pub CCU42_CC42: CCU42_CC42,
#[doc = "CCU42_CC43"]
pub CCU42_CC43: CCU42_CC43,
#[doc = "CCU43_CC40"]
pub CCU43_CC40: CCU43_CC40,
#[doc = "CCU43_CC41"]
pub CCU43_CC41: CCU43_CC41,
#[doc = "CCU43_CC42"]
pub CCU43_CC42: CCU43_CC42,
#[doc = "CCU43_CC43"]
pub CCU43_CC43: CCU43_CC43,
#[doc = "CCU80"]
pub CCU80: CCU80,
#[doc = "CCU81"]
pub CCU81: CCU81,
#[doc = "CCU80_CC80"]
pub CCU80_CC80: CCU80_CC80,
#[doc = "CCU80_CC81"]
pub CCU80_CC81: CCU80_CC81,
#[doc = "CCU80_CC82"]
pub CCU80_CC82: CCU80_CC82,
#[doc = "CCU80_CC83"]
pub CCU80_CC83: CCU80_CC83,
#[doc = "CCU81_CC80"]
pub CCU81_CC80: CCU81_CC80,
#[doc = "CCU81_CC81"]
pub CCU81_CC81: CCU81_CC81,
#[doc = "CCU81_CC82"]
pub CCU81_CC82: CCU81_CC82,
#[doc = "CCU81_CC83"]
pub CCU81_CC83: CCU81_CC83,
#[doc = "POSIF0"]
pub POSIF0: POSIF0,
#[doc = "POSIF1"]
pub POSIF1: POSIF1,
#[doc = "PORT0"]
pub PORT0: PORT0,
#[doc = "PORT1"]
pub PORT1: PORT1,
#[doc = "PORT2"]
pub PORT2: PORT2,
#[doc = "PORT3"]
pub PORT3: PORT3,
#[doc = "PORT4"]
pub PORT4: PORT4,
#[doc = "PORT5"]
pub PORT5: PORT5,
#[doc = "PORT6"]
pub PORT6: PORT6,
#[doc = "PORT7"]
pub PORT7: PORT7,
#[doc = "PORT8"]
pub PORT8: PORT8,
#[doc = "PORT9"]
pub PORT9: PORT9,
#[doc = "PORT14"]
pub PORT14: PORT14,
#[doc = "PORT15"]
pub PORT15: PORT15,
}
impl Peripherals {
#[doc = r" Returns all the peripherals *once*."]
#[cfg(feature = "critical-section")]
#[inline]
pub fn take() -> Option<Self> {
critical_section::with(|_| {
if unsafe { DEVICE_PERIPHERALS } {
return None;
}
Some(unsafe { Peripherals::steal() })
})
}
#[doc = r" Unchecked version of `Peripherals::take`."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Each of the returned peripherals must be used at most once."]
#[inline]
pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true;
Peripherals {
PPB: PPB::steal(),
DLR: DLR::steal(),
ERU0: ERU0::steal(),
ERU1: ERU1::steal(),
GPDMA0: GPDMA0::steal(),
GPDMA0_CH0: GPDMA0_CH0::steal(),
GPDMA0_CH1: GPDMA0_CH1::steal(),
GPDMA0_CH2: GPDMA0_CH2::steal(),
GPDMA0_CH3: GPDMA0_CH3::steal(),
GPDMA0_CH4: GPDMA0_CH4::steal(),
GPDMA0_CH5: GPDMA0_CH5::steal(),
GPDMA0_CH6: GPDMA0_CH6::steal(),
GPDMA0_CH7: GPDMA0_CH7::steal(),
GPDMA1: GPDMA1::steal(),
GPDMA1_CH0: GPDMA1_CH0::steal(),
GPDMA1_CH1: GPDMA1_CH1::steal(),
GPDMA1_CH2: GPDMA1_CH2::steal(),
GPDMA1_CH3: GPDMA1_CH3::steal(),
FCE: FCE::steal(),
FCE_KE0: FCE_KE0::steal(),
FCE_KE1: FCE_KE1::steal(),
FCE_KE2: FCE_KE2::steal(),
FCE_KE3: FCE_KE3::steal(),
PBA0: PBA0::steal(),
PBA1: PBA1::steal(),
FLASH0: FLASH0::steal(),
PREF: PREF::steal(),
PMU0: PMU0::steal(),
WDT: WDT::steal(),
RTC: RTC::steal(),
SCU_CLK: SCU_CLK::steal(),
SCU_OSC: SCU_OSC::steal(),
SCU_PLL: SCU_PLL::steal(),
SCU_GENERAL: SCU_GENERAL::steal(),
SCU_INTERRUPT: SCU_INTERRUPT::steal(),
SCU_PARITY: SCU_PARITY::steal(),
SCU_TRAP: SCU_TRAP::steal(),
SCU_HIBERNATE: SCU_HIBERNATE::steal(),
SCU_POWER: SCU_POWER::steal(),
SCU_RESET: SCU_RESET::steal(),
LEDTS0: LEDTS0::steal(),
SDMMC_CON: SDMMC_CON::steal(),
SDMMC: SDMMC::steal(),
EBU: EBU::steal(),
ETH0_CON: ETH0_CON::steal(),
ETH0: ETH0::steal(),
ECAT0_CON: ECAT0_CON::steal(),
ECAT0: ECAT0::steal(),
ECAT0_FMMU0: ECAT0_FMMU0::steal(),
ECAT0_FMMU1: ECAT0_FMMU1::steal(),
ECAT0_FMMU2: ECAT0_FMMU2::steal(),
ECAT0_FMMU3: ECAT0_FMMU3::steal(),
ECAT0_FMMU4: ECAT0_FMMU4::steal(),
ECAT0_FMMU5: ECAT0_FMMU5::steal(),
ECAT0_FMMU6: ECAT0_FMMU6::steal(),
ECAT0_FMMU7: ECAT0_FMMU7::steal(),
ECAT0_SM0: ECAT0_SM0::steal(),
ECAT0_SM1: ECAT0_SM1::steal(),
ECAT0_SM2: ECAT0_SM2::steal(),
ECAT0_SM3: ECAT0_SM3::steal(),
ECAT0_SM4: ECAT0_SM4::steal(),
ECAT0_SM5: ECAT0_SM5::steal(),
ECAT0_SM6: ECAT0_SM6::steal(),
ECAT0_SM7: ECAT0_SM7::steal(),
USB0: USB0::steal(),
USB0_EP0: USB0_EP0::steal(),
USB0_EP1: USB0_EP1::steal(),
USB0_EP2: USB0_EP2::steal(),
USB0_EP3: USB0_EP3::steal(),
USB0_EP4: USB0_EP4::steal(),
USB0_EP5: USB0_EP5::steal(),
USB0_EP6: USB0_EP6::steal(),
USB0_CH0: USB0_CH0::steal(),
USB0_CH1: USB0_CH1::steal(),
USB0_CH2: USB0_CH2::steal(),
USB0_CH3: USB0_CH3::steal(),
USB0_CH4: USB0_CH4::steal(),
USB0_CH5: USB0_CH5::steal(),
USB0_CH6: USB0_CH6::steal(),
USB0_CH7: USB0_CH7::steal(),
USB0_CH8: USB0_CH8::steal(),
USB0_CH9: USB0_CH9::steal(),
USB0_CH10: USB0_CH10::steal(),
USB0_CH11: USB0_CH11::steal(),
USB0_CH12: USB0_CH12::steal(),
USB0_CH13: USB0_CH13::steal(),
USIC0: USIC0::steal(),
USIC1: USIC1::steal(),
USIC2: USIC2::steal(),
USIC0_CH0: USIC0_CH0::steal(),
USIC0_CH1: USIC0_CH1::steal(),
USIC1_CH0: USIC1_CH0::steal(),
USIC1_CH1: USIC1_CH1::steal(),
USIC2_CH0: USIC2_CH0::steal(),
USIC2_CH1: USIC2_CH1::steal(),
CAN: CAN::steal(),
CAN_NODE0: CAN_NODE0::steal(),
CAN_NODE1: CAN_NODE1::steal(),
CAN_NODE2: CAN_NODE2::steal(),
CAN_NODE3: CAN_NODE3::steal(),
CAN_NODE4: CAN_NODE4::steal(),
CAN_NODE5: CAN_NODE5::steal(),
CAN_MO: CAN_MO::steal(),
VADC: VADC::steal(),
VADC_G0: VADC_G0::steal(),
VADC_G1: VADC_G1::steal(),
VADC_G2: VADC_G2::steal(),
VADC_G3: VADC_G3::steal(),
DSD: DSD::steal(),
DSD_CH0: DSD_CH0::steal(),
DSD_CH1: DSD_CH1::steal(),
DSD_CH2: DSD_CH2::steal(),
DSD_CH3: DSD_CH3::steal(),
DAC: DAC::steal(),
CCU40: CCU40::steal(),
CCU41: CCU41::steal(),
CCU42: CCU42::steal(),
CCU43: CCU43::steal(),
CCU40_CC40: CCU40_CC40::steal(),
CCU40_CC41: CCU40_CC41::steal(),
CCU40_CC42: CCU40_CC42::steal(),
CCU40_CC43: CCU40_CC43::steal(),
CCU41_CC40: CCU41_CC40::steal(),
CCU41_CC41: CCU41_CC41::steal(),
CCU41_CC42: CCU41_CC42::steal(),
CCU41_CC43: CCU41_CC43::steal(),
CCU42_CC40: CCU42_CC40::steal(),
CCU42_CC41: CCU42_CC41::steal(),
CCU42_CC42: CCU42_CC42::steal(),
CCU42_CC43: CCU42_CC43::steal(),
CCU43_CC40: CCU43_CC40::steal(),
CCU43_CC41: CCU43_CC41::steal(),
CCU43_CC42: CCU43_CC42::steal(),
CCU43_CC43: CCU43_CC43::steal(),
CCU80: CCU80::steal(),
CCU81: CCU81::steal(),
CCU80_CC80: CCU80_CC80::steal(),
CCU80_CC81: CCU80_CC81::steal(),
CCU80_CC82: CCU80_CC82::steal(),
CCU80_CC83: CCU80_CC83::steal(),
CCU81_CC80: CCU81_CC80::steal(),
CCU81_CC81: CCU81_CC81::steal(),
CCU81_CC82: CCU81_CC82::steal(),
CCU81_CC83: CCU81_CC83::steal(),
POSIF0: POSIF0::steal(),
POSIF1: POSIF1::steal(),
PORT0: PORT0::steal(),
PORT1: PORT1::steal(),
PORT2: PORT2::steal(),
PORT3: PORT3::steal(),
PORT4: PORT4::steal(),
PORT5: PORT5::steal(),
PORT6: PORT6::steal(),
PORT7: PORT7::steal(),
PORT8: PORT8::steal(),
PORT9: PORT9::steal(),
PORT14: PORT14::steal(),
PORT15: PORT15::steal(),
}
}
}