xmc4800/ecat0_con/
con_.rs

1#[doc = "Register `CON` reader"]
2pub type R = crate::R<CON_SPEC>;
3#[doc = "Register `CON` writer"]
4pub type W = crate::W<CON_SPEC>;
5#[doc = "Enable EtherCAT Reset Request\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum ECATRSTEN_A {
8    #[doc = "0: Reset request by EtherCAT Master disabled"]
9    VALUE1 = 0,
10    #[doc = "1: Reset request by EtherCAT Master enabled"]
11    VALUE2 = 1,
12}
13impl From<ECATRSTEN_A> for bool {
14    #[inline(always)]
15    fn from(variant: ECATRSTEN_A) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `ECATRSTEN` reader - Enable EtherCAT Reset Request"]
20pub type ECATRSTEN_R = crate::BitReader<ECATRSTEN_A>;
21impl ECATRSTEN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> ECATRSTEN_A {
25        match self.bits {
26            false => ECATRSTEN_A::VALUE1,
27            true => ECATRSTEN_A::VALUE2,
28        }
29    }
30    #[doc = "Reset request by EtherCAT Master disabled"]
31    #[inline(always)]
32    pub fn is_value1(&self) -> bool {
33        *self == ECATRSTEN_A::VALUE1
34    }
35    #[doc = "Reset request by EtherCAT Master enabled"]
36    #[inline(always)]
37    pub fn is_value2(&self) -> bool {
38        *self == ECATRSTEN_A::VALUE2
39    }
40}
41#[doc = "Field `ECATRSTEN` writer - Enable EtherCAT Reset Request"]
42pub type ECATRSTEN_W<'a, REG> = crate::BitWriter<'a, REG, ECATRSTEN_A>;
43impl<'a, REG> ECATRSTEN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Reset request by EtherCAT Master disabled"]
48    #[inline(always)]
49    pub fn value1(self) -> &'a mut crate::W<REG> {
50        self.variant(ECATRSTEN_A::VALUE1)
51    }
52    #[doc = "Reset request by EtherCAT Master enabled"]
53    #[inline(always)]
54    pub fn value2(self) -> &'a mut crate::W<REG> {
55        self.variant(ECATRSTEN_A::VALUE2)
56    }
57}
58#[doc = "LATCHIN0 Input Select\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60#[repr(u8)]
61pub enum LATCHIN0SEL_A {
62    #[doc = "0: Data input LATCHIN0A is selected"]
63    VALUE1 = 0,
64    #[doc = "1: Data input LATCHIN0B is selected"]
65    VALUE2 = 1,
66    #[doc = "2: Data input LATCHIN0C is selected"]
67    VALUE3 = 2,
68    #[doc = "3: Data input LATCHIN0D is selected"]
69    VALUE4 = 3,
70}
71impl From<LATCHIN0SEL_A> for u8 {
72    #[inline(always)]
73    fn from(variant: LATCHIN0SEL_A) -> Self {
74        variant as _
75    }
76}
77impl crate::FieldSpec for LATCHIN0SEL_A {
78    type Ux = u8;
79}
80impl crate::IsEnum for LATCHIN0SEL_A {}
81#[doc = "Field `LATCHIN0SEL` reader - LATCHIN0 Input Select"]
82pub type LATCHIN0SEL_R = crate::FieldReader<LATCHIN0SEL_A>;
83impl LATCHIN0SEL_R {
84    #[doc = "Get enumerated values variant"]
85    #[inline(always)]
86    pub const fn variant(&self) -> LATCHIN0SEL_A {
87        match self.bits {
88            0 => LATCHIN0SEL_A::VALUE1,
89            1 => LATCHIN0SEL_A::VALUE2,
90            2 => LATCHIN0SEL_A::VALUE3,
91            3 => LATCHIN0SEL_A::VALUE4,
92            _ => unreachable!(),
93        }
94    }
95    #[doc = "Data input LATCHIN0A is selected"]
96    #[inline(always)]
97    pub fn is_value1(&self) -> bool {
98        *self == LATCHIN0SEL_A::VALUE1
99    }
100    #[doc = "Data input LATCHIN0B is selected"]
101    #[inline(always)]
102    pub fn is_value2(&self) -> bool {
103        *self == LATCHIN0SEL_A::VALUE2
104    }
105    #[doc = "Data input LATCHIN0C is selected"]
106    #[inline(always)]
107    pub fn is_value3(&self) -> bool {
108        *self == LATCHIN0SEL_A::VALUE3
109    }
110    #[doc = "Data input LATCHIN0D is selected"]
111    #[inline(always)]
112    pub fn is_value4(&self) -> bool {
113        *self == LATCHIN0SEL_A::VALUE4
114    }
115}
116#[doc = "Field `LATCHIN0SEL` writer - LATCHIN0 Input Select"]
117pub type LATCHIN0SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, LATCHIN0SEL_A, crate::Safe>;
118impl<'a, REG> LATCHIN0SEL_W<'a, REG>
119where
120    REG: crate::Writable + crate::RegisterSpec,
121    REG::Ux: From<u8>,
122{
123    #[doc = "Data input LATCHIN0A is selected"]
124    #[inline(always)]
125    pub fn value1(self) -> &'a mut crate::W<REG> {
126        self.variant(LATCHIN0SEL_A::VALUE1)
127    }
128    #[doc = "Data input LATCHIN0B is selected"]
129    #[inline(always)]
130    pub fn value2(self) -> &'a mut crate::W<REG> {
131        self.variant(LATCHIN0SEL_A::VALUE2)
132    }
133    #[doc = "Data input LATCHIN0C is selected"]
134    #[inline(always)]
135    pub fn value3(self) -> &'a mut crate::W<REG> {
136        self.variant(LATCHIN0SEL_A::VALUE3)
137    }
138    #[doc = "Data input LATCHIN0D is selected"]
139    #[inline(always)]
140    pub fn value4(self) -> &'a mut crate::W<REG> {
141        self.variant(LATCHIN0SEL_A::VALUE4)
142    }
143}
144#[doc = "Field `LATCHIN0` reader - EtherCAT LATCH_IN0 Input Signal"]
145pub type LATCHIN0_R = crate::BitReader;
146#[doc = "LATCHIN1 Input Select\n\nValue on reset: 0"]
147#[derive(Clone, Copy, Debug, PartialEq, Eq)]
148#[repr(u8)]
149pub enum LATCHIN1SEL_A {
150    #[doc = "0: Data input LATCHIN1A is selected"]
151    VALUE1 = 0,
152    #[doc = "1: Data input LATCHIN1B is selected"]
153    VALUE2 = 1,
154    #[doc = "2: Data input LATCHIN1C is selected"]
155    VALUE3 = 2,
156    #[doc = "3: Data input LATCHIN1D is selected"]
157    VALUE4 = 3,
158}
159impl From<LATCHIN1SEL_A> for u8 {
160    #[inline(always)]
161    fn from(variant: LATCHIN1SEL_A) -> Self {
162        variant as _
163    }
164}
165impl crate::FieldSpec for LATCHIN1SEL_A {
166    type Ux = u8;
167}
168impl crate::IsEnum for LATCHIN1SEL_A {}
169#[doc = "Field `LATCHIN1SEL` reader - LATCHIN1 Input Select"]
170pub type LATCHIN1SEL_R = crate::FieldReader<LATCHIN1SEL_A>;
171impl LATCHIN1SEL_R {
172    #[doc = "Get enumerated values variant"]
173    #[inline(always)]
174    pub const fn variant(&self) -> LATCHIN1SEL_A {
175        match self.bits {
176            0 => LATCHIN1SEL_A::VALUE1,
177            1 => LATCHIN1SEL_A::VALUE2,
178            2 => LATCHIN1SEL_A::VALUE3,
179            3 => LATCHIN1SEL_A::VALUE4,
180            _ => unreachable!(),
181        }
182    }
183    #[doc = "Data input LATCHIN1A is selected"]
184    #[inline(always)]
185    pub fn is_value1(&self) -> bool {
186        *self == LATCHIN1SEL_A::VALUE1
187    }
188    #[doc = "Data input LATCHIN1B is selected"]
189    #[inline(always)]
190    pub fn is_value2(&self) -> bool {
191        *self == LATCHIN1SEL_A::VALUE2
192    }
193    #[doc = "Data input LATCHIN1C is selected"]
194    #[inline(always)]
195    pub fn is_value3(&self) -> bool {
196        *self == LATCHIN1SEL_A::VALUE3
197    }
198    #[doc = "Data input LATCHIN1D is selected"]
199    #[inline(always)]
200    pub fn is_value4(&self) -> bool {
201        *self == LATCHIN1SEL_A::VALUE4
202    }
203}
204#[doc = "Field `LATCHIN1SEL` writer - LATCHIN1 Input Select"]
205pub type LATCHIN1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, LATCHIN1SEL_A, crate::Safe>;
206impl<'a, REG> LATCHIN1SEL_W<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209    REG::Ux: From<u8>,
210{
211    #[doc = "Data input LATCHIN1A is selected"]
212    #[inline(always)]
213    pub fn value1(self) -> &'a mut crate::W<REG> {
214        self.variant(LATCHIN1SEL_A::VALUE1)
215    }
216    #[doc = "Data input LATCHIN1B is selected"]
217    #[inline(always)]
218    pub fn value2(self) -> &'a mut crate::W<REG> {
219        self.variant(LATCHIN1SEL_A::VALUE2)
220    }
221    #[doc = "Data input LATCHIN1C is selected"]
222    #[inline(always)]
223    pub fn value3(self) -> &'a mut crate::W<REG> {
224        self.variant(LATCHIN1SEL_A::VALUE3)
225    }
226    #[doc = "Data input LATCHIN1D is selected"]
227    #[inline(always)]
228    pub fn value4(self) -> &'a mut crate::W<REG> {
229        self.variant(LATCHIN1SEL_A::VALUE4)
230    }
231}
232#[doc = "Field `LATCHIN1` reader - EtherCAT LATCH_IN1 Input Signal"]
233pub type LATCHIN1_R = crate::BitReader;
234#[doc = "Field `PHYOFFSET` reader - Ethernet PHY Address Offset"]
235pub type PHYOFFSET_R = crate::FieldReader;
236#[doc = "Field `PHYOFFSET` writer - Ethernet PHY Address Offset"]
237pub type PHYOFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
238#[doc = "MDIO Input Select\n\nValue on reset: 0"]
239#[derive(Clone, Copy, Debug, PartialEq, Eq)]
240#[repr(u8)]
241pub enum MDIO_A {
242    #[doc = "0: Data input MDIA is selected"]
243    VALUE1 = 0,
244    #[doc = "1: Data input MDIB is selected"]
245    VALUE2 = 1,
246    #[doc = "2: Data input MDIC is selected"]
247    VALUE3 = 2,
248    #[doc = "3: Data input MDID is selected"]
249    VALUE4 = 3,
250}
251impl From<MDIO_A> for u8 {
252    #[inline(always)]
253    fn from(variant: MDIO_A) -> Self {
254        variant as _
255    }
256}
257impl crate::FieldSpec for MDIO_A {
258    type Ux = u8;
259}
260impl crate::IsEnum for MDIO_A {}
261#[doc = "Field `MDIO` reader - MDIO Input Select"]
262pub type MDIO_R = crate::FieldReader<MDIO_A>;
263impl MDIO_R {
264    #[doc = "Get enumerated values variant"]
265    #[inline(always)]
266    pub const fn variant(&self) -> MDIO_A {
267        match self.bits {
268            0 => MDIO_A::VALUE1,
269            1 => MDIO_A::VALUE2,
270            2 => MDIO_A::VALUE3,
271            3 => MDIO_A::VALUE4,
272            _ => unreachable!(),
273        }
274    }
275    #[doc = "Data input MDIA is selected"]
276    #[inline(always)]
277    pub fn is_value1(&self) -> bool {
278        *self == MDIO_A::VALUE1
279    }
280    #[doc = "Data input MDIB is selected"]
281    #[inline(always)]
282    pub fn is_value2(&self) -> bool {
283        *self == MDIO_A::VALUE2
284    }
285    #[doc = "Data input MDIC is selected"]
286    #[inline(always)]
287    pub fn is_value3(&self) -> bool {
288        *self == MDIO_A::VALUE3
289    }
290    #[doc = "Data input MDID is selected"]
291    #[inline(always)]
292    pub fn is_value4(&self) -> bool {
293        *self == MDIO_A::VALUE4
294    }
295}
296#[doc = "Field `MDIO` writer - MDIO Input Select"]
297pub type MDIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2, MDIO_A, crate::Safe>;
298impl<'a, REG> MDIO_W<'a, REG>
299where
300    REG: crate::Writable + crate::RegisterSpec,
301    REG::Ux: From<u8>,
302{
303    #[doc = "Data input MDIA is selected"]
304    #[inline(always)]
305    pub fn value1(self) -> &'a mut crate::W<REG> {
306        self.variant(MDIO_A::VALUE1)
307    }
308    #[doc = "Data input MDIB is selected"]
309    #[inline(always)]
310    pub fn value2(self) -> &'a mut crate::W<REG> {
311        self.variant(MDIO_A::VALUE2)
312    }
313    #[doc = "Data input MDIC is selected"]
314    #[inline(always)]
315    pub fn value3(self) -> &'a mut crate::W<REG> {
316        self.variant(MDIO_A::VALUE3)
317    }
318    #[doc = "Data input MDID is selected"]
319    #[inline(always)]
320    pub fn value4(self) -> &'a mut crate::W<REG> {
321        self.variant(MDIO_A::VALUE4)
322    }
323}
324impl R {
325    #[doc = "Bit 0 - Enable EtherCAT Reset Request"]
326    #[inline(always)]
327    pub fn ecatrsten(&self) -> ECATRSTEN_R {
328        ECATRSTEN_R::new((self.bits & 1) != 0)
329    }
330    #[doc = "Bits 8:9 - LATCHIN0 Input Select"]
331    #[inline(always)]
332    pub fn latchin0sel(&self) -> LATCHIN0SEL_R {
333        LATCHIN0SEL_R::new(((self.bits >> 8) & 3) as u8)
334    }
335    #[doc = "Bit 11 - EtherCAT LATCH_IN0 Input Signal"]
336    #[inline(always)]
337    pub fn latchin0(&self) -> LATCHIN0_R {
338        LATCHIN0_R::new(((self.bits >> 11) & 1) != 0)
339    }
340    #[doc = "Bits 12:13 - LATCHIN1 Input Select"]
341    #[inline(always)]
342    pub fn latchin1sel(&self) -> LATCHIN1SEL_R {
343        LATCHIN1SEL_R::new(((self.bits >> 12) & 3) as u8)
344    }
345    #[doc = "Bit 15 - EtherCAT LATCH_IN1 Input Signal"]
346    #[inline(always)]
347    pub fn latchin1(&self) -> LATCHIN1_R {
348        LATCHIN1_R::new(((self.bits >> 15) & 1) != 0)
349    }
350    #[doc = "Bits 16:20 - Ethernet PHY Address Offset"]
351    #[inline(always)]
352    pub fn phyoffset(&self) -> PHYOFFSET_R {
353        PHYOFFSET_R::new(((self.bits >> 16) & 0x1f) as u8)
354    }
355    #[doc = "Bits 22:23 - MDIO Input Select"]
356    #[inline(always)]
357    pub fn mdio(&self) -> MDIO_R {
358        MDIO_R::new(((self.bits >> 22) & 3) as u8)
359    }
360}
361impl W {
362    #[doc = "Bit 0 - Enable EtherCAT Reset Request"]
363    #[inline(always)]
364    pub fn ecatrsten(&mut self) -> ECATRSTEN_W<CON_SPEC> {
365        ECATRSTEN_W::new(self, 0)
366    }
367    #[doc = "Bits 8:9 - LATCHIN0 Input Select"]
368    #[inline(always)]
369    pub fn latchin0sel(&mut self) -> LATCHIN0SEL_W<CON_SPEC> {
370        LATCHIN0SEL_W::new(self, 8)
371    }
372    #[doc = "Bits 12:13 - LATCHIN1 Input Select"]
373    #[inline(always)]
374    pub fn latchin1sel(&mut self) -> LATCHIN1SEL_W<CON_SPEC> {
375        LATCHIN1SEL_W::new(self, 12)
376    }
377    #[doc = "Bits 16:20 - Ethernet PHY Address Offset"]
378    #[inline(always)]
379    pub fn phyoffset(&mut self) -> PHYOFFSET_W<CON_SPEC> {
380        PHYOFFSET_W::new(self, 16)
381    }
382    #[doc = "Bits 22:23 - MDIO Input Select"]
383    #[inline(always)]
384    pub fn mdio(&mut self) -> MDIO_W<CON_SPEC> {
385        MDIO_W::new(self, 22)
386    }
387}
388#[doc = "EtherCAT 0 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`con::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`con::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
389pub struct CON_SPEC;
390impl crate::RegisterSpec for CON_SPEC {
391    type Ux = u32;
392}
393#[doc = "`read()` method returns [`con::R`](R) reader structure"]
394impl crate::Readable for CON_SPEC {}
395#[doc = "`write(|w| ..)` method takes [`con::W`](W) writer structure"]
396impl crate::Writable for CON_SPEC {
397    type Safety = crate::Unsafe;
398    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
399    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
400}
401#[doc = "`reset()` method sets CON to value 0"]
402impl crate::Resettable for CON_SPEC {
403    const RESET_VALUE: u32 = 0;
404}
xmc4800/ecat0_con/con_.rs

xmc4800/ecat0_con/
con_.rs
