1#[doc = "Register `NCR` reader"]
2pub type R = crate::R<NCR_SPEC>;
3#[doc = "Register `NCR` writer"]
4pub type W = crate::W<NCR_SPEC>;
5#[doc = "Node Initialization\n\nValue on reset: 1"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum INIT_A {
8 #[doc = "0: Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus-off state, the ongoing bus-off recovery (which does not depend on the INIT bit) is continued. With the end of the bus-off recovery sequence the CAN node is allowed to take part in the CAN traffic. If the CAN node is not in the bus-off state, a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic."]
9 VALUE1 = 0,
10 #[doc = "1: Setting this bit terminates the participation of this node in the CAN traffic. Any ongoing frame transfer is cancelled and the transmit line goes recessive. If the CAN node is in the bus-off state, then the running bus-off recovery sequence is continued. If the INIT bit is still set after the successful completion of the bus-off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 1), then the CAN node leaves the bus-off state but remains inactive as long as INIT remains set."]
11 VALUE2 = 1,
12}
13impl From<INIT_A> for bool {
14 #[inline(always)]
15 fn from(variant: INIT_A) -> Self {
16 variant as u8 != 0
17 }
18}
19#[doc = "Field `INIT` reader - Node Initialization"]
20pub type INIT_R = crate::BitReader<INIT_A>;
21impl INIT_R {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> INIT_A {
25 match self.bits {
26 false => INIT_A::VALUE1,
27 true => INIT_A::VALUE2,
28 }
29 }
30 #[doc = "Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus-off state, the ongoing bus-off recovery (which does not depend on the INIT bit) is continued. With the end of the bus-off recovery sequence the CAN node is allowed to take part in the CAN traffic. If the CAN node is not in the bus-off state, a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic."]
31 #[inline(always)]
32 pub fn is_value1(&self) -> bool {
33 *self == INIT_A::VALUE1
34 }
35 #[doc = "Setting this bit terminates the participation of this node in the CAN traffic. Any ongoing frame transfer is cancelled and the transmit line goes recessive. If the CAN node is in the bus-off state, then the running bus-off recovery sequence is continued. If the INIT bit is still set after the successful completion of the bus-off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 1), then the CAN node leaves the bus-off state but remains inactive as long as INIT remains set."]
36 #[inline(always)]
37 pub fn is_value2(&self) -> bool {
38 *self == INIT_A::VALUE2
39 }
40}
41#[doc = "Field `INIT` writer - Node Initialization"]
42pub type INIT_W<'a, REG> = crate::BitWriter<'a, REG, INIT_A>;
43impl<'a, REG> INIT_W<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus-off state, the ongoing bus-off recovery (which does not depend on the INIT bit) is continued. With the end of the bus-off recovery sequence the CAN node is allowed to take part in the CAN traffic. If the CAN node is not in the bus-off state, a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic."]
48 #[inline(always)]
49 pub fn value1(self) -> &'a mut crate::W<REG> {
50 self.variant(INIT_A::VALUE1)
51 }
52 #[doc = "Setting this bit terminates the participation of this node in the CAN traffic. Any ongoing frame transfer is cancelled and the transmit line goes recessive. If the CAN node is in the bus-off state, then the running bus-off recovery sequence is continued. If the INIT bit is still set after the successful completion of the bus-off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 1), then the CAN node leaves the bus-off state but remains inactive as long as INIT remains set."]
53 #[inline(always)]
54 pub fn value2(self) -> &'a mut crate::W<REG> {
55 self.variant(INIT_A::VALUE2)
56 }
57}
58#[doc = "Transfer Interrupt Enable\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum TRIE_A {
61 #[doc = "0: Transfer interrupt is disabled."]
62 VALUE1 = 0,
63 #[doc = "1: Transfer interrupt is enabled."]
64 VALUE2 = 1,
65}
66impl From<TRIE_A> for bool {
67 #[inline(always)]
68 fn from(variant: TRIE_A) -> Self {
69 variant as u8 != 0
70 }
71}
72#[doc = "Field `TRIE` reader - Transfer Interrupt Enable"]
73pub type TRIE_R = crate::BitReader<TRIE_A>;
74impl TRIE_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub const fn variant(&self) -> TRIE_A {
78 match self.bits {
79 false => TRIE_A::VALUE1,
80 true => TRIE_A::VALUE2,
81 }
82 }
83 #[doc = "Transfer interrupt is disabled."]
84 #[inline(always)]
85 pub fn is_value1(&self) -> bool {
86 *self == TRIE_A::VALUE1
87 }
88 #[doc = "Transfer interrupt is enabled."]
89 #[inline(always)]
90 pub fn is_value2(&self) -> bool {
91 *self == TRIE_A::VALUE2
92 }
93}
94#[doc = "Field `TRIE` writer - Transfer Interrupt Enable"]
95pub type TRIE_W<'a, REG> = crate::BitWriter<'a, REG, TRIE_A>;
96impl<'a, REG> TRIE_W<'a, REG>
97where
98 REG: crate::Writable + crate::RegisterSpec,
99{
100 #[doc = "Transfer interrupt is disabled."]
101 #[inline(always)]
102 pub fn value1(self) -> &'a mut crate::W<REG> {
103 self.variant(TRIE_A::VALUE1)
104 }
105 #[doc = "Transfer interrupt is enabled."]
106 #[inline(always)]
107 pub fn value2(self) -> &'a mut crate::W<REG> {
108 self.variant(TRIE_A::VALUE2)
109 }
110}
111#[doc = "LEC Indicated Error Interrupt Enable\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum LECIE_A {
114 #[doc = "0: Last error code interrupt is disabled."]
115 VALUE1 = 0,
116 #[doc = "1: Last error code interrupt is enabled."]
117 VALUE2 = 1,
118}
119impl From<LECIE_A> for bool {
120 #[inline(always)]
121 fn from(variant: LECIE_A) -> Self {
122 variant as u8 != 0
123 }
124}
125#[doc = "Field `LECIE` reader - LEC Indicated Error Interrupt Enable"]
126pub type LECIE_R = crate::BitReader<LECIE_A>;
127impl LECIE_R {
128 #[doc = "Get enumerated values variant"]
129 #[inline(always)]
130 pub const fn variant(&self) -> LECIE_A {
131 match self.bits {
132 false => LECIE_A::VALUE1,
133 true => LECIE_A::VALUE2,
134 }
135 }
136 #[doc = "Last error code interrupt is disabled."]
137 #[inline(always)]
138 pub fn is_value1(&self) -> bool {
139 *self == LECIE_A::VALUE1
140 }
141 #[doc = "Last error code interrupt is enabled."]
142 #[inline(always)]
143 pub fn is_value2(&self) -> bool {
144 *self == LECIE_A::VALUE2
145 }
146}
147#[doc = "Field `LECIE` writer - LEC Indicated Error Interrupt Enable"]
148pub type LECIE_W<'a, REG> = crate::BitWriter<'a, REG, LECIE_A>;
149impl<'a, REG> LECIE_W<'a, REG>
150where
151 REG: crate::Writable + crate::RegisterSpec,
152{
153 #[doc = "Last error code interrupt is disabled."]
154 #[inline(always)]
155 pub fn value1(self) -> &'a mut crate::W<REG> {
156 self.variant(LECIE_A::VALUE1)
157 }
158 #[doc = "Last error code interrupt is enabled."]
159 #[inline(always)]
160 pub fn value2(self) -> &'a mut crate::W<REG> {
161 self.variant(LECIE_A::VALUE2)
162 }
163}
164#[doc = "Alert Interrupt Enable\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum ALIE_A {
167 #[doc = "0: Alert interrupt is disabled."]
168 VALUE1 = 0,
169 #[doc = "1: Alert interrupt is enabled."]
170 VALUE2 = 1,
171}
172impl From<ALIE_A> for bool {
173 #[inline(always)]
174 fn from(variant: ALIE_A) -> Self {
175 variant as u8 != 0
176 }
177}
178#[doc = "Field `ALIE` reader - Alert Interrupt Enable"]
179pub type ALIE_R = crate::BitReader<ALIE_A>;
180impl ALIE_R {
181 #[doc = "Get enumerated values variant"]
182 #[inline(always)]
183 pub const fn variant(&self) -> ALIE_A {
184 match self.bits {
185 false => ALIE_A::VALUE1,
186 true => ALIE_A::VALUE2,
187 }
188 }
189 #[doc = "Alert interrupt is disabled."]
190 #[inline(always)]
191 pub fn is_value1(&self) -> bool {
192 *self == ALIE_A::VALUE1
193 }
194 #[doc = "Alert interrupt is enabled."]
195 #[inline(always)]
196 pub fn is_value2(&self) -> bool {
197 *self == ALIE_A::VALUE2
198 }
199}
200#[doc = "Field `ALIE` writer - Alert Interrupt Enable"]
201pub type ALIE_W<'a, REG> = crate::BitWriter<'a, REG, ALIE_A>;
202impl<'a, REG> ALIE_W<'a, REG>
203where
204 REG: crate::Writable + crate::RegisterSpec,
205{
206 #[doc = "Alert interrupt is disabled."]
207 #[inline(always)]
208 pub fn value1(self) -> &'a mut crate::W<REG> {
209 self.variant(ALIE_A::VALUE1)
210 }
211 #[doc = "Alert interrupt is enabled."]
212 #[inline(always)]
213 pub fn value2(self) -> &'a mut crate::W<REG> {
214 self.variant(ALIE_A::VALUE2)
215 }
216}
217#[doc = "Field `CANDIS` reader - CAN Disable"]
218pub type CANDIS_R = crate::BitReader;
219#[doc = "Field `CANDIS` writer - CAN Disable"]
220pub type CANDIS_W<'a, REG> = crate::BitWriter<'a, REG>;
221#[doc = "Field `TXDIS` reader - Transmit Disable"]
222pub type TXDIS_R = crate::BitReader;
223#[doc = "Field `TXDIS` writer - Transmit Disable"]
224pub type TXDIS_W<'a, REG> = crate::BitWriter<'a, REG>;
225#[doc = "Configuration Change Enable\n\nValue on reset: 1"]
226#[derive(Clone, Copy, Debug, PartialEq, Eq)]
227pub enum CCE_A {
228 #[doc = "0: The Bit Timing Register, the Port Control Register, Error Counter Register may only be read. All attempts to modify them are ignored."]
229 VALUE1 = 0,
230 #[doc = "1: The Bit Timing Register, the Port Control Register, Error Counter Register may be read and written."]
231 VALUE2 = 1,
232}
233impl From<CCE_A> for bool {
234 #[inline(always)]
235 fn from(variant: CCE_A) -> Self {
236 variant as u8 != 0
237 }
238}
239#[doc = "Field `CCE` reader - Configuration Change Enable"]
240pub type CCE_R = crate::BitReader<CCE_A>;
241impl CCE_R {
242 #[doc = "Get enumerated values variant"]
243 #[inline(always)]
244 pub const fn variant(&self) -> CCE_A {
245 match self.bits {
246 false => CCE_A::VALUE1,
247 true => CCE_A::VALUE2,
248 }
249 }
250 #[doc = "The Bit Timing Register, the Port Control Register, Error Counter Register may only be read. All attempts to modify them are ignored."]
251 #[inline(always)]
252 pub fn is_value1(&self) -> bool {
253 *self == CCE_A::VALUE1
254 }
255 #[doc = "The Bit Timing Register, the Port Control Register, Error Counter Register may be read and written."]
256 #[inline(always)]
257 pub fn is_value2(&self) -> bool {
258 *self == CCE_A::VALUE2
259 }
260}
261#[doc = "Field `CCE` writer - Configuration Change Enable"]
262pub type CCE_W<'a, REG> = crate::BitWriter<'a, REG, CCE_A>;
263impl<'a, REG> CCE_W<'a, REG>
264where
265 REG: crate::Writable + crate::RegisterSpec,
266{
267 #[doc = "The Bit Timing Register, the Port Control Register, Error Counter Register may only be read. All attempts to modify them are ignored."]
268 #[inline(always)]
269 pub fn value1(self) -> &'a mut crate::W<REG> {
270 self.variant(CCE_A::VALUE1)
271 }
272 #[doc = "The Bit Timing Register, the Port Control Register, Error Counter Register may be read and written."]
273 #[inline(always)]
274 pub fn value2(self) -> &'a mut crate::W<REG> {
275 self.variant(CCE_A::VALUE2)
276 }
277}
278#[doc = "Field `CALM` reader - CAN Analyzer Mode"]
279pub type CALM_R = crate::BitReader;
280#[doc = "Field `CALM` writer - CAN Analyzer Mode"]
281pub type CALM_W<'a, REG> = crate::BitWriter<'a, REG>;
282impl R {
283 #[doc = "Bit 0 - Node Initialization"]
284 #[inline(always)]
285 pub fn init(&self) -> INIT_R {
286 INIT_R::new((self.bits & 1) != 0)
287 }
288 #[doc = "Bit 1 - Transfer Interrupt Enable"]
289 #[inline(always)]
290 pub fn trie(&self) -> TRIE_R {
291 TRIE_R::new(((self.bits >> 1) & 1) != 0)
292 }
293 #[doc = "Bit 2 - LEC Indicated Error Interrupt Enable"]
294 #[inline(always)]
295 pub fn lecie(&self) -> LECIE_R {
296 LECIE_R::new(((self.bits >> 2) & 1) != 0)
297 }
298 #[doc = "Bit 3 - Alert Interrupt Enable"]
299 #[inline(always)]
300 pub fn alie(&self) -> ALIE_R {
301 ALIE_R::new(((self.bits >> 3) & 1) != 0)
302 }
303 #[doc = "Bit 4 - CAN Disable"]
304 #[inline(always)]
305 pub fn candis(&self) -> CANDIS_R {
306 CANDIS_R::new(((self.bits >> 4) & 1) != 0)
307 }
308 #[doc = "Bit 5 - Transmit Disable"]
309 #[inline(always)]
310 pub fn txdis(&self) -> TXDIS_R {
311 TXDIS_R::new(((self.bits >> 5) & 1) != 0)
312 }
313 #[doc = "Bit 6 - Configuration Change Enable"]
314 #[inline(always)]
315 pub fn cce(&self) -> CCE_R {
316 CCE_R::new(((self.bits >> 6) & 1) != 0)
317 }
318 #[doc = "Bit 7 - CAN Analyzer Mode"]
319 #[inline(always)]
320 pub fn calm(&self) -> CALM_R {
321 CALM_R::new(((self.bits >> 7) & 1) != 0)
322 }
323}
324impl W {
325 #[doc = "Bit 0 - Node Initialization"]
326 #[inline(always)]
327 pub fn init(&mut self) -> INIT_W<NCR_SPEC> {
328 INIT_W::new(self, 0)
329 }
330 #[doc = "Bit 1 - Transfer Interrupt Enable"]
331 #[inline(always)]
332 pub fn trie(&mut self) -> TRIE_W<NCR_SPEC> {
333 TRIE_W::new(self, 1)
334 }
335 #[doc = "Bit 2 - LEC Indicated Error Interrupt Enable"]
336 #[inline(always)]
337 pub fn lecie(&mut self) -> LECIE_W<NCR_SPEC> {
338 LECIE_W::new(self, 2)
339 }
340 #[doc = "Bit 3 - Alert Interrupt Enable"]
341 #[inline(always)]
342 pub fn alie(&mut self) -> ALIE_W<NCR_SPEC> {
343 ALIE_W::new(self, 3)
344 }
345 #[doc = "Bit 4 - CAN Disable"]
346 #[inline(always)]
347 pub fn candis(&mut self) -> CANDIS_W<NCR_SPEC> {
348 CANDIS_W::new(self, 4)
349 }
350 #[doc = "Bit 5 - Transmit Disable"]
351 #[inline(always)]
352 pub fn txdis(&mut self) -> TXDIS_W<NCR_SPEC> {
353 TXDIS_W::new(self, 5)
354 }
355 #[doc = "Bit 6 - Configuration Change Enable"]
356 #[inline(always)]
357 pub fn cce(&mut self) -> CCE_W<NCR_SPEC> {
358 CCE_W::new(self, 6)
359 }
360 #[doc = "Bit 7 - CAN Analyzer Mode"]
361 #[inline(always)]
362 pub fn calm(&mut self) -> CALM_W<NCR_SPEC> {
363 CALM_W::new(self, 7)
364 }
365}
366#[doc = "Node Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ncr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ncr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
367pub struct NCR_SPEC;
368impl crate::RegisterSpec for NCR_SPEC {
369 type Ux = u32;
370}
371#[doc = "`read()` method returns [`ncr::R`](R) reader structure"]
372impl crate::Readable for NCR_SPEC {}
373#[doc = "`write(|w| ..)` method takes [`ncr::W`](W) writer structure"]
374impl crate::Writable for NCR_SPEC {
375 type Safety = crate::Unsafe;
376 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
377 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
378}
379#[doc = "`reset()` method sets NCR to value 0x41"]
380impl crate::Resettable for NCR_SPEC {
381 const RESET_VALUE: u32 = 0x41;
382}