1#[doc = "Register `GRSTCTL` reader"]
2pub type R = crate::R<GRSTCTL_SPEC>;
3#[doc = "Register `GRSTCTL` writer"]
4pub type W = crate::W<GRSTCTL_SPEC>;
5#[doc = "Field `CSftRst` reader - Core Soft Reset"]
6pub type CSFT_RST_R = crate::BitReader;
7#[doc = "Field `CSftRst` writer - Core Soft Reset"]
8pub type CSFT_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FrmCntrRst` reader - Host Frame Counter Reset"]
10pub type FRM_CNTR_RST_R = crate::BitReader;
11#[doc = "Field `FrmCntrRst` writer - Host Frame Counter Reset"]
12pub type FRM_CNTR_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RxFFlsh` reader - RxFIFO Flush"]
14pub type RX_FFLSH_R = crate::BitReader;
15#[doc = "Field `RxFFlsh` writer - RxFIFO Flush"]
16pub type RX_FFLSH_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TxFFlsh` reader - TxFIFO Flush"]
18pub type TX_FFLSH_R = crate::BitReader;
19#[doc = "Field `TxFFlsh` writer - TxFIFO Flush"]
20pub type TX_FFLSH_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "TxFIFO Number\n\nValue on reset: 0"]
22#[derive(Clone, Copy, Debug, PartialEq, Eq)]
23#[repr(u8)]
24pub enum TX_FNUM_A {
25 #[doc = "0: Non-periodic TxFIFO flush in Host mode or Tx FIFO 0 flush in device mode"]
26 VALUE1 = 0,
27 #[doc = "1: Periodic TxFIFO flush in Host mode or Tx FIFO 1 flush in device mode"]
28 VALUE2 = 1,
29 #[doc = "2: Tx FIFO 2 flush in device mode"]
30 VALUE3 = 2,
31 #[doc = "15: Tx FIFO 15 flush in device mode"]
32 VALUE4 = 15,
33 #[doc = "16: Flush all the transmit FIFOs in device or host mode."]
34 VALUE5 = 16,
35}
36impl From<TX_FNUM_A> for u8 {
37 #[inline(always)]
38 fn from(variant: TX_FNUM_A) -> Self {
39 variant as _
40 }
41}
42impl crate::FieldSpec for TX_FNUM_A {
43 type Ux = u8;
44}
45impl crate::IsEnum for TX_FNUM_A {}
46#[doc = "Field `TxFNum` reader - TxFIFO Number"]
47pub type TX_FNUM_R = crate::FieldReader<TX_FNUM_A>;
48impl TX_FNUM_R {
49 #[doc = "Get enumerated values variant"]
50 #[inline(always)]
51 pub const fn variant(&self) -> Option<TX_FNUM_A> {
52 match self.bits {
53 0 => Some(TX_FNUM_A::VALUE1),
54 1 => Some(TX_FNUM_A::VALUE2),
55 2 => Some(TX_FNUM_A::VALUE3),
56 15 => Some(TX_FNUM_A::VALUE4),
57 16 => Some(TX_FNUM_A::VALUE5),
58 _ => None,
59 }
60 }
61 #[doc = "Non-periodic TxFIFO flush in Host mode or Tx FIFO 0 flush in device mode"]
62 #[inline(always)]
63 pub fn is_value1(&self) -> bool {
64 *self == TX_FNUM_A::VALUE1
65 }
66 #[doc = "Periodic TxFIFO flush in Host mode or Tx FIFO 1 flush in device mode"]
67 #[inline(always)]
68 pub fn is_value2(&self) -> bool {
69 *self == TX_FNUM_A::VALUE2
70 }
71 #[doc = "Tx FIFO 2 flush in device mode"]
72 #[inline(always)]
73 pub fn is_value3(&self) -> bool {
74 *self == TX_FNUM_A::VALUE3
75 }
76 #[doc = "Tx FIFO 15 flush in device mode"]
77 #[inline(always)]
78 pub fn is_value4(&self) -> bool {
79 *self == TX_FNUM_A::VALUE4
80 }
81 #[doc = "Flush all the transmit FIFOs in device or host mode."]
82 #[inline(always)]
83 pub fn is_value5(&self) -> bool {
84 *self == TX_FNUM_A::VALUE5
85 }
86}
87#[doc = "Field `TxFNum` writer - TxFIFO Number"]
88pub type TX_FNUM_W<'a, REG> = crate::FieldWriter<'a, REG, 5, TX_FNUM_A>;
89impl<'a, REG> TX_FNUM_W<'a, REG>
90where
91 REG: crate::Writable + crate::RegisterSpec,
92 REG::Ux: From<u8>,
93{
94 #[doc = "Non-periodic TxFIFO flush in Host mode or Tx FIFO 0 flush in device mode"]
95 #[inline(always)]
96 pub fn value1(self) -> &'a mut crate::W<REG> {
97 self.variant(TX_FNUM_A::VALUE1)
98 }
99 #[doc = "Periodic TxFIFO flush in Host mode or Tx FIFO 1 flush in device mode"]
100 #[inline(always)]
101 pub fn value2(self) -> &'a mut crate::W<REG> {
102 self.variant(TX_FNUM_A::VALUE2)
103 }
104 #[doc = "Tx FIFO 2 flush in device mode"]
105 #[inline(always)]
106 pub fn value3(self) -> &'a mut crate::W<REG> {
107 self.variant(TX_FNUM_A::VALUE3)
108 }
109 #[doc = "Tx FIFO 15 flush in device mode"]
110 #[inline(always)]
111 pub fn value4(self) -> &'a mut crate::W<REG> {
112 self.variant(TX_FNUM_A::VALUE4)
113 }
114 #[doc = "Flush all the transmit FIFOs in device or host mode."]
115 #[inline(always)]
116 pub fn value5(self) -> &'a mut crate::W<REG> {
117 self.variant(TX_FNUM_A::VALUE5)
118 }
119}
120#[doc = "Field `DMAReq` reader - DMA Request Signal"]
121pub type DMAREQ_R = crate::BitReader;
122#[doc = "Field `AHBIdle` reader - AHB Master Idle"]
123pub type AHBIDLE_R = crate::BitReader;
124impl R {
125 #[doc = "Bit 0 - Core Soft Reset"]
126 #[inline(always)]
127 pub fn csft_rst(&self) -> CSFT_RST_R {
128 CSFT_RST_R::new((self.bits & 1) != 0)
129 }
130 #[doc = "Bit 2 - Host Frame Counter Reset"]
131 #[inline(always)]
132 pub fn frm_cntr_rst(&self) -> FRM_CNTR_RST_R {
133 FRM_CNTR_RST_R::new(((self.bits >> 2) & 1) != 0)
134 }
135 #[doc = "Bit 4 - RxFIFO Flush"]
136 #[inline(always)]
137 pub fn rx_fflsh(&self) -> RX_FFLSH_R {
138 RX_FFLSH_R::new(((self.bits >> 4) & 1) != 0)
139 }
140 #[doc = "Bit 5 - TxFIFO Flush"]
141 #[inline(always)]
142 pub fn tx_fflsh(&self) -> TX_FFLSH_R {
143 TX_FFLSH_R::new(((self.bits >> 5) & 1) != 0)
144 }
145 #[doc = "Bits 6:10 - TxFIFO Number"]
146 #[inline(always)]
147 pub fn tx_fnum(&self) -> TX_FNUM_R {
148 TX_FNUM_R::new(((self.bits >> 6) & 0x1f) as u8)
149 }
150 #[doc = "Bit 30 - DMA Request Signal"]
151 #[inline(always)]
152 pub fn dmareq(&self) -> DMAREQ_R {
153 DMAREQ_R::new(((self.bits >> 30) & 1) != 0)
154 }
155 #[doc = "Bit 31 - AHB Master Idle"]
156 #[inline(always)]
157 pub fn ahbidle(&self) -> AHBIDLE_R {
158 AHBIDLE_R::new(((self.bits >> 31) & 1) != 0)
159 }
160}
161impl W {
162 #[doc = "Bit 0 - Core Soft Reset"]
163 #[inline(always)]
164 pub fn csft_rst(&mut self) -> CSFT_RST_W<GRSTCTL_SPEC> {
165 CSFT_RST_W::new(self, 0)
166 }
167 #[doc = "Bit 2 - Host Frame Counter Reset"]
168 #[inline(always)]
169 pub fn frm_cntr_rst(&mut self) -> FRM_CNTR_RST_W<GRSTCTL_SPEC> {
170 FRM_CNTR_RST_W::new(self, 2)
171 }
172 #[doc = "Bit 4 - RxFIFO Flush"]
173 #[inline(always)]
174 pub fn rx_fflsh(&mut self) -> RX_FFLSH_W<GRSTCTL_SPEC> {
175 RX_FFLSH_W::new(self, 4)
176 }
177 #[doc = "Bit 5 - TxFIFO Flush"]
178 #[inline(always)]
179 pub fn tx_fflsh(&mut self) -> TX_FFLSH_W<GRSTCTL_SPEC> {
180 TX_FFLSH_W::new(self, 5)
181 }
182 #[doc = "Bits 6:10 - TxFIFO Number"]
183 #[inline(always)]
184 pub fn tx_fnum(&mut self) -> TX_FNUM_W<GRSTCTL_SPEC> {
185 TX_FNUM_W::new(self, 6)
186 }
187}
188#[doc = "Reset Register\n\nYou can [`read`](crate::Reg::read) this register and get [`grstctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`grstctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
189pub struct GRSTCTL_SPEC;
190impl crate::RegisterSpec for GRSTCTL_SPEC {
191 type Ux = u32;
192}
193#[doc = "`read()` method returns [`grstctl::R`](R) reader structure"]
194impl crate::Readable for GRSTCTL_SPEC {}
195#[doc = "`write(|w| ..)` method takes [`grstctl::W`](W) writer structure"]
196impl crate::Writable for GRSTCTL_SPEC {
197 type Safety = crate::Unsafe;
198 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
199 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
200}
201#[doc = "`reset()` method sets GRSTCTL to value 0x1000_0000"]
202impl crate::Resettable for GRSTCTL_SPEC {
203 const RESET_VALUE: u32 = 0x1000_0000;
204}