xmc4700/posif0/
pconf.rs

1#[doc = "Register `PCONF` reader"]
2pub type R = crate::R<PCONF_SPEC>;
3#[doc = "Register `PCONF` writer"]
4pub type W = crate::W<PCONF_SPEC>;
5#[doc = "Function Selector\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum FSEL_A {
9    #[doc = "0: Hall Sensor Mode enabled"]
10    VALUE1 = 0,
11    #[doc = "1: Quadrature Decoder Mode enabled"]
12    VALUE2 = 1,
13    #[doc = "2: stand-alone Multi-Channel Mode enabled"]
14    VALUE3 = 2,
15    #[doc = "3: Quadrature Decoder and stand-alone Multi-Channel Mode enabled"]
16    VALUE4 = 3,
17}
18impl From<FSEL_A> for u8 {
19    #[inline(always)]
20    fn from(variant: FSEL_A) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for FSEL_A {
25    type Ux = u8;
26}
27impl crate::IsEnum for FSEL_A {}
28#[doc = "Field `FSEL` reader - Function Selector"]
29pub type FSEL_R = crate::FieldReader<FSEL_A>;
30impl FSEL_R {
31    #[doc = "Get enumerated values variant"]
32    #[inline(always)]
33    pub const fn variant(&self) -> FSEL_A {
34        match self.bits {
35            0 => FSEL_A::VALUE1,
36            1 => FSEL_A::VALUE2,
37            2 => FSEL_A::VALUE3,
38            3 => FSEL_A::VALUE4,
39            _ => unreachable!(),
40        }
41    }
42    #[doc = "Hall Sensor Mode enabled"]
43    #[inline(always)]
44    pub fn is_value1(&self) -> bool {
45        *self == FSEL_A::VALUE1
46    }
47    #[doc = "Quadrature Decoder Mode enabled"]
48    #[inline(always)]
49    pub fn is_value2(&self) -> bool {
50        *self == FSEL_A::VALUE2
51    }
52    #[doc = "stand-alone Multi-Channel Mode enabled"]
53    #[inline(always)]
54    pub fn is_value3(&self) -> bool {
55        *self == FSEL_A::VALUE3
56    }
57    #[doc = "Quadrature Decoder and stand-alone Multi-Channel Mode enabled"]
58    #[inline(always)]
59    pub fn is_value4(&self) -> bool {
60        *self == FSEL_A::VALUE4
61    }
62}
63#[doc = "Field `FSEL` writer - Function Selector"]
64pub type FSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, FSEL_A, crate::Safe>;
65impl<'a, REG> FSEL_W<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "Hall Sensor Mode enabled"]
71    #[inline(always)]
72    pub fn value1(self) -> &'a mut crate::W<REG> {
73        self.variant(FSEL_A::VALUE1)
74    }
75    #[doc = "Quadrature Decoder Mode enabled"]
76    #[inline(always)]
77    pub fn value2(self) -> &'a mut crate::W<REG> {
78        self.variant(FSEL_A::VALUE2)
79    }
80    #[doc = "stand-alone Multi-Channel Mode enabled"]
81    #[inline(always)]
82    pub fn value3(self) -> &'a mut crate::W<REG> {
83        self.variant(FSEL_A::VALUE3)
84    }
85    #[doc = "Quadrature Decoder and stand-alone Multi-Channel Mode enabled"]
86    #[inline(always)]
87    pub fn value4(self) -> &'a mut crate::W<REG> {
88        self.variant(FSEL_A::VALUE4)
89    }
90}
91#[doc = "Position Decoder Mode selection\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq, Eq)]
93pub enum QDCM_A {
94    #[doc = "0: Position encoder is in Quadrature Mode"]
95    VALUE1 = 0,
96    #[doc = "1: Position encoder is in Direction Count Mode."]
97    VALUE2 = 1,
98}
99impl From<QDCM_A> for bool {
100    #[inline(always)]
101    fn from(variant: QDCM_A) -> Self {
102        variant as u8 != 0
103    }
104}
105#[doc = "Field `QDCM` reader - Position Decoder Mode selection"]
106pub type QDCM_R = crate::BitReader<QDCM_A>;
107impl QDCM_R {
108    #[doc = "Get enumerated values variant"]
109    #[inline(always)]
110    pub const fn variant(&self) -> QDCM_A {
111        match self.bits {
112            false => QDCM_A::VALUE1,
113            true => QDCM_A::VALUE2,
114        }
115    }
116    #[doc = "Position encoder is in Quadrature Mode"]
117    #[inline(always)]
118    pub fn is_value1(&self) -> bool {
119        *self == QDCM_A::VALUE1
120    }
121    #[doc = "Position encoder is in Direction Count Mode."]
122    #[inline(always)]
123    pub fn is_value2(&self) -> bool {
124        *self == QDCM_A::VALUE2
125    }
126}
127#[doc = "Field `QDCM` writer - Position Decoder Mode selection"]
128pub type QDCM_W<'a, REG> = crate::BitWriter<'a, REG, QDCM_A>;
129impl<'a, REG> QDCM_W<'a, REG>
130where
131    REG: crate::Writable + crate::RegisterSpec,
132{
133    #[doc = "Position encoder is in Quadrature Mode"]
134    #[inline(always)]
135    pub fn value1(self) -> &'a mut crate::W<REG> {
136        self.variant(QDCM_A::VALUE1)
137    }
138    #[doc = "Position encoder is in Direction Count Mode."]
139    #[inline(always)]
140    pub fn value2(self) -> &'a mut crate::W<REG> {
141        self.variant(QDCM_A::VALUE2)
142    }
143}
144#[doc = "Field `HIDG` reader - Idle generation enable"]
145pub type HIDG_R = crate::BitReader;
146#[doc = "Field `HIDG` writer - Idle generation enable"]
147pub type HIDG_W<'a, REG> = crate::BitWriter<'a, REG>;
148#[doc = "Multi-Channel Pattern SW update enable\n\nValue on reset: 0"]
149#[derive(Clone, Copy, Debug, PartialEq, Eq)]
150pub enum MCUE_A {
151    #[doc = "0: Multi-Channel pattern update is controlled via HW"]
152    VALUE1 = 0,
153    #[doc = "1: Multi-Channel pattern update is controlled via SW"]
154    VALUE2 = 1,
155}
156impl From<MCUE_A> for bool {
157    #[inline(always)]
158    fn from(variant: MCUE_A) -> Self {
159        variant as u8 != 0
160    }
161}
162#[doc = "Field `MCUE` reader - Multi-Channel Pattern SW update enable"]
163pub type MCUE_R = crate::BitReader<MCUE_A>;
164impl MCUE_R {
165    #[doc = "Get enumerated values variant"]
166    #[inline(always)]
167    pub const fn variant(&self) -> MCUE_A {
168        match self.bits {
169            false => MCUE_A::VALUE1,
170            true => MCUE_A::VALUE2,
171        }
172    }
173    #[doc = "Multi-Channel pattern update is controlled via HW"]
174    #[inline(always)]
175    pub fn is_value1(&self) -> bool {
176        *self == MCUE_A::VALUE1
177    }
178    #[doc = "Multi-Channel pattern update is controlled via SW"]
179    #[inline(always)]
180    pub fn is_value2(&self) -> bool {
181        *self == MCUE_A::VALUE2
182    }
183}
184#[doc = "Field `MCUE` writer - Multi-Channel Pattern SW update enable"]
185pub type MCUE_W<'a, REG> = crate::BitWriter<'a, REG, MCUE_A>;
186impl<'a, REG> MCUE_W<'a, REG>
187where
188    REG: crate::Writable + crate::RegisterSpec,
189{
190    #[doc = "Multi-Channel pattern update is controlled via HW"]
191    #[inline(always)]
192    pub fn value1(self) -> &'a mut crate::W<REG> {
193        self.variant(MCUE_A::VALUE1)
194    }
195    #[doc = "Multi-Channel pattern update is controlled via SW"]
196    #[inline(always)]
197    pub fn value2(self) -> &'a mut crate::W<REG> {
198        self.variant(MCUE_A::VALUE2)
199    }
200}
201#[doc = "PhaseA/Hal input 1 selector\n\nValue on reset: 0"]
202#[derive(Clone, Copy, Debug, PartialEq, Eq)]
203#[repr(u8)]
204pub enum INSEL0_A {
205    #[doc = "0: POSIFx.IN0A"]
206    VALUE1 = 0,
207    #[doc = "1: POSIFx.IN0B"]
208    VALUE2 = 1,
209    #[doc = "2: POSIFx.IN0C"]
210    VALUE3 = 2,
211    #[doc = "3: POSIFx.IN0D"]
212    VALUE4 = 3,
213}
214impl From<INSEL0_A> for u8 {
215    #[inline(always)]
216    fn from(variant: INSEL0_A) -> Self {
217        variant as _
218    }
219}
220impl crate::FieldSpec for INSEL0_A {
221    type Ux = u8;
222}
223impl crate::IsEnum for INSEL0_A {}
224#[doc = "Field `INSEL0` reader - PhaseA/Hal input 1 selector"]
225pub type INSEL0_R = crate::FieldReader<INSEL0_A>;
226impl INSEL0_R {
227    #[doc = "Get enumerated values variant"]
228    #[inline(always)]
229    pub const fn variant(&self) -> INSEL0_A {
230        match self.bits {
231            0 => INSEL0_A::VALUE1,
232            1 => INSEL0_A::VALUE2,
233            2 => INSEL0_A::VALUE3,
234            3 => INSEL0_A::VALUE4,
235            _ => unreachable!(),
236        }
237    }
238    #[doc = "POSIFx.IN0A"]
239    #[inline(always)]
240    pub fn is_value1(&self) -> bool {
241        *self == INSEL0_A::VALUE1
242    }
243    #[doc = "POSIFx.IN0B"]
244    #[inline(always)]
245    pub fn is_value2(&self) -> bool {
246        *self == INSEL0_A::VALUE2
247    }
248    #[doc = "POSIFx.IN0C"]
249    #[inline(always)]
250    pub fn is_value3(&self) -> bool {
251        *self == INSEL0_A::VALUE3
252    }
253    #[doc = "POSIFx.IN0D"]
254    #[inline(always)]
255    pub fn is_value4(&self) -> bool {
256        *self == INSEL0_A::VALUE4
257    }
258}
259#[doc = "Field `INSEL0` writer - PhaseA/Hal input 1 selector"]
260pub type INSEL0_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INSEL0_A, crate::Safe>;
261impl<'a, REG> INSEL0_W<'a, REG>
262where
263    REG: crate::Writable + crate::RegisterSpec,
264    REG::Ux: From<u8>,
265{
266    #[doc = "POSIFx.IN0A"]
267    #[inline(always)]
268    pub fn value1(self) -> &'a mut crate::W<REG> {
269        self.variant(INSEL0_A::VALUE1)
270    }
271    #[doc = "POSIFx.IN0B"]
272    #[inline(always)]
273    pub fn value2(self) -> &'a mut crate::W<REG> {
274        self.variant(INSEL0_A::VALUE2)
275    }
276    #[doc = "POSIFx.IN0C"]
277    #[inline(always)]
278    pub fn value3(self) -> &'a mut crate::W<REG> {
279        self.variant(INSEL0_A::VALUE3)
280    }
281    #[doc = "POSIFx.IN0D"]
282    #[inline(always)]
283    pub fn value4(self) -> &'a mut crate::W<REG> {
284        self.variant(INSEL0_A::VALUE4)
285    }
286}
287#[doc = "PhaseB/Hall input 2 selector\n\nValue on reset: 0"]
288#[derive(Clone, Copy, Debug, PartialEq, Eq)]
289#[repr(u8)]
290pub enum INSEL1_A {
291    #[doc = "0: POSIFx.IN1A"]
292    VALUE1 = 0,
293    #[doc = "1: POSIFx.IN1B"]
294    VALUE2 = 1,
295    #[doc = "2: POSIFx.IN1C"]
296    VALUE3 = 2,
297    #[doc = "3: POSIFx.IN1D"]
298    VALUE4 = 3,
299}
300impl From<INSEL1_A> for u8 {
301    #[inline(always)]
302    fn from(variant: INSEL1_A) -> Self {
303        variant as _
304    }
305}
306impl crate::FieldSpec for INSEL1_A {
307    type Ux = u8;
308}
309impl crate::IsEnum for INSEL1_A {}
310#[doc = "Field `INSEL1` reader - PhaseB/Hall input 2 selector"]
311pub type INSEL1_R = crate::FieldReader<INSEL1_A>;
312impl INSEL1_R {
313    #[doc = "Get enumerated values variant"]
314    #[inline(always)]
315    pub const fn variant(&self) -> INSEL1_A {
316        match self.bits {
317            0 => INSEL1_A::VALUE1,
318            1 => INSEL1_A::VALUE2,
319            2 => INSEL1_A::VALUE3,
320            3 => INSEL1_A::VALUE4,
321            _ => unreachable!(),
322        }
323    }
324    #[doc = "POSIFx.IN1A"]
325    #[inline(always)]
326    pub fn is_value1(&self) -> bool {
327        *self == INSEL1_A::VALUE1
328    }
329    #[doc = "POSIFx.IN1B"]
330    #[inline(always)]
331    pub fn is_value2(&self) -> bool {
332        *self == INSEL1_A::VALUE2
333    }
334    #[doc = "POSIFx.IN1C"]
335    #[inline(always)]
336    pub fn is_value3(&self) -> bool {
337        *self == INSEL1_A::VALUE3
338    }
339    #[doc = "POSIFx.IN1D"]
340    #[inline(always)]
341    pub fn is_value4(&self) -> bool {
342        *self == INSEL1_A::VALUE4
343    }
344}
345#[doc = "Field `INSEL1` writer - PhaseB/Hall input 2 selector"]
346pub type INSEL1_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INSEL1_A, crate::Safe>;
347impl<'a, REG> INSEL1_W<'a, REG>
348where
349    REG: crate::Writable + crate::RegisterSpec,
350    REG::Ux: From<u8>,
351{
352    #[doc = "POSIFx.IN1A"]
353    #[inline(always)]
354    pub fn value1(self) -> &'a mut crate::W<REG> {
355        self.variant(INSEL1_A::VALUE1)
356    }
357    #[doc = "POSIFx.IN1B"]
358    #[inline(always)]
359    pub fn value2(self) -> &'a mut crate::W<REG> {
360        self.variant(INSEL1_A::VALUE2)
361    }
362    #[doc = "POSIFx.IN1C"]
363    #[inline(always)]
364    pub fn value3(self) -> &'a mut crate::W<REG> {
365        self.variant(INSEL1_A::VALUE3)
366    }
367    #[doc = "POSIFx.IN1D"]
368    #[inline(always)]
369    pub fn value4(self) -> &'a mut crate::W<REG> {
370        self.variant(INSEL1_A::VALUE4)
371    }
372}
373#[doc = "Index/Hall input 3 selector\n\nValue on reset: 0"]
374#[derive(Clone, Copy, Debug, PartialEq, Eq)]
375#[repr(u8)]
376pub enum INSEL2_A {
377    #[doc = "0: POSIFx.IN2A"]
378    VALUE1 = 0,
379    #[doc = "1: POSIFx.IN2B"]
380    VALUE2 = 1,
381    #[doc = "2: POSIFx.IN2C"]
382    VALUE3 = 2,
383    #[doc = "3: POSIFx.IN2D"]
384    VALUE4 = 3,
385}
386impl From<INSEL2_A> for u8 {
387    #[inline(always)]
388    fn from(variant: INSEL2_A) -> Self {
389        variant as _
390    }
391}
392impl crate::FieldSpec for INSEL2_A {
393    type Ux = u8;
394}
395impl crate::IsEnum for INSEL2_A {}
396#[doc = "Field `INSEL2` reader - Index/Hall input 3 selector"]
397pub type INSEL2_R = crate::FieldReader<INSEL2_A>;
398impl INSEL2_R {
399    #[doc = "Get enumerated values variant"]
400    #[inline(always)]
401    pub const fn variant(&self) -> INSEL2_A {
402        match self.bits {
403            0 => INSEL2_A::VALUE1,
404            1 => INSEL2_A::VALUE2,
405            2 => INSEL2_A::VALUE3,
406            3 => INSEL2_A::VALUE4,
407            _ => unreachable!(),
408        }
409    }
410    #[doc = "POSIFx.IN2A"]
411    #[inline(always)]
412    pub fn is_value1(&self) -> bool {
413        *self == INSEL2_A::VALUE1
414    }
415    #[doc = "POSIFx.IN2B"]
416    #[inline(always)]
417    pub fn is_value2(&self) -> bool {
418        *self == INSEL2_A::VALUE2
419    }
420    #[doc = "POSIFx.IN2C"]
421    #[inline(always)]
422    pub fn is_value3(&self) -> bool {
423        *self == INSEL2_A::VALUE3
424    }
425    #[doc = "POSIFx.IN2D"]
426    #[inline(always)]
427    pub fn is_value4(&self) -> bool {
428        *self == INSEL2_A::VALUE4
429    }
430}
431#[doc = "Field `INSEL2` writer - Index/Hall input 3 selector"]
432pub type INSEL2_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INSEL2_A, crate::Safe>;
433impl<'a, REG> INSEL2_W<'a, REG>
434where
435    REG: crate::Writable + crate::RegisterSpec,
436    REG::Ux: From<u8>,
437{
438    #[doc = "POSIFx.IN2A"]
439    #[inline(always)]
440    pub fn value1(self) -> &'a mut crate::W<REG> {
441        self.variant(INSEL2_A::VALUE1)
442    }
443    #[doc = "POSIFx.IN2B"]
444    #[inline(always)]
445    pub fn value2(self) -> &'a mut crate::W<REG> {
446        self.variant(INSEL2_A::VALUE2)
447    }
448    #[doc = "POSIFx.IN2C"]
449    #[inline(always)]
450    pub fn value3(self) -> &'a mut crate::W<REG> {
451        self.variant(INSEL2_A::VALUE3)
452    }
453    #[doc = "POSIFx.IN2D"]
454    #[inline(always)]
455    pub fn value4(self) -> &'a mut crate::W<REG> {
456        self.variant(INSEL2_A::VALUE4)
457    }
458}
459#[doc = "Delay Pin selector\n\nValue on reset: 0"]
460#[derive(Clone, Copy, Debug, PartialEq, Eq)]
461pub enum DSEL_A {
462    #[doc = "0: POSIFx.HSDA"]
463    VALUE1 = 0,
464    #[doc = "1: POSIFx.HSDB"]
465    VALUE2 = 1,
466}
467impl From<DSEL_A> for bool {
468    #[inline(always)]
469    fn from(variant: DSEL_A) -> Self {
470        variant as u8 != 0
471    }
472}
473#[doc = "Field `DSEL` reader - Delay Pin selector"]
474pub type DSEL_R = crate::BitReader<DSEL_A>;
475impl DSEL_R {
476    #[doc = "Get enumerated values variant"]
477    #[inline(always)]
478    pub const fn variant(&self) -> DSEL_A {
479        match self.bits {
480            false => DSEL_A::VALUE1,
481            true => DSEL_A::VALUE2,
482        }
483    }
484    #[doc = "POSIFx.HSDA"]
485    #[inline(always)]
486    pub fn is_value1(&self) -> bool {
487        *self == DSEL_A::VALUE1
488    }
489    #[doc = "POSIFx.HSDB"]
490    #[inline(always)]
491    pub fn is_value2(&self) -> bool {
492        *self == DSEL_A::VALUE2
493    }
494}
495#[doc = "Field `DSEL` writer - Delay Pin selector"]
496pub type DSEL_W<'a, REG> = crate::BitWriter<'a, REG, DSEL_A>;
497impl<'a, REG> DSEL_W<'a, REG>
498where
499    REG: crate::Writable + crate::RegisterSpec,
500{
501    #[doc = "POSIFx.HSDA"]
502    #[inline(always)]
503    pub fn value1(self) -> &'a mut crate::W<REG> {
504        self.variant(DSEL_A::VALUE1)
505    }
506    #[doc = "POSIFx.HSDB"]
507    #[inline(always)]
508    pub fn value2(self) -> &'a mut crate::W<REG> {
509        self.variant(DSEL_A::VALUE2)
510    }
511}
512#[doc = "Edge selector for the sampling trigger\n\nValue on reset: 0"]
513#[derive(Clone, Copy, Debug, PartialEq, Eq)]
514pub enum SPES_A {
515    #[doc = "0: Rising edge"]
516    VALUE1 = 0,
517    #[doc = "1: Falling edge"]
518    VALUE2 = 1,
519}
520impl From<SPES_A> for bool {
521    #[inline(always)]
522    fn from(variant: SPES_A) -> Self {
523        variant as u8 != 0
524    }
525}
526#[doc = "Field `SPES` reader - Edge selector for the sampling trigger"]
527pub type SPES_R = crate::BitReader<SPES_A>;
528impl SPES_R {
529    #[doc = "Get enumerated values variant"]
530    #[inline(always)]
531    pub const fn variant(&self) -> SPES_A {
532        match self.bits {
533            false => SPES_A::VALUE1,
534            true => SPES_A::VALUE2,
535        }
536    }
537    #[doc = "Rising edge"]
538    #[inline(always)]
539    pub fn is_value1(&self) -> bool {
540        *self == SPES_A::VALUE1
541    }
542    #[doc = "Falling edge"]
543    #[inline(always)]
544    pub fn is_value2(&self) -> bool {
545        *self == SPES_A::VALUE2
546    }
547}
548#[doc = "Field `SPES` writer - Edge selector for the sampling trigger"]
549pub type SPES_W<'a, REG> = crate::BitWriter<'a, REG, SPES_A>;
550impl<'a, REG> SPES_W<'a, REG>
551where
552    REG: crate::Writable + crate::RegisterSpec,
553{
554    #[doc = "Rising edge"]
555    #[inline(always)]
556    pub fn value1(self) -> &'a mut crate::W<REG> {
557        self.variant(SPES_A::VALUE1)
558    }
559    #[doc = "Falling edge"]
560    #[inline(always)]
561    pub fn value2(self) -> &'a mut crate::W<REG> {
562        self.variant(SPES_A::VALUE2)
563    }
564}
565#[doc = "Pattern update signal select\n\nValue on reset: 0"]
566#[derive(Clone, Copy, Debug, PartialEq, Eq)]
567#[repr(u8)]
568pub enum MSETS_A {
569    #[doc = "0: POSIFx.MSETA"]
570    VALUE1 = 0,
571    #[doc = "1: POSIFx.MSETB"]
572    VALUE2 = 1,
573    #[doc = "2: POSIFx.MSETC"]
574    VALUE3 = 2,
575    #[doc = "3: POSIFx.MSETD"]
576    VALUE4 = 3,
577    #[doc = "4: POSIFx.MSETE"]
578    VALUE5 = 4,
579    #[doc = "5: POSIFx.MSETF"]
580    VALUE6 = 5,
581    #[doc = "6: POSIFx.MSETG"]
582    VALUE7 = 6,
583    #[doc = "7: POSIFx.MSETH"]
584    VALUE8 = 7,
585}
586impl From<MSETS_A> for u8 {
587    #[inline(always)]
588    fn from(variant: MSETS_A) -> Self {
589        variant as _
590    }
591}
592impl crate::FieldSpec for MSETS_A {
593    type Ux = u8;
594}
595impl crate::IsEnum for MSETS_A {}
596#[doc = "Field `MSETS` reader - Pattern update signal select"]
597pub type MSETS_R = crate::FieldReader<MSETS_A>;
598impl MSETS_R {
599    #[doc = "Get enumerated values variant"]
600    #[inline(always)]
601    pub const fn variant(&self) -> MSETS_A {
602        match self.bits {
603            0 => MSETS_A::VALUE1,
604            1 => MSETS_A::VALUE2,
605            2 => MSETS_A::VALUE3,
606            3 => MSETS_A::VALUE4,
607            4 => MSETS_A::VALUE5,
608            5 => MSETS_A::VALUE6,
609            6 => MSETS_A::VALUE7,
610            7 => MSETS_A::VALUE8,
611            _ => unreachable!(),
612        }
613    }
614    #[doc = "POSIFx.MSETA"]
615    #[inline(always)]
616    pub fn is_value1(&self) -> bool {
617        *self == MSETS_A::VALUE1
618    }
619    #[doc = "POSIFx.MSETB"]
620    #[inline(always)]
621    pub fn is_value2(&self) -> bool {
622        *self == MSETS_A::VALUE2
623    }
624    #[doc = "POSIFx.MSETC"]
625    #[inline(always)]
626    pub fn is_value3(&self) -> bool {
627        *self == MSETS_A::VALUE3
628    }
629    #[doc = "POSIFx.MSETD"]
630    #[inline(always)]
631    pub fn is_value4(&self) -> bool {
632        *self == MSETS_A::VALUE4
633    }
634    #[doc = "POSIFx.MSETE"]
635    #[inline(always)]
636    pub fn is_value5(&self) -> bool {
637        *self == MSETS_A::VALUE5
638    }
639    #[doc = "POSIFx.MSETF"]
640    #[inline(always)]
641    pub fn is_value6(&self) -> bool {
642        *self == MSETS_A::VALUE6
643    }
644    #[doc = "POSIFx.MSETG"]
645    #[inline(always)]
646    pub fn is_value7(&self) -> bool {
647        *self == MSETS_A::VALUE7
648    }
649    #[doc = "POSIFx.MSETH"]
650    #[inline(always)]
651    pub fn is_value8(&self) -> bool {
652        *self == MSETS_A::VALUE8
653    }
654}
655#[doc = "Field `MSETS` writer - Pattern update signal select"]
656pub type MSETS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, MSETS_A, crate::Safe>;
657impl<'a, REG> MSETS_W<'a, REG>
658where
659    REG: crate::Writable + crate::RegisterSpec,
660    REG::Ux: From<u8>,
661{
662    #[doc = "POSIFx.MSETA"]
663    #[inline(always)]
664    pub fn value1(self) -> &'a mut crate::W<REG> {
665        self.variant(MSETS_A::VALUE1)
666    }
667    #[doc = "POSIFx.MSETB"]
668    #[inline(always)]
669    pub fn value2(self) -> &'a mut crate::W<REG> {
670        self.variant(MSETS_A::VALUE2)
671    }
672    #[doc = "POSIFx.MSETC"]
673    #[inline(always)]
674    pub fn value3(self) -> &'a mut crate::W<REG> {
675        self.variant(MSETS_A::VALUE3)
676    }
677    #[doc = "POSIFx.MSETD"]
678    #[inline(always)]
679    pub fn value4(self) -> &'a mut crate::W<REG> {
680        self.variant(MSETS_A::VALUE4)
681    }
682    #[doc = "POSIFx.MSETE"]
683    #[inline(always)]
684    pub fn value5(self) -> &'a mut crate::W<REG> {
685        self.variant(MSETS_A::VALUE5)
686    }
687    #[doc = "POSIFx.MSETF"]
688    #[inline(always)]
689    pub fn value6(self) -> &'a mut crate::W<REG> {
690        self.variant(MSETS_A::VALUE6)
691    }
692    #[doc = "POSIFx.MSETG"]
693    #[inline(always)]
694    pub fn value7(self) -> &'a mut crate::W<REG> {
695        self.variant(MSETS_A::VALUE7)
696    }
697    #[doc = "POSIFx.MSETH"]
698    #[inline(always)]
699    pub fn value8(self) -> &'a mut crate::W<REG> {
700        self.variant(MSETS_A::VALUE8)
701    }
702}
703#[doc = "Multi-Channel pattern update trigger edge\n\nValue on reset: 0"]
704#[derive(Clone, Copy, Debug, PartialEq, Eq)]
705pub enum MSES_A {
706    #[doc = "0: The signal used to enable a pattern update is active on the rising edge"]
707    VALUE1 = 0,
708    #[doc = "1: The signal used to enable a pattern update is active on the falling edge"]
709    VALUE2 = 1,
710}
711impl From<MSES_A> for bool {
712    #[inline(always)]
713    fn from(variant: MSES_A) -> Self {
714        variant as u8 != 0
715    }
716}
717#[doc = "Field `MSES` reader - Multi-Channel pattern update trigger edge"]
718pub type MSES_R = crate::BitReader<MSES_A>;
719impl MSES_R {
720    #[doc = "Get enumerated values variant"]
721    #[inline(always)]
722    pub const fn variant(&self) -> MSES_A {
723        match self.bits {
724            false => MSES_A::VALUE1,
725            true => MSES_A::VALUE2,
726        }
727    }
728    #[doc = "The signal used to enable a pattern update is active on the rising edge"]
729    #[inline(always)]
730    pub fn is_value1(&self) -> bool {
731        *self == MSES_A::VALUE1
732    }
733    #[doc = "The signal used to enable a pattern update is active on the falling edge"]
734    #[inline(always)]
735    pub fn is_value2(&self) -> bool {
736        *self == MSES_A::VALUE2
737    }
738}
739#[doc = "Field `MSES` writer - Multi-Channel pattern update trigger edge"]
740pub type MSES_W<'a, REG> = crate::BitWriter<'a, REG, MSES_A>;
741impl<'a, REG> MSES_W<'a, REG>
742where
743    REG: crate::Writable + crate::RegisterSpec,
744{
745    #[doc = "The signal used to enable a pattern update is active on the rising edge"]
746    #[inline(always)]
747    pub fn value1(self) -> &'a mut crate::W<REG> {
748        self.variant(MSES_A::VALUE1)
749    }
750    #[doc = "The signal used to enable a pattern update is active on the falling edge"]
751    #[inline(always)]
752    pub fn value2(self) -> &'a mut crate::W<REG> {
753        self.variant(MSES_A::VALUE2)
754    }
755}
756#[doc = "PWM synchronization signal selector\n\nValue on reset: 0"]
757#[derive(Clone, Copy, Debug, PartialEq, Eq)]
758#[repr(u8)]
759pub enum MSYNS_A {
760    #[doc = "0: POSIFx.MSYNCA"]
761    VALUE1 = 0,
762    #[doc = "1: POSIFx.MSYNCB"]
763    VALUE2 = 1,
764    #[doc = "2: POSIFx.MSYNCC"]
765    VALUE3 = 2,
766    #[doc = "3: POSIFx.MSYNCD"]
767    VALUE4 = 3,
768}
769impl From<MSYNS_A> for u8 {
770    #[inline(always)]
771    fn from(variant: MSYNS_A) -> Self {
772        variant as _
773    }
774}
775impl crate::FieldSpec for MSYNS_A {
776    type Ux = u8;
777}
778impl crate::IsEnum for MSYNS_A {}
779#[doc = "Field `MSYNS` reader - PWM synchronization signal selector"]
780pub type MSYNS_R = crate::FieldReader<MSYNS_A>;
781impl MSYNS_R {
782    #[doc = "Get enumerated values variant"]
783    #[inline(always)]
784    pub const fn variant(&self) -> MSYNS_A {
785        match self.bits {
786            0 => MSYNS_A::VALUE1,
787            1 => MSYNS_A::VALUE2,
788            2 => MSYNS_A::VALUE3,
789            3 => MSYNS_A::VALUE4,
790            _ => unreachable!(),
791        }
792    }
793    #[doc = "POSIFx.MSYNCA"]
794    #[inline(always)]
795    pub fn is_value1(&self) -> bool {
796        *self == MSYNS_A::VALUE1
797    }
798    #[doc = "POSIFx.MSYNCB"]
799    #[inline(always)]
800    pub fn is_value2(&self) -> bool {
801        *self == MSYNS_A::VALUE2
802    }
803    #[doc = "POSIFx.MSYNCC"]
804    #[inline(always)]
805    pub fn is_value3(&self) -> bool {
806        *self == MSYNS_A::VALUE3
807    }
808    #[doc = "POSIFx.MSYNCD"]
809    #[inline(always)]
810    pub fn is_value4(&self) -> bool {
811        *self == MSYNS_A::VALUE4
812    }
813}
814#[doc = "Field `MSYNS` writer - PWM synchronization signal selector"]
815pub type MSYNS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, MSYNS_A, crate::Safe>;
816impl<'a, REG> MSYNS_W<'a, REG>
817where
818    REG: crate::Writable + crate::RegisterSpec,
819    REG::Ux: From<u8>,
820{
821    #[doc = "POSIFx.MSYNCA"]
822    #[inline(always)]
823    pub fn value1(self) -> &'a mut crate::W<REG> {
824        self.variant(MSYNS_A::VALUE1)
825    }
826    #[doc = "POSIFx.MSYNCB"]
827    #[inline(always)]
828    pub fn value2(self) -> &'a mut crate::W<REG> {
829        self.variant(MSYNS_A::VALUE2)
830    }
831    #[doc = "POSIFx.MSYNCC"]
832    #[inline(always)]
833    pub fn value3(self) -> &'a mut crate::W<REG> {
834        self.variant(MSYNS_A::VALUE3)
835    }
836    #[doc = "POSIFx.MSYNCD"]
837    #[inline(always)]
838    pub fn value4(self) -> &'a mut crate::W<REG> {
839        self.variant(MSYNS_A::VALUE4)
840    }
841}
842#[doc = "Wrong Hall Event selection\n\nValue on reset: 0"]
843#[derive(Clone, Copy, Debug, PartialEq, Eq)]
844#[repr(u8)]
845pub enum EWIS_A {
846    #[doc = "0: POSIFx.EWHEA"]
847    VALUE1 = 0,
848    #[doc = "1: POSIFx.EWHEB"]
849    VALUE2 = 1,
850    #[doc = "2: POSIFx.EWHEC"]
851    VALUE3 = 2,
852    #[doc = "3: POSIFx.EWHED"]
853    VALUE4 = 3,
854}
855impl From<EWIS_A> for u8 {
856    #[inline(always)]
857    fn from(variant: EWIS_A) -> Self {
858        variant as _
859    }
860}
861impl crate::FieldSpec for EWIS_A {
862    type Ux = u8;
863}
864impl crate::IsEnum for EWIS_A {}
865#[doc = "Field `EWIS` reader - Wrong Hall Event selection"]
866pub type EWIS_R = crate::FieldReader<EWIS_A>;
867impl EWIS_R {
868    #[doc = "Get enumerated values variant"]
869    #[inline(always)]
870    pub const fn variant(&self) -> EWIS_A {
871        match self.bits {
872            0 => EWIS_A::VALUE1,
873            1 => EWIS_A::VALUE2,
874            2 => EWIS_A::VALUE3,
875            3 => EWIS_A::VALUE4,
876            _ => unreachable!(),
877        }
878    }
879    #[doc = "POSIFx.EWHEA"]
880    #[inline(always)]
881    pub fn is_value1(&self) -> bool {
882        *self == EWIS_A::VALUE1
883    }
884    #[doc = "POSIFx.EWHEB"]
885    #[inline(always)]
886    pub fn is_value2(&self) -> bool {
887        *self == EWIS_A::VALUE2
888    }
889    #[doc = "POSIFx.EWHEC"]
890    #[inline(always)]
891    pub fn is_value3(&self) -> bool {
892        *self == EWIS_A::VALUE3
893    }
894    #[doc = "POSIFx.EWHED"]
895    #[inline(always)]
896    pub fn is_value4(&self) -> bool {
897        *self == EWIS_A::VALUE4
898    }
899}
900#[doc = "Field `EWIS` writer - Wrong Hall Event selection"]
901pub type EWIS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EWIS_A, crate::Safe>;
902impl<'a, REG> EWIS_W<'a, REG>
903where
904    REG: crate::Writable + crate::RegisterSpec,
905    REG::Ux: From<u8>,
906{
907    #[doc = "POSIFx.EWHEA"]
908    #[inline(always)]
909    pub fn value1(self) -> &'a mut crate::W<REG> {
910        self.variant(EWIS_A::VALUE1)
911    }
912    #[doc = "POSIFx.EWHEB"]
913    #[inline(always)]
914    pub fn value2(self) -> &'a mut crate::W<REG> {
915        self.variant(EWIS_A::VALUE2)
916    }
917    #[doc = "POSIFx.EWHEC"]
918    #[inline(always)]
919    pub fn value3(self) -> &'a mut crate::W<REG> {
920        self.variant(EWIS_A::VALUE3)
921    }
922    #[doc = "POSIFx.EWHED"]
923    #[inline(always)]
924    pub fn value4(self) -> &'a mut crate::W<REG> {
925        self.variant(EWIS_A::VALUE4)
926    }
927}
928#[doc = "External Wrong Hall Event enable\n\nValue on reset: 0"]
929#[derive(Clone, Copy, Debug, PartialEq, Eq)]
930pub enum EWIE_A {
931    #[doc = "0: External wrong hall event emulation signal, POSIFx.EWHE\\[D...A\\], is disabled"]
932    VALUE1 = 0,
933    #[doc = "1: External wrong hall event emulation signal, POSIFx.EWHE\\[D...A\\], is enabled."]
934    VALUE2 = 1,
935}
936impl From<EWIE_A> for bool {
937    #[inline(always)]
938    fn from(variant: EWIE_A) -> Self {
939        variant as u8 != 0
940    }
941}
942#[doc = "Field `EWIE` reader - External Wrong Hall Event enable"]
943pub type EWIE_R = crate::BitReader<EWIE_A>;
944impl EWIE_R {
945    #[doc = "Get enumerated values variant"]
946    #[inline(always)]
947    pub const fn variant(&self) -> EWIE_A {
948        match self.bits {
949            false => EWIE_A::VALUE1,
950            true => EWIE_A::VALUE2,
951        }
952    }
953    #[doc = "External wrong hall event emulation signal, POSIFx.EWHE\\[D...A\\], is disabled"]
954    #[inline(always)]
955    pub fn is_value1(&self) -> bool {
956        *self == EWIE_A::VALUE1
957    }
958    #[doc = "External wrong hall event emulation signal, POSIFx.EWHE\\[D...A\\], is enabled."]
959    #[inline(always)]
960    pub fn is_value2(&self) -> bool {
961        *self == EWIE_A::VALUE2
962    }
963}
964#[doc = "Field `EWIE` writer - External Wrong Hall Event enable"]
965pub type EWIE_W<'a, REG> = crate::BitWriter<'a, REG, EWIE_A>;
966impl<'a, REG> EWIE_W<'a, REG>
967where
968    REG: crate::Writable + crate::RegisterSpec,
969{
970    #[doc = "External wrong hall event emulation signal, POSIFx.EWHE\\[D...A\\], is disabled"]
971    #[inline(always)]
972    pub fn value1(self) -> &'a mut crate::W<REG> {
973        self.variant(EWIE_A::VALUE1)
974    }
975    #[doc = "External wrong hall event emulation signal, POSIFx.EWHE\\[D...A\\], is enabled."]
976    #[inline(always)]
977    pub fn value2(self) -> &'a mut crate::W<REG> {
978        self.variant(EWIE_A::VALUE2)
979    }
980}
981#[doc = "External Wrong Hall Event active level\n\nValue on reset: 0"]
982#[derive(Clone, Copy, Debug, PartialEq, Eq)]
983pub enum EWIL_A {
984    #[doc = "0: POSIFx.EWHE\\[D...A\\]
985signal is active HIGH"]
986    VALUE1 = 0,
987    #[doc = "1: POSIFx.EWHE\\[D...A\\]
988signal is active LOW"]
989    VALUE2 = 1,
990}
991impl From<EWIL_A> for bool {
992    #[inline(always)]
993    fn from(variant: EWIL_A) -> Self {
994        variant as u8 != 0
995    }
996}
997#[doc = "Field `EWIL` reader - External Wrong Hall Event active level"]
998pub type EWIL_R = crate::BitReader<EWIL_A>;
999impl EWIL_R {
1000    #[doc = "Get enumerated values variant"]
1001    #[inline(always)]
1002    pub const fn variant(&self) -> EWIL_A {
1003        match self.bits {
1004            false => EWIL_A::VALUE1,
1005            true => EWIL_A::VALUE2,
1006        }
1007    }
1008    #[doc = "POSIFx.EWHE\\[D...A\\]
1009signal is active HIGH"]
1010    #[inline(always)]
1011    pub fn is_value1(&self) -> bool {
1012        *self == EWIL_A::VALUE1
1013    }
1014    #[doc = "POSIFx.EWHE\\[D...A\\]
1015signal is active LOW"]
1016    #[inline(always)]
1017    pub fn is_value2(&self) -> bool {
1018        *self == EWIL_A::VALUE2
1019    }
1020}
1021#[doc = "Field `EWIL` writer - External Wrong Hall Event active level"]
1022pub type EWIL_W<'a, REG> = crate::BitWriter<'a, REG, EWIL_A>;
1023impl<'a, REG> EWIL_W<'a, REG>
1024where
1025    REG: crate::Writable + crate::RegisterSpec,
1026{
1027    #[doc = "POSIFx.EWHE\\[D...A\\]
1028signal is active HIGH"]
1029    #[inline(always)]
1030    pub fn value1(self) -> &'a mut crate::W<REG> {
1031        self.variant(EWIL_A::VALUE1)
1032    }
1033    #[doc = "POSIFx.EWHE\\[D...A\\]
1034signal is active LOW"]
1035    #[inline(always)]
1036    pub fn value2(self) -> &'a mut crate::W<REG> {
1037        self.variant(EWIL_A::VALUE2)
1038    }
1039}
1040#[doc = "Low Pass Filters Configuration\n\nValue on reset: 0"]
1041#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1042#[repr(u8)]
1043pub enum LPC_A {
1044    #[doc = "0: Low pass filter disabled"]
1045    VALUE1 = 0,
1046    #[doc = "1: Low pass of 1 clock cycle"]
1047    VALUE2 = 1,
1048    #[doc = "2: Low pass of 2 clock cycles"]
1049    VALUE3 = 2,
1050    #[doc = "3: Low pass of 4 clock cycles"]
1051    VALUE4 = 3,
1052    #[doc = "4: Low pass of 8 clock cycles"]
1053    VALUE5 = 4,
1054    #[doc = "5: Low pass of 16 clock cycles"]
1055    VALUE6 = 5,
1056    #[doc = "6: Low pass of 32 clock cycles"]
1057    VALUE7 = 6,
1058    #[doc = "7: Low pass of 64 clock cycles"]
1059    VALUE8 = 7,
1060}
1061impl From<LPC_A> for u8 {
1062    #[inline(always)]
1063    fn from(variant: LPC_A) -> Self {
1064        variant as _
1065    }
1066}
1067impl crate::FieldSpec for LPC_A {
1068    type Ux = u8;
1069}
1070impl crate::IsEnum for LPC_A {}
1071#[doc = "Field `LPC` reader - Low Pass Filters Configuration"]
1072pub type LPC_R = crate::FieldReader<LPC_A>;
1073impl LPC_R {
1074    #[doc = "Get enumerated values variant"]
1075    #[inline(always)]
1076    pub const fn variant(&self) -> LPC_A {
1077        match self.bits {
1078            0 => LPC_A::VALUE1,
1079            1 => LPC_A::VALUE2,
1080            2 => LPC_A::VALUE3,
1081            3 => LPC_A::VALUE4,
1082            4 => LPC_A::VALUE5,
1083            5 => LPC_A::VALUE6,
1084            6 => LPC_A::VALUE7,
1085            7 => LPC_A::VALUE8,
1086            _ => unreachable!(),
1087        }
1088    }
1089    #[doc = "Low pass filter disabled"]
1090    #[inline(always)]
1091    pub fn is_value1(&self) -> bool {
1092        *self == LPC_A::VALUE1
1093    }
1094    #[doc = "Low pass of 1 clock cycle"]
1095    #[inline(always)]
1096    pub fn is_value2(&self) -> bool {
1097        *self == LPC_A::VALUE2
1098    }
1099    #[doc = "Low pass of 2 clock cycles"]
1100    #[inline(always)]
1101    pub fn is_value3(&self) -> bool {
1102        *self == LPC_A::VALUE3
1103    }
1104    #[doc = "Low pass of 4 clock cycles"]
1105    #[inline(always)]
1106    pub fn is_value4(&self) -> bool {
1107        *self == LPC_A::VALUE4
1108    }
1109    #[doc = "Low pass of 8 clock cycles"]
1110    #[inline(always)]
1111    pub fn is_value5(&self) -> bool {
1112        *self == LPC_A::VALUE5
1113    }
1114    #[doc = "Low pass of 16 clock cycles"]
1115    #[inline(always)]
1116    pub fn is_value6(&self) -> bool {
1117        *self == LPC_A::VALUE6
1118    }
1119    #[doc = "Low pass of 32 clock cycles"]
1120    #[inline(always)]
1121    pub fn is_value7(&self) -> bool {
1122        *self == LPC_A::VALUE7
1123    }
1124    #[doc = "Low pass of 64 clock cycles"]
1125    #[inline(always)]
1126    pub fn is_value8(&self) -> bool {
1127        *self == LPC_A::VALUE8
1128    }
1129}
1130#[doc = "Field `LPC` writer - Low Pass Filters Configuration"]
1131pub type LPC_W<'a, REG> = crate::FieldWriter<'a, REG, 3, LPC_A, crate::Safe>;
1132impl<'a, REG> LPC_W<'a, REG>
1133where
1134    REG: crate::Writable + crate::RegisterSpec,
1135    REG::Ux: From<u8>,
1136{
1137    #[doc = "Low pass filter disabled"]
1138    #[inline(always)]
1139    pub fn value1(self) -> &'a mut crate::W<REG> {
1140        self.variant(LPC_A::VALUE1)
1141    }
1142    #[doc = "Low pass of 1 clock cycle"]
1143    #[inline(always)]
1144    pub fn value2(self) -> &'a mut crate::W<REG> {
1145        self.variant(LPC_A::VALUE2)
1146    }
1147    #[doc = "Low pass of 2 clock cycles"]
1148    #[inline(always)]
1149    pub fn value3(self) -> &'a mut crate::W<REG> {
1150        self.variant(LPC_A::VALUE3)
1151    }
1152    #[doc = "Low pass of 4 clock cycles"]
1153    #[inline(always)]
1154    pub fn value4(self) -> &'a mut crate::W<REG> {
1155        self.variant(LPC_A::VALUE4)
1156    }
1157    #[doc = "Low pass of 8 clock cycles"]
1158    #[inline(always)]
1159    pub fn value5(self) -> &'a mut crate::W<REG> {
1160        self.variant(LPC_A::VALUE5)
1161    }
1162    #[doc = "Low pass of 16 clock cycles"]
1163    #[inline(always)]
1164    pub fn value6(self) -> &'a mut crate::W<REG> {
1165        self.variant(LPC_A::VALUE6)
1166    }
1167    #[doc = "Low pass of 32 clock cycles"]
1168    #[inline(always)]
1169    pub fn value7(self) -> &'a mut crate::W<REG> {
1170        self.variant(LPC_A::VALUE7)
1171    }
1172    #[doc = "Low pass of 64 clock cycles"]
1173    #[inline(always)]
1174    pub fn value8(self) -> &'a mut crate::W<REG> {
1175        self.variant(LPC_A::VALUE8)
1176    }
1177}
1178impl R {
1179    #[doc = "Bits 0:1 - Function Selector"]
1180    #[inline(always)]
1181    pub fn fsel(&self) -> FSEL_R {
1182        FSEL_R::new((self.bits & 3) as u8)
1183    }
1184    #[doc = "Bit 2 - Position Decoder Mode selection"]
1185    #[inline(always)]
1186    pub fn qdcm(&self) -> QDCM_R {
1187        QDCM_R::new(((self.bits >> 2) & 1) != 0)
1188    }
1189    #[doc = "Bit 4 - Idle generation enable"]
1190    #[inline(always)]
1191    pub fn hidg(&self) -> HIDG_R {
1192        HIDG_R::new(((self.bits >> 4) & 1) != 0)
1193    }
1194    #[doc = "Bit 5 - Multi-Channel Pattern SW update enable"]
1195    #[inline(always)]
1196    pub fn mcue(&self) -> MCUE_R {
1197        MCUE_R::new(((self.bits >> 5) & 1) != 0)
1198    }
1199    #[doc = "Bits 8:9 - PhaseA/Hal input 1 selector"]
1200    #[inline(always)]
1201    pub fn insel0(&self) -> INSEL0_R {
1202        INSEL0_R::new(((self.bits >> 8) & 3) as u8)
1203    }
1204    #[doc = "Bits 10:11 - PhaseB/Hall input 2 selector"]
1205    #[inline(always)]
1206    pub fn insel1(&self) -> INSEL1_R {
1207        INSEL1_R::new(((self.bits >> 10) & 3) as u8)
1208    }
1209    #[doc = "Bits 12:13 - Index/Hall input 3 selector"]
1210    #[inline(always)]
1211    pub fn insel2(&self) -> INSEL2_R {
1212        INSEL2_R::new(((self.bits >> 12) & 3) as u8)
1213    }
1214    #[doc = "Bit 16 - Delay Pin selector"]
1215    #[inline(always)]
1216    pub fn dsel(&self) -> DSEL_R {
1217        DSEL_R::new(((self.bits >> 16) & 1) != 0)
1218    }
1219    #[doc = "Bit 17 - Edge selector for the sampling trigger"]
1220    #[inline(always)]
1221    pub fn spes(&self) -> SPES_R {
1222        SPES_R::new(((self.bits >> 17) & 1) != 0)
1223    }
1224    #[doc = "Bits 18:20 - Pattern update signal select"]
1225    #[inline(always)]
1226    pub fn msets(&self) -> MSETS_R {
1227        MSETS_R::new(((self.bits >> 18) & 7) as u8)
1228    }
1229    #[doc = "Bit 21 - Multi-Channel pattern update trigger edge"]
1230    #[inline(always)]
1231    pub fn mses(&self) -> MSES_R {
1232        MSES_R::new(((self.bits >> 21) & 1) != 0)
1233    }
1234    #[doc = "Bits 22:23 - PWM synchronization signal selector"]
1235    #[inline(always)]
1236    pub fn msyns(&self) -> MSYNS_R {
1237        MSYNS_R::new(((self.bits >> 22) & 3) as u8)
1238    }
1239    #[doc = "Bits 24:25 - Wrong Hall Event selection"]
1240    #[inline(always)]
1241    pub fn ewis(&self) -> EWIS_R {
1242        EWIS_R::new(((self.bits >> 24) & 3) as u8)
1243    }
1244    #[doc = "Bit 26 - External Wrong Hall Event enable"]
1245    #[inline(always)]
1246    pub fn ewie(&self) -> EWIE_R {
1247        EWIE_R::new(((self.bits >> 26) & 1) != 0)
1248    }
1249    #[doc = "Bit 27 - External Wrong Hall Event active level"]
1250    #[inline(always)]
1251    pub fn ewil(&self) -> EWIL_R {
1252        EWIL_R::new(((self.bits >> 27) & 1) != 0)
1253    }
1254    #[doc = "Bits 28:30 - Low Pass Filters Configuration"]
1255    #[inline(always)]
1256    pub fn lpc(&self) -> LPC_R {
1257        LPC_R::new(((self.bits >> 28) & 7) as u8)
1258    }
1259}
1260impl W {
1261    #[doc = "Bits 0:1 - Function Selector"]
1262    #[inline(always)]
1263    pub fn fsel(&mut self) -> FSEL_W<PCONF_SPEC> {
1264        FSEL_W::new(self, 0)
1265    }
1266    #[doc = "Bit 2 - Position Decoder Mode selection"]
1267    #[inline(always)]
1268    pub fn qdcm(&mut self) -> QDCM_W<PCONF_SPEC> {
1269        QDCM_W::new(self, 2)
1270    }
1271    #[doc = "Bit 4 - Idle generation enable"]
1272    #[inline(always)]
1273    pub fn hidg(&mut self) -> HIDG_W<PCONF_SPEC> {
1274        HIDG_W::new(self, 4)
1275    }
1276    #[doc = "Bit 5 - Multi-Channel Pattern SW update enable"]
1277    #[inline(always)]
1278    pub fn mcue(&mut self) -> MCUE_W<PCONF_SPEC> {
1279        MCUE_W::new(self, 5)
1280    }
1281    #[doc = "Bits 8:9 - PhaseA/Hal input 1 selector"]
1282    #[inline(always)]
1283    pub fn insel0(&mut self) -> INSEL0_W<PCONF_SPEC> {
1284        INSEL0_W::new(self, 8)
1285    }
1286    #[doc = "Bits 10:11 - PhaseB/Hall input 2 selector"]
1287    #[inline(always)]
1288    pub fn insel1(&mut self) -> INSEL1_W<PCONF_SPEC> {
1289        INSEL1_W::new(self, 10)
1290    }
1291    #[doc = "Bits 12:13 - Index/Hall input 3 selector"]
1292    #[inline(always)]
1293    pub fn insel2(&mut self) -> INSEL2_W<PCONF_SPEC> {
1294        INSEL2_W::new(self, 12)
1295    }
1296    #[doc = "Bit 16 - Delay Pin selector"]
1297    #[inline(always)]
1298    pub fn dsel(&mut self) -> DSEL_W<PCONF_SPEC> {
1299        DSEL_W::new(self, 16)
1300    }
1301    #[doc = "Bit 17 - Edge selector for the sampling trigger"]
1302    #[inline(always)]
1303    pub fn spes(&mut self) -> SPES_W<PCONF_SPEC> {
1304        SPES_W::new(self, 17)
1305    }
1306    #[doc = "Bits 18:20 - Pattern update signal select"]
1307    #[inline(always)]
1308    pub fn msets(&mut self) -> MSETS_W<PCONF_SPEC> {
1309        MSETS_W::new(self, 18)
1310    }
1311    #[doc = "Bit 21 - Multi-Channel pattern update trigger edge"]
1312    #[inline(always)]
1313    pub fn mses(&mut self) -> MSES_W<PCONF_SPEC> {
1314        MSES_W::new(self, 21)
1315    }
1316    #[doc = "Bits 22:23 - PWM synchronization signal selector"]
1317    #[inline(always)]
1318    pub fn msyns(&mut self) -> MSYNS_W<PCONF_SPEC> {
1319        MSYNS_W::new(self, 22)
1320    }
1321    #[doc = "Bits 24:25 - Wrong Hall Event selection"]
1322    #[inline(always)]
1323    pub fn ewis(&mut self) -> EWIS_W<PCONF_SPEC> {
1324        EWIS_W::new(self, 24)
1325    }
1326    #[doc = "Bit 26 - External Wrong Hall Event enable"]
1327    #[inline(always)]
1328    pub fn ewie(&mut self) -> EWIE_W<PCONF_SPEC> {
1329        EWIE_W::new(self, 26)
1330    }
1331    #[doc = "Bit 27 - External Wrong Hall Event active level"]
1332    #[inline(always)]
1333    pub fn ewil(&mut self) -> EWIL_W<PCONF_SPEC> {
1334        EWIL_W::new(self, 27)
1335    }
1336    #[doc = "Bits 28:30 - Low Pass Filters Configuration"]
1337    #[inline(always)]
1338    pub fn lpc(&mut self) -> LPC_W<PCONF_SPEC> {
1339        LPC_W::new(self, 28)
1340    }
1341}
1342#[doc = "POSIF configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`pconf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pconf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1343pub struct PCONF_SPEC;
1344impl crate::RegisterSpec for PCONF_SPEC {
1345    type Ux = u32;
1346}
1347#[doc = "`read()` method returns [`pconf::R`](R) reader structure"]
1348impl crate::Readable for PCONF_SPEC {}
1349#[doc = "`write(|w| ..)` method takes [`pconf::W`](W) writer structure"]
1350impl crate::Writable for PCONF_SPEC {
1351    type Safety = crate::Unsafe;
1352    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1353    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1354}
1355#[doc = "`reset()` method sets PCONF to value 0"]
1356impl crate::Resettable for PCONF_SPEC {
1357    const RESET_VALUE: u32 = 0;
1358}
xmc4700/posif0/pconf.rs

xmc4700/posif0/
pconf.rs
