xmc4700/vadc/
brsctrl.rs

1#[doc = "Register `BRSCTRL` reader"]
2pub type R = crate::R<BRSCTRL_SPEC>;
3#[doc = "Register `BRSCTRL` writer"]
4pub type W = crate::W<BRSCTRL_SPEC>;
5#[doc = "Source-specific Result Register\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum SRCRESREG_A {
9    #[doc = "0: Use GxCHCTRy.RESREG to select a group result register"]
10    VALUE1 = 0,
11    #[doc = "1: Store result in group result register GxRES1"]
12    VALUE2 = 1,
13    #[doc = "15: Store result in group result register GxRES15"]
14    VALUE3 = 15,
15}
16impl From<SRCRESREG_A> for u8 {
17    #[inline(always)]
18    fn from(variant: SRCRESREG_A) -> Self {
19        variant as _
20    }
21}
22impl crate::FieldSpec for SRCRESREG_A {
23    type Ux = u8;
24}
25impl crate::IsEnum for SRCRESREG_A {}
26#[doc = "Field `SRCRESREG` reader - Source-specific Result Register"]
27pub type SRCRESREG_R = crate::FieldReader<SRCRESREG_A>;
28impl SRCRESREG_R {
29    #[doc = "Get enumerated values variant"]
30    #[inline(always)]
31    pub const fn variant(&self) -> Option<SRCRESREG_A> {
32        match self.bits {
33            0 => Some(SRCRESREG_A::VALUE1),
34            1 => Some(SRCRESREG_A::VALUE2),
35            15 => Some(SRCRESREG_A::VALUE3),
36            _ => None,
37        }
38    }
39    #[doc = "Use GxCHCTRy.RESREG to select a group result register"]
40    #[inline(always)]
41    pub fn is_value1(&self) -> bool {
42        *self == SRCRESREG_A::VALUE1
43    }
44    #[doc = "Store result in group result register GxRES1"]
45    #[inline(always)]
46    pub fn is_value2(&self) -> bool {
47        *self == SRCRESREG_A::VALUE2
48    }
49    #[doc = "Store result in group result register GxRES15"]
50    #[inline(always)]
51    pub fn is_value3(&self) -> bool {
52        *self == SRCRESREG_A::VALUE3
53    }
54}
55#[doc = "Field `SRCRESREG` writer - Source-specific Result Register"]
56pub type SRCRESREG_W<'a, REG> = crate::FieldWriter<'a, REG, 4, SRCRESREG_A>;
57impl<'a, REG> SRCRESREG_W<'a, REG>
58where
59    REG: crate::Writable + crate::RegisterSpec,
60    REG::Ux: From<u8>,
61{
62    #[doc = "Use GxCHCTRy.RESREG to select a group result register"]
63    #[inline(always)]
64    pub fn value1(self) -> &'a mut crate::W<REG> {
65        self.variant(SRCRESREG_A::VALUE1)
66    }
67    #[doc = "Store result in group result register GxRES1"]
68    #[inline(always)]
69    pub fn value2(self) -> &'a mut crate::W<REG> {
70        self.variant(SRCRESREG_A::VALUE2)
71    }
72    #[doc = "Store result in group result register GxRES15"]
73    #[inline(always)]
74    pub fn value3(self) -> &'a mut crate::W<REG> {
75        self.variant(SRCRESREG_A::VALUE3)
76    }
77}
78#[doc = "Field `XTSEL` reader - External Trigger Input Selection"]
79pub type XTSEL_R = crate::FieldReader;
80#[doc = "Field `XTSEL` writer - External Trigger Input Selection"]
81pub type XTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
82#[doc = "Field `XTLVL` reader - External Trigger Level"]
83pub type XTLVL_R = crate::BitReader;
84#[doc = "Trigger Operating Mode\n\nValue on reset: 0"]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86#[repr(u8)]
87pub enum XTMODE_A {
88    #[doc = "0: No external trigger"]
89    VALUE1 = 0,
90    #[doc = "1: Trigger event upon a falling edge"]
91    VALUE2 = 1,
92    #[doc = "2: Trigger event upon a rising edge"]
93    VALUE3 = 2,
94    #[doc = "3: Trigger event upon any edge"]
95    VALUE4 = 3,
96}
97impl From<XTMODE_A> for u8 {
98    #[inline(always)]
99    fn from(variant: XTMODE_A) -> Self {
100        variant as _
101    }
102}
103impl crate::FieldSpec for XTMODE_A {
104    type Ux = u8;
105}
106impl crate::IsEnum for XTMODE_A {}
107#[doc = "Field `XTMODE` reader - Trigger Operating Mode"]
108pub type XTMODE_R = crate::FieldReader<XTMODE_A>;
109impl XTMODE_R {
110    #[doc = "Get enumerated values variant"]
111    #[inline(always)]
112    pub const fn variant(&self) -> XTMODE_A {
113        match self.bits {
114            0 => XTMODE_A::VALUE1,
115            1 => XTMODE_A::VALUE2,
116            2 => XTMODE_A::VALUE3,
117            3 => XTMODE_A::VALUE4,
118            _ => unreachable!(),
119        }
120    }
121    #[doc = "No external trigger"]
122    #[inline(always)]
123    pub fn is_value1(&self) -> bool {
124        *self == XTMODE_A::VALUE1
125    }
126    #[doc = "Trigger event upon a falling edge"]
127    #[inline(always)]
128    pub fn is_value2(&self) -> bool {
129        *self == XTMODE_A::VALUE2
130    }
131    #[doc = "Trigger event upon a rising edge"]
132    #[inline(always)]
133    pub fn is_value3(&self) -> bool {
134        *self == XTMODE_A::VALUE3
135    }
136    #[doc = "Trigger event upon any edge"]
137    #[inline(always)]
138    pub fn is_value4(&self) -> bool {
139        *self == XTMODE_A::VALUE4
140    }
141}
142#[doc = "Field `XTMODE` writer - Trigger Operating Mode"]
143pub type XTMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, XTMODE_A, crate::Safe>;
144impl<'a, REG> XTMODE_W<'a, REG>
145where
146    REG: crate::Writable + crate::RegisterSpec,
147    REG::Ux: From<u8>,
148{
149    #[doc = "No external trigger"]
150    #[inline(always)]
151    pub fn value1(self) -> &'a mut crate::W<REG> {
152        self.variant(XTMODE_A::VALUE1)
153    }
154    #[doc = "Trigger event upon a falling edge"]
155    #[inline(always)]
156    pub fn value2(self) -> &'a mut crate::W<REG> {
157        self.variant(XTMODE_A::VALUE2)
158    }
159    #[doc = "Trigger event upon a rising edge"]
160    #[inline(always)]
161    pub fn value3(self) -> &'a mut crate::W<REG> {
162        self.variant(XTMODE_A::VALUE3)
163    }
164    #[doc = "Trigger event upon any edge"]
165    #[inline(always)]
166    pub fn value4(self) -> &'a mut crate::W<REG> {
167        self.variant(XTMODE_A::VALUE4)
168    }
169}
170#[doc = "Write Control for Trigger Configuration\n\nValue on reset: 0"]
171#[derive(Clone, Copy, Debug, PartialEq, Eq)]
172pub enum XTWC_A {
173    #[doc = "0: No write access to trigger configuration"]
174    VALUE1 = 0,
175    #[doc = "1: Bitfields XTMODE and XTSEL can be written"]
176    VALUE2 = 1,
177}
178impl From<XTWC_A> for bool {
179    #[inline(always)]
180    fn from(variant: XTWC_A) -> Self {
181        variant as u8 != 0
182    }
183}
184#[doc = "Field `XTWC` writer - Write Control for Trigger Configuration"]
185pub type XTWC_W<'a, REG> = crate::BitWriter<'a, REG, XTWC_A>;
186impl<'a, REG> XTWC_W<'a, REG>
187where
188    REG: crate::Writable + crate::RegisterSpec,
189{
190    #[doc = "No write access to trigger configuration"]
191    #[inline(always)]
192    pub fn value1(self) -> &'a mut crate::W<REG> {
193        self.variant(XTWC_A::VALUE1)
194    }
195    #[doc = "Bitfields XTMODE and XTSEL can be written"]
196    #[inline(always)]
197    pub fn value2(self) -> &'a mut crate::W<REG> {
198        self.variant(XTWC_A::VALUE2)
199    }
200}
201#[doc = "Field `GTSEL` reader - Gate Input Selection"]
202pub type GTSEL_R = crate::FieldReader;
203#[doc = "Field `GTSEL` writer - Gate Input Selection"]
204pub type GTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
205#[doc = "Field `GTLVL` reader - Gate Input Level"]
206pub type GTLVL_R = crate::BitReader;
207#[doc = "Write Control for Gate Configuration\n\nValue on reset: 0"]
208#[derive(Clone, Copy, Debug, PartialEq, Eq)]
209pub enum GTWC_A {
210    #[doc = "0: No write access to gate configuration"]
211    VALUE1 = 0,
212    #[doc = "1: Bitfield GTSEL can be written"]
213    VALUE2 = 1,
214}
215impl From<GTWC_A> for bool {
216    #[inline(always)]
217    fn from(variant: GTWC_A) -> Self {
218        variant as u8 != 0
219    }
220}
221#[doc = "Field `GTWC` writer - Write Control for Gate Configuration"]
222pub type GTWC_W<'a, REG> = crate::BitWriter<'a, REG, GTWC_A>;
223impl<'a, REG> GTWC_W<'a, REG>
224where
225    REG: crate::Writable + crate::RegisterSpec,
226{
227    #[doc = "No write access to gate configuration"]
228    #[inline(always)]
229    pub fn value1(self) -> &'a mut crate::W<REG> {
230        self.variant(GTWC_A::VALUE1)
231    }
232    #[doc = "Bitfield GTSEL can be written"]
233    #[inline(always)]
234    pub fn value2(self) -> &'a mut crate::W<REG> {
235        self.variant(GTWC_A::VALUE2)
236    }
237}
238impl R {
239    #[doc = "Bits 0:3 - Source-specific Result Register"]
240    #[inline(always)]
241    pub fn srcresreg(&self) -> SRCRESREG_R {
242        SRCRESREG_R::new((self.bits & 0x0f) as u8)
243    }
244    #[doc = "Bits 8:11 - External Trigger Input Selection"]
245    #[inline(always)]
246    pub fn xtsel(&self) -> XTSEL_R {
247        XTSEL_R::new(((self.bits >> 8) & 0x0f) as u8)
248    }
249    #[doc = "Bit 12 - External Trigger Level"]
250    #[inline(always)]
251    pub fn xtlvl(&self) -> XTLVL_R {
252        XTLVL_R::new(((self.bits >> 12) & 1) != 0)
253    }
254    #[doc = "Bits 13:14 - Trigger Operating Mode"]
255    #[inline(always)]
256    pub fn xtmode(&self) -> XTMODE_R {
257        XTMODE_R::new(((self.bits >> 13) & 3) as u8)
258    }
259    #[doc = "Bits 16:19 - Gate Input Selection"]
260    #[inline(always)]
261    pub fn gtsel(&self) -> GTSEL_R {
262        GTSEL_R::new(((self.bits >> 16) & 0x0f) as u8)
263    }
264    #[doc = "Bit 20 - Gate Input Level"]
265    #[inline(always)]
266    pub fn gtlvl(&self) -> GTLVL_R {
267        GTLVL_R::new(((self.bits >> 20) & 1) != 0)
268    }
269}
270impl W {
271    #[doc = "Bits 0:3 - Source-specific Result Register"]
272    #[inline(always)]
273    pub fn srcresreg(&mut self) -> SRCRESREG_W<BRSCTRL_SPEC> {
274        SRCRESREG_W::new(self, 0)
275    }
276    #[doc = "Bits 8:11 - External Trigger Input Selection"]
277    #[inline(always)]
278    pub fn xtsel(&mut self) -> XTSEL_W<BRSCTRL_SPEC> {
279        XTSEL_W::new(self, 8)
280    }
281    #[doc = "Bits 13:14 - Trigger Operating Mode"]
282    #[inline(always)]
283    pub fn xtmode(&mut self) -> XTMODE_W<BRSCTRL_SPEC> {
284        XTMODE_W::new(self, 13)
285    }
286    #[doc = "Bit 15 - Write Control for Trigger Configuration"]
287    #[inline(always)]
288    pub fn xtwc(&mut self) -> XTWC_W<BRSCTRL_SPEC> {
289        XTWC_W::new(self, 15)
290    }
291    #[doc = "Bits 16:19 - Gate Input Selection"]
292    #[inline(always)]
293    pub fn gtsel(&mut self) -> GTSEL_W<BRSCTRL_SPEC> {
294        GTSEL_W::new(self, 16)
295    }
296    #[doc = "Bit 23 - Write Control for Gate Configuration"]
297    #[inline(always)]
298    pub fn gtwc(&mut self) -> GTWC_W<BRSCTRL_SPEC> {
299        GTWC_W::new(self, 23)
300    }
301}
302#[doc = "Background Request Source Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`brsctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`brsctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
303pub struct BRSCTRL_SPEC;
304impl crate::RegisterSpec for BRSCTRL_SPEC {
305    type Ux = u32;
306}
307#[doc = "`read()` method returns [`brsctrl::R`](R) reader structure"]
308impl crate::Readable for BRSCTRL_SPEC {}
309#[doc = "`write(|w| ..)` method takes [`brsctrl::W`](W) writer structure"]
310impl crate::Writable for BRSCTRL_SPEC {
311    type Safety = crate::Unsafe;
312    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
313    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
314}
315#[doc = "`reset()` method sets BRSCTRL to value 0"]
316impl crate::Resettable for BRSCTRL_SPEC {
317    const RESET_VALUE: u32 = 0;
318}
xmc4700/vadc/brsctrl.rs

xmc4700/vadc/
brsctrl.rs
