xmc4500/usic0_ch0/
sctr.rs

1#[doc = "Register `SCTR` reader"]
2pub type R = crate::R<SCTR_SPEC>;
3#[doc = "Register `SCTR` writer"]
4pub type W = crate::W<SCTR_SPEC>;
5#[doc = "Shift Direction\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum SDIR_A {
8    #[doc = "0: Shift LSB first. The first data bit of a data word is located at bit position 0."]
9    VALUE1 = 0,
10    #[doc = "1: Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTR.WLE."]
11    VALUE2 = 1,
12}
13impl From<SDIR_A> for bool {
14    #[inline(always)]
15    fn from(variant: SDIR_A) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `SDIR` reader - Shift Direction"]
20pub type SDIR_R = crate::BitReader<SDIR_A>;
21impl SDIR_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> SDIR_A {
25        match self.bits {
26            false => SDIR_A::VALUE1,
27            true => SDIR_A::VALUE2,
28        }
29    }
30    #[doc = "Shift LSB first. The first data bit of a data word is located at bit position 0."]
31    #[inline(always)]
32    pub fn is_value1(&self) -> bool {
33        *self == SDIR_A::VALUE1
34    }
35    #[doc = "Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTR.WLE."]
36    #[inline(always)]
37    pub fn is_value2(&self) -> bool {
38        *self == SDIR_A::VALUE2
39    }
40}
41#[doc = "Field `SDIR` writer - Shift Direction"]
42pub type SDIR_W<'a, REG> = crate::BitWriter<'a, REG, SDIR_A>;
43impl<'a, REG> SDIR_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Shift LSB first. The first data bit of a data word is located at bit position 0."]
48    #[inline(always)]
49    pub fn value1(self) -> &'a mut crate::W<REG> {
50        self.variant(SDIR_A::VALUE1)
51    }
52    #[doc = "Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTR.WLE."]
53    #[inline(always)]
54    pub fn value2(self) -> &'a mut crate::W<REG> {
55        self.variant(SDIR_A::VALUE2)
56    }
57}
58#[doc = "Passive Data Level\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum PDL_A {
61    #[doc = "0: The passive data level is 0."]
62    VALUE1 = 0,
63    #[doc = "1: The passive data level is 1."]
64    VALUE2 = 1,
65}
66impl From<PDL_A> for bool {
67    #[inline(always)]
68    fn from(variant: PDL_A) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `PDL` reader - Passive Data Level"]
73pub type PDL_R = crate::BitReader<PDL_A>;
74impl PDL_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> PDL_A {
78        match self.bits {
79            false => PDL_A::VALUE1,
80            true => PDL_A::VALUE2,
81        }
82    }
83    #[doc = "The passive data level is 0."]
84    #[inline(always)]
85    pub fn is_value1(&self) -> bool {
86        *self == PDL_A::VALUE1
87    }
88    #[doc = "The passive data level is 1."]
89    #[inline(always)]
90    pub fn is_value2(&self) -> bool {
91        *self == PDL_A::VALUE2
92    }
93}
94#[doc = "Field `PDL` writer - Passive Data Level"]
95pub type PDL_W<'a, REG> = crate::BitWriter<'a, REG, PDL_A>;
96impl<'a, REG> PDL_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "The passive data level is 0."]
101    #[inline(always)]
102    pub fn value1(self) -> &'a mut crate::W<REG> {
103        self.variant(PDL_A::VALUE1)
104    }
105    #[doc = "The passive data level is 1."]
106    #[inline(always)]
107    pub fn value2(self) -> &'a mut crate::W<REG> {
108        self.variant(PDL_A::VALUE2)
109    }
110}
111#[doc = "Data Shift Mode\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113#[repr(u8)]
114pub enum DSM_A {
115    #[doc = "0: Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0."]
116    VALUE1 = 0,
117    #[doc = "2: Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT\\[1:0\\]
118respectively."]
119    VALUE3 = 2,
120    #[doc = "3: Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX\\[5:3\\]) and DOUT\\[3:0\\]
121respectively."]
122    VALUE4 = 3,
123}
124impl From<DSM_A> for u8 {
125    #[inline(always)]
126    fn from(variant: DSM_A) -> Self {
127        variant as _
128    }
129}
130impl crate::FieldSpec for DSM_A {
131    type Ux = u8;
132}
133impl crate::IsEnum for DSM_A {}
134#[doc = "Field `DSM` reader - Data Shift Mode"]
135pub type DSM_R = crate::FieldReader<DSM_A>;
136impl DSM_R {
137    #[doc = "Get enumerated values variant"]
138    #[inline(always)]
139    pub const fn variant(&self) -> Option<DSM_A> {
140        match self.bits {
141            0 => Some(DSM_A::VALUE1),
142            2 => Some(DSM_A::VALUE3),
143            3 => Some(DSM_A::VALUE4),
144            _ => None,
145        }
146    }
147    #[doc = "Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0."]
148    #[inline(always)]
149    pub fn is_value1(&self) -> bool {
150        *self == DSM_A::VALUE1
151    }
152    #[doc = "Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT\\[1:0\\]
153respectively."]
154    #[inline(always)]
155    pub fn is_value3(&self) -> bool {
156        *self == DSM_A::VALUE3
157    }
158    #[doc = "Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX\\[5:3\\]) and DOUT\\[3:0\\]
159respectively."]
160    #[inline(always)]
161    pub fn is_value4(&self) -> bool {
162        *self == DSM_A::VALUE4
163    }
164}
165#[doc = "Field `DSM` writer - Data Shift Mode"]
166pub type DSM_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DSM_A>;
167impl<'a, REG> DSM_W<'a, REG>
168where
169    REG: crate::Writable + crate::RegisterSpec,
170    REG::Ux: From<u8>,
171{
172    #[doc = "Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0."]
173    #[inline(always)]
174    pub fn value1(self) -> &'a mut crate::W<REG> {
175        self.variant(DSM_A::VALUE1)
176    }
177    #[doc = "Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT\\[1:0\\]
178respectively."]
179    #[inline(always)]
180    pub fn value3(self) -> &'a mut crate::W<REG> {
181        self.variant(DSM_A::VALUE3)
182    }
183    #[doc = "Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX\\[5:3\\]) and DOUT\\[3:0\\]
184respectively."]
185    #[inline(always)]
186    pub fn value4(self) -> &'a mut crate::W<REG> {
187        self.variant(DSM_A::VALUE4)
188    }
189}
190#[doc = "Port Control Direction\n\nValue on reset: 0"]
191#[derive(Clone, Copy, Debug, PartialEq, Eq)]
192pub enum HPCDIR_A {
193    #[doc = "0: The pin(s) with hardware pin control enabled are selected to be in input mode."]
194    VALUE1 = 0,
195    #[doc = "1: The pin(s) with hardware pin control enabled are selected to be in output mode."]
196    VALUE2 = 1,
197}
198impl From<HPCDIR_A> for bool {
199    #[inline(always)]
200    fn from(variant: HPCDIR_A) -> Self {
201        variant as u8 != 0
202    }
203}
204#[doc = "Field `HPCDIR` reader - Port Control Direction"]
205pub type HPCDIR_R = crate::BitReader<HPCDIR_A>;
206impl HPCDIR_R {
207    #[doc = "Get enumerated values variant"]
208    #[inline(always)]
209    pub const fn variant(&self) -> HPCDIR_A {
210        match self.bits {
211            false => HPCDIR_A::VALUE1,
212            true => HPCDIR_A::VALUE2,
213        }
214    }
215    #[doc = "The pin(s) with hardware pin control enabled are selected to be in input mode."]
216    #[inline(always)]
217    pub fn is_value1(&self) -> bool {
218        *self == HPCDIR_A::VALUE1
219    }
220    #[doc = "The pin(s) with hardware pin control enabled are selected to be in output mode."]
221    #[inline(always)]
222    pub fn is_value2(&self) -> bool {
223        *self == HPCDIR_A::VALUE2
224    }
225}
226#[doc = "Field `HPCDIR` writer - Port Control Direction"]
227pub type HPCDIR_W<'a, REG> = crate::BitWriter<'a, REG, HPCDIR_A>;
228impl<'a, REG> HPCDIR_W<'a, REG>
229where
230    REG: crate::Writable + crate::RegisterSpec,
231{
232    #[doc = "The pin(s) with hardware pin control enabled are selected to be in input mode."]
233    #[inline(always)]
234    pub fn value1(self) -> &'a mut crate::W<REG> {
235        self.variant(HPCDIR_A::VALUE1)
236    }
237    #[doc = "The pin(s) with hardware pin control enabled are selected to be in output mode."]
238    #[inline(always)]
239    pub fn value2(self) -> &'a mut crate::W<REG> {
240        self.variant(HPCDIR_A::VALUE2)
241    }
242}
243#[doc = "Data Output Configuration\n\nValue on reset: 0"]
244#[derive(Clone, Copy, Debug, PartialEq, Eq)]
245#[repr(u8)]
246pub enum DOCFG_A {
247    #[doc = "0: DOUTx = shift data value"]
248    VALUE1 = 0,
249    #[doc = "1: DOUTx = inverted shift data value"]
250    VALUE2 = 1,
251}
252impl From<DOCFG_A> for u8 {
253    #[inline(always)]
254    fn from(variant: DOCFG_A) -> Self {
255        variant as _
256    }
257}
258impl crate::FieldSpec for DOCFG_A {
259    type Ux = u8;
260}
261impl crate::IsEnum for DOCFG_A {}
262#[doc = "Field `DOCFG` reader - Data Output Configuration"]
263pub type DOCFG_R = crate::FieldReader<DOCFG_A>;
264impl DOCFG_R {
265    #[doc = "Get enumerated values variant"]
266    #[inline(always)]
267    pub const fn variant(&self) -> Option<DOCFG_A> {
268        match self.bits {
269            0 => Some(DOCFG_A::VALUE1),
270            1 => Some(DOCFG_A::VALUE2),
271            _ => None,
272        }
273    }
274    #[doc = "DOUTx = shift data value"]
275    #[inline(always)]
276    pub fn is_value1(&self) -> bool {
277        *self == DOCFG_A::VALUE1
278    }
279    #[doc = "DOUTx = inverted shift data value"]
280    #[inline(always)]
281    pub fn is_value2(&self) -> bool {
282        *self == DOCFG_A::VALUE2
283    }
284}
285#[doc = "Field `DOCFG` writer - Data Output Configuration"]
286pub type DOCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DOCFG_A>;
287impl<'a, REG> DOCFG_W<'a, REG>
288where
289    REG: crate::Writable + crate::RegisterSpec,
290    REG::Ux: From<u8>,
291{
292    #[doc = "DOUTx = shift data value"]
293    #[inline(always)]
294    pub fn value1(self) -> &'a mut crate::W<REG> {
295        self.variant(DOCFG_A::VALUE1)
296    }
297    #[doc = "DOUTx = inverted shift data value"]
298    #[inline(always)]
299    pub fn value2(self) -> &'a mut crate::W<REG> {
300        self.variant(DOCFG_A::VALUE2)
301    }
302}
303#[doc = "Transmission Mode\n\nValue on reset: 0"]
304#[derive(Clone, Copy, Debug, PartialEq, Eq)]
305#[repr(u8)]
306pub enum TRM_A {
307    #[doc = "0: The shift control signal is considered as inactive and data frame transfers are not possible."]
308    VALUE1 = 0,
309    #[doc = "1: The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers."]
310    VALUE2 = 1,
311    #[doc = "2: The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal."]
312    VALUE3 = 2,
313    #[doc = "3: The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal."]
314    VALUE4 = 3,
315}
316impl From<TRM_A> for u8 {
317    #[inline(always)]
318    fn from(variant: TRM_A) -> Self {
319        variant as _
320    }
321}
322impl crate::FieldSpec for TRM_A {
323    type Ux = u8;
324}
325impl crate::IsEnum for TRM_A {}
326#[doc = "Field `TRM` reader - Transmission Mode"]
327pub type TRM_R = crate::FieldReader<TRM_A>;
328impl TRM_R {
329    #[doc = "Get enumerated values variant"]
330    #[inline(always)]
331    pub const fn variant(&self) -> TRM_A {
332        match self.bits {
333            0 => TRM_A::VALUE1,
334            1 => TRM_A::VALUE2,
335            2 => TRM_A::VALUE3,
336            3 => TRM_A::VALUE4,
337            _ => unreachable!(),
338        }
339    }
340    #[doc = "The shift control signal is considered as inactive and data frame transfers are not possible."]
341    #[inline(always)]
342    pub fn is_value1(&self) -> bool {
343        *self == TRM_A::VALUE1
344    }
345    #[doc = "The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers."]
346    #[inline(always)]
347    pub fn is_value2(&self) -> bool {
348        *self == TRM_A::VALUE2
349    }
350    #[doc = "The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal."]
351    #[inline(always)]
352    pub fn is_value3(&self) -> bool {
353        *self == TRM_A::VALUE3
354    }
355    #[doc = "The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal."]
356    #[inline(always)]
357    pub fn is_value4(&self) -> bool {
358        *self == TRM_A::VALUE4
359    }
360}
361#[doc = "Field `TRM` writer - Transmission Mode"]
362pub type TRM_W<'a, REG> = crate::FieldWriter<'a, REG, 2, TRM_A, crate::Safe>;
363impl<'a, REG> TRM_W<'a, REG>
364where
365    REG: crate::Writable + crate::RegisterSpec,
366    REG::Ux: From<u8>,
367{
368    #[doc = "The shift control signal is considered as inactive and data frame transfers are not possible."]
369    #[inline(always)]
370    pub fn value1(self) -> &'a mut crate::W<REG> {
371        self.variant(TRM_A::VALUE1)
372    }
373    #[doc = "The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers."]
374    #[inline(always)]
375    pub fn value2(self) -> &'a mut crate::W<REG> {
376        self.variant(TRM_A::VALUE2)
377    }
378    #[doc = "The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal."]
379    #[inline(always)]
380    pub fn value3(self) -> &'a mut crate::W<REG> {
381        self.variant(TRM_A::VALUE3)
382    }
383    #[doc = "The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal."]
384    #[inline(always)]
385    pub fn value4(self) -> &'a mut crate::W<REG> {
386        self.variant(TRM_A::VALUE4)
387    }
388}
389#[doc = "Field `FLE` reader - Frame Length"]
390pub type FLE_R = crate::FieldReader;
391#[doc = "Field `FLE` writer - Frame Length"]
392pub type FLE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
393#[doc = "Word Length\n\nValue on reset: 0"]
394#[derive(Clone, Copy, Debug, PartialEq, Eq)]
395#[repr(u8)]
396pub enum WLE_A {
397    #[doc = "0: The data word contains 1 data bit located at bit position 0."]
398    VALUE1 = 0,
399    #[doc = "1: The data word contains 2 data bits located at bit positions \\[1:0\\]."]
400    VALUE2 = 1,
401    #[doc = "14: The data word contains 15 data bits located at bit positions \\[14:0\\]."]
402    VALUE3 = 14,
403    #[doc = "15: The data word contains 16 data bits located at bit positions \\[15:0\\]."]
404    VALUE4 = 15,
405}
406impl From<WLE_A> for u8 {
407    #[inline(always)]
408    fn from(variant: WLE_A) -> Self {
409        variant as _
410    }
411}
412impl crate::FieldSpec for WLE_A {
413    type Ux = u8;
414}
415impl crate::IsEnum for WLE_A {}
416#[doc = "Field `WLE` reader - Word Length"]
417pub type WLE_R = crate::FieldReader<WLE_A>;
418impl WLE_R {
419    #[doc = "Get enumerated values variant"]
420    #[inline(always)]
421    pub const fn variant(&self) -> Option<WLE_A> {
422        match self.bits {
423            0 => Some(WLE_A::VALUE1),
424            1 => Some(WLE_A::VALUE2),
425            14 => Some(WLE_A::VALUE3),
426            15 => Some(WLE_A::VALUE4),
427            _ => None,
428        }
429    }
430    #[doc = "The data word contains 1 data bit located at bit position 0."]
431    #[inline(always)]
432    pub fn is_value1(&self) -> bool {
433        *self == WLE_A::VALUE1
434    }
435    #[doc = "The data word contains 2 data bits located at bit positions \\[1:0\\]."]
436    #[inline(always)]
437    pub fn is_value2(&self) -> bool {
438        *self == WLE_A::VALUE2
439    }
440    #[doc = "The data word contains 15 data bits located at bit positions \\[14:0\\]."]
441    #[inline(always)]
442    pub fn is_value3(&self) -> bool {
443        *self == WLE_A::VALUE3
444    }
445    #[doc = "The data word contains 16 data bits located at bit positions \\[15:0\\]."]
446    #[inline(always)]
447    pub fn is_value4(&self) -> bool {
448        *self == WLE_A::VALUE4
449    }
450}
451#[doc = "Field `WLE` writer - Word Length"]
452pub type WLE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, WLE_A>;
453impl<'a, REG> WLE_W<'a, REG>
454where
455    REG: crate::Writable + crate::RegisterSpec,
456    REG::Ux: From<u8>,
457{
458    #[doc = "The data word contains 1 data bit located at bit position 0."]
459    #[inline(always)]
460    pub fn value1(self) -> &'a mut crate::W<REG> {
461        self.variant(WLE_A::VALUE1)
462    }
463    #[doc = "The data word contains 2 data bits located at bit positions \\[1:0\\]."]
464    #[inline(always)]
465    pub fn value2(self) -> &'a mut crate::W<REG> {
466        self.variant(WLE_A::VALUE2)
467    }
468    #[doc = "The data word contains 15 data bits located at bit positions \\[14:0\\]."]
469    #[inline(always)]
470    pub fn value3(self) -> &'a mut crate::W<REG> {
471        self.variant(WLE_A::VALUE3)
472    }
473    #[doc = "The data word contains 16 data bits located at bit positions \\[15:0\\]."]
474    #[inline(always)]
475    pub fn value4(self) -> &'a mut crate::W<REG> {
476        self.variant(WLE_A::VALUE4)
477    }
478}
479impl R {
480    #[doc = "Bit 0 - Shift Direction"]
481    #[inline(always)]
482    pub fn sdir(&self) -> SDIR_R {
483        SDIR_R::new((self.bits & 1) != 0)
484    }
485    #[doc = "Bit 1 - Passive Data Level"]
486    #[inline(always)]
487    pub fn pdl(&self) -> PDL_R {
488        PDL_R::new(((self.bits >> 1) & 1) != 0)
489    }
490    #[doc = "Bits 2:3 - Data Shift Mode"]
491    #[inline(always)]
492    pub fn dsm(&self) -> DSM_R {
493        DSM_R::new(((self.bits >> 2) & 3) as u8)
494    }
495    #[doc = "Bit 4 - Port Control Direction"]
496    #[inline(always)]
497    pub fn hpcdir(&self) -> HPCDIR_R {
498        HPCDIR_R::new(((self.bits >> 4) & 1) != 0)
499    }
500    #[doc = "Bits 6:7 - Data Output Configuration"]
501    #[inline(always)]
502    pub fn docfg(&self) -> DOCFG_R {
503        DOCFG_R::new(((self.bits >> 6) & 3) as u8)
504    }
505    #[doc = "Bits 8:9 - Transmission Mode"]
506    #[inline(always)]
507    pub fn trm(&self) -> TRM_R {
508        TRM_R::new(((self.bits >> 8) & 3) as u8)
509    }
510    #[doc = "Bits 16:21 - Frame Length"]
511    #[inline(always)]
512    pub fn fle(&self) -> FLE_R {
513        FLE_R::new(((self.bits >> 16) & 0x3f) as u8)
514    }
515    #[doc = "Bits 24:27 - Word Length"]
516    #[inline(always)]
517    pub fn wle(&self) -> WLE_R {
518        WLE_R::new(((self.bits >> 24) & 0x0f) as u8)
519    }
520}
521impl W {
522    #[doc = "Bit 0 - Shift Direction"]
523    #[inline(always)]
524    pub fn sdir(&mut self) -> SDIR_W<SCTR_SPEC> {
525        SDIR_W::new(self, 0)
526    }
527    #[doc = "Bit 1 - Passive Data Level"]
528    #[inline(always)]
529    pub fn pdl(&mut self) -> PDL_W<SCTR_SPEC> {
530        PDL_W::new(self, 1)
531    }
532    #[doc = "Bits 2:3 - Data Shift Mode"]
533    #[inline(always)]
534    pub fn dsm(&mut self) -> DSM_W<SCTR_SPEC> {
535        DSM_W::new(self, 2)
536    }
537    #[doc = "Bit 4 - Port Control Direction"]
538    #[inline(always)]
539    pub fn hpcdir(&mut self) -> HPCDIR_W<SCTR_SPEC> {
540        HPCDIR_W::new(self, 4)
541    }
542    #[doc = "Bits 6:7 - Data Output Configuration"]
543    #[inline(always)]
544    pub fn docfg(&mut self) -> DOCFG_W<SCTR_SPEC> {
545        DOCFG_W::new(self, 6)
546    }
547    #[doc = "Bits 8:9 - Transmission Mode"]
548    #[inline(always)]
549    pub fn trm(&mut self) -> TRM_W<SCTR_SPEC> {
550        TRM_W::new(self, 8)
551    }
552    #[doc = "Bits 16:21 - Frame Length"]
553    #[inline(always)]
554    pub fn fle(&mut self) -> FLE_W<SCTR_SPEC> {
555        FLE_W::new(self, 16)
556    }
557    #[doc = "Bits 24:27 - Word Length"]
558    #[inline(always)]
559    pub fn wle(&mut self) -> WLE_W<SCTR_SPEC> {
560        WLE_W::new(self, 24)
561    }
562}
563#[doc = "Shift Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
564pub struct SCTR_SPEC;
565impl crate::RegisterSpec for SCTR_SPEC {
566    type Ux = u32;
567}
568#[doc = "`read()` method returns [`sctr::R`](R) reader structure"]
569impl crate::Readable for SCTR_SPEC {}
570#[doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"]
571impl crate::Writable for SCTR_SPEC {
572    type Safety = crate::Unsafe;
573    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
574    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
575}
576#[doc = "`reset()` method sets SCTR to value 0"]
577impl crate::Resettable for SCTR_SPEC {
578    const RESET_VALUE: u32 = 0;
579}
xmc4500/usic0_ch0/sctr.rs

xmc4500/usic0_ch0/
sctr.rs
