1#[doc = "Register `CLC` reader"]
2pub type R = crate::R<CLC_SPEC>;
3#[doc = "Register `CLC` writer"]
4pub type W = crate::W<CLC_SPEC>;
5#[doc = "Field `DISR` reader - Module Disable Request Bit"]
6pub type DISR_R = crate::BitReader;
7#[doc = "Field `DISR` writer - Module Disable Request Bit"]
8pub type DISR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DISS` reader - Module Disable Status Bit"]
10pub type DISS_R = crate::BitReader;
11impl R {
12 #[doc = "Bit 0 - Module Disable Request Bit"]
13 #[inline(always)]
14 pub fn disr(&self) -> DISR_R {
15 DISR_R::new((self.bits & 1) != 0)
16 }
17 #[doc = "Bit 1 - Module Disable Status Bit"]
18 #[inline(always)]
19 pub fn diss(&self) -> DISS_R {
20 DISS_R::new(((self.bits >> 1) & 1) != 0)
21 }
22}
23impl W {
24 #[doc = "Bit 0 - Module Disable Request Bit"]
25 #[inline(always)]
26 pub fn disr(&mut self) -> DISR_W<CLC_SPEC> {
27 DISR_W::new(self, 0)
28 }
29}
30#[doc = "Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
31pub struct CLC_SPEC;
32impl crate::RegisterSpec for CLC_SPEC {
33 type Ux = u32;
34}
35#[doc = "`read()` method returns [`clc::R`](R) reader structure"]
36impl crate::Readable for CLC_SPEC {}
37#[doc = "`write(|w| ..)` method takes [`clc::W`](W) writer structure"]
38impl crate::Writable for CLC_SPEC {
39 type Safety = crate::Unsafe;
40 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
41 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
42}
43#[doc = "`reset()` method sets CLC to value 0x03"]
44impl crate::Resettable for CLC_SPEC {
45 const RESET_VALUE: u32 = 0x03;
46}