xmc4500/vadc_g0/
asctrl.rs

1#[doc = "Register `ASCTRL` reader"]
2pub type R = crate::R<ASCTRL_SPEC>;
3#[doc = "Register `ASCTRL` writer"]
4pub type W = crate::W<ASCTRL_SPEC>;
5#[doc = "Field `XTSEL` reader - External Trigger Input Selection"]
6pub type XTSEL_R = crate::FieldReader;
7#[doc = "Field `XTSEL` writer - External Trigger Input Selection"]
8pub type XTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `XTLVL` reader - External Trigger Level"]
10pub type XTLVL_R = crate::BitReader;
11#[doc = "Trigger Operating Mode\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum XTMODE_A {
15    #[doc = "0: No external trigger"]
16    VALUE1 = 0,
17    #[doc = "1: Trigger event upon a falling edge"]
18    VALUE2 = 1,
19    #[doc = "2: Trigger event upon a rising edge"]
20    VALUE3 = 2,
21    #[doc = "3: Trigger event upon any edge"]
22    VALUE4 = 3,
23}
24impl From<XTMODE_A> for u8 {
25    #[inline(always)]
26    fn from(variant: XTMODE_A) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for XTMODE_A {
31    type Ux = u8;
32}
33impl crate::IsEnum for XTMODE_A {}
34#[doc = "Field `XTMODE` reader - Trigger Operating Mode"]
35pub type XTMODE_R = crate::FieldReader<XTMODE_A>;
36impl XTMODE_R {
37    #[doc = "Get enumerated values variant"]
38    #[inline(always)]
39    pub const fn variant(&self) -> XTMODE_A {
40        match self.bits {
41            0 => XTMODE_A::VALUE1,
42            1 => XTMODE_A::VALUE2,
43            2 => XTMODE_A::VALUE3,
44            3 => XTMODE_A::VALUE4,
45            _ => unreachable!(),
46        }
47    }
48    #[doc = "No external trigger"]
49    #[inline(always)]
50    pub fn is_value1(&self) -> bool {
51        *self == XTMODE_A::VALUE1
52    }
53    #[doc = "Trigger event upon a falling edge"]
54    #[inline(always)]
55    pub fn is_value2(&self) -> bool {
56        *self == XTMODE_A::VALUE2
57    }
58    #[doc = "Trigger event upon a rising edge"]
59    #[inline(always)]
60    pub fn is_value3(&self) -> bool {
61        *self == XTMODE_A::VALUE3
62    }
63    #[doc = "Trigger event upon any edge"]
64    #[inline(always)]
65    pub fn is_value4(&self) -> bool {
66        *self == XTMODE_A::VALUE4
67    }
68}
69#[doc = "Field `XTMODE` writer - Trigger Operating Mode"]
70pub type XTMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, XTMODE_A, crate::Safe>;
71impl<'a, REG> XTMODE_W<'a, REG>
72where
73    REG: crate::Writable + crate::RegisterSpec,
74    REG::Ux: From<u8>,
75{
76    #[doc = "No external trigger"]
77    #[inline(always)]
78    pub fn value1(self) -> &'a mut crate::W<REG> {
79        self.variant(XTMODE_A::VALUE1)
80    }
81    #[doc = "Trigger event upon a falling edge"]
82    #[inline(always)]
83    pub fn value2(self) -> &'a mut crate::W<REG> {
84        self.variant(XTMODE_A::VALUE2)
85    }
86    #[doc = "Trigger event upon a rising edge"]
87    #[inline(always)]
88    pub fn value3(self) -> &'a mut crate::W<REG> {
89        self.variant(XTMODE_A::VALUE3)
90    }
91    #[doc = "Trigger event upon any edge"]
92    #[inline(always)]
93    pub fn value4(self) -> &'a mut crate::W<REG> {
94        self.variant(XTMODE_A::VALUE4)
95    }
96}
97#[doc = "Write Control for Trigger Configuration\n\nValue on reset: 0"]
98#[derive(Clone, Copy, Debug, PartialEq, Eq)]
99pub enum XTWC_A {
100    #[doc = "0: No write access to trigger configuration"]
101    VALUE1 = 0,
102    #[doc = "1: Bitfields XTMODE and XTSEL can be written"]
103    VALUE2 = 1,
104}
105impl From<XTWC_A> for bool {
106    #[inline(always)]
107    fn from(variant: XTWC_A) -> Self {
108        variant as u8 != 0
109    }
110}
111#[doc = "Field `XTWC` writer - Write Control for Trigger Configuration"]
112pub type XTWC_W<'a, REG> = crate::BitWriter<'a, REG, XTWC_A>;
113impl<'a, REG> XTWC_W<'a, REG>
114where
115    REG: crate::Writable + crate::RegisterSpec,
116{
117    #[doc = "No write access to trigger configuration"]
118    #[inline(always)]
119    pub fn value1(self) -> &'a mut crate::W<REG> {
120        self.variant(XTWC_A::VALUE1)
121    }
122    #[doc = "Bitfields XTMODE and XTSEL can be written"]
123    #[inline(always)]
124    pub fn value2(self) -> &'a mut crate::W<REG> {
125        self.variant(XTWC_A::VALUE2)
126    }
127}
128#[doc = "Field `GTSEL` reader - Gate Input Selection"]
129pub type GTSEL_R = crate::FieldReader;
130#[doc = "Field `GTSEL` writer - Gate Input Selection"]
131pub type GTSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
132#[doc = "Field `GTLVL` reader - Gate Input Level"]
133pub type GTLVL_R = crate::BitReader;
134#[doc = "Write Control for Gate Configuration\n\nValue on reset: 0"]
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136pub enum GTWC_A {
137    #[doc = "0: No write access to gate configuration"]
138    VALUE1 = 0,
139    #[doc = "1: Bitfield GTSEL can be written"]
140    VALUE2 = 1,
141}
142impl From<GTWC_A> for bool {
143    #[inline(always)]
144    fn from(variant: GTWC_A) -> Self {
145        variant as u8 != 0
146    }
147}
148#[doc = "Field `GTWC` writer - Write Control for Gate Configuration"]
149pub type GTWC_W<'a, REG> = crate::BitWriter<'a, REG, GTWC_A>;
150impl<'a, REG> GTWC_W<'a, REG>
151where
152    REG: crate::Writable + crate::RegisterSpec,
153{
154    #[doc = "No write access to gate configuration"]
155    #[inline(always)]
156    pub fn value1(self) -> &'a mut crate::W<REG> {
157        self.variant(GTWC_A::VALUE1)
158    }
159    #[doc = "Bitfield GTSEL can be written"]
160    #[inline(always)]
161    pub fn value2(self) -> &'a mut crate::W<REG> {
162        self.variant(GTWC_A::VALUE2)
163    }
164}
165#[doc = "Timer Mode Enable\n\nValue on reset: 0"]
166#[derive(Clone, Copy, Debug, PartialEq, Eq)]
167pub enum TMEN_A {
168    #[doc = "0: No timer mode: standard gating mechanism can be used"]
169    VALUE1 = 0,
170    #[doc = "1: Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled"]
171    VALUE2 = 1,
172}
173impl From<TMEN_A> for bool {
174    #[inline(always)]
175    fn from(variant: TMEN_A) -> Self {
176        variant as u8 != 0
177    }
178}
179#[doc = "Field `TMEN` reader - Timer Mode Enable"]
180pub type TMEN_R = crate::BitReader<TMEN_A>;
181impl TMEN_R {
182    #[doc = "Get enumerated values variant"]
183    #[inline(always)]
184    pub const fn variant(&self) -> TMEN_A {
185        match self.bits {
186            false => TMEN_A::VALUE1,
187            true => TMEN_A::VALUE2,
188        }
189    }
190    #[doc = "No timer mode: standard gating mechanism can be used"]
191    #[inline(always)]
192    pub fn is_value1(&self) -> bool {
193        *self == TMEN_A::VALUE1
194    }
195    #[doc = "Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled"]
196    #[inline(always)]
197    pub fn is_value2(&self) -> bool {
198        *self == TMEN_A::VALUE2
199    }
200}
201#[doc = "Field `TMEN` writer - Timer Mode Enable"]
202pub type TMEN_W<'a, REG> = crate::BitWriter<'a, REG, TMEN_A>;
203impl<'a, REG> TMEN_W<'a, REG>
204where
205    REG: crate::Writable + crate::RegisterSpec,
206{
207    #[doc = "No timer mode: standard gating mechanism can be used"]
208    #[inline(always)]
209    pub fn value1(self) -> &'a mut crate::W<REG> {
210        self.variant(TMEN_A::VALUE1)
211    }
212    #[doc = "Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled"]
213    #[inline(always)]
214    pub fn value2(self) -> &'a mut crate::W<REG> {
215        self.variant(TMEN_A::VALUE2)
216    }
217}
218#[doc = "Write Control for Timer Mode\n\nValue on reset: 0"]
219#[derive(Clone, Copy, Debug, PartialEq, Eq)]
220pub enum TMWC_A {
221    #[doc = "0: No write access to timer mode"]
222    VALUE1 = 0,
223    #[doc = "1: Bitfield TMEN can be written"]
224    VALUE2 = 1,
225}
226impl From<TMWC_A> for bool {
227    #[inline(always)]
228    fn from(variant: TMWC_A) -> Self {
229        variant as u8 != 0
230    }
231}
232#[doc = "Field `TMWC` writer - Write Control for Timer Mode"]
233pub type TMWC_W<'a, REG> = crate::BitWriter<'a, REG, TMWC_A>;
234impl<'a, REG> TMWC_W<'a, REG>
235where
236    REG: crate::Writable + crate::RegisterSpec,
237{
238    #[doc = "No write access to timer mode"]
239    #[inline(always)]
240    pub fn value1(self) -> &'a mut crate::W<REG> {
241        self.variant(TMWC_A::VALUE1)
242    }
243    #[doc = "Bitfield TMEN can be written"]
244    #[inline(always)]
245    pub fn value2(self) -> &'a mut crate::W<REG> {
246        self.variant(TMWC_A::VALUE2)
247    }
248}
249impl R {
250    #[doc = "Bits 8:11 - External Trigger Input Selection"]
251    #[inline(always)]
252    pub fn xtsel(&self) -> XTSEL_R {
253        XTSEL_R::new(((self.bits >> 8) & 0x0f) as u8)
254    }
255    #[doc = "Bit 12 - External Trigger Level"]
256    #[inline(always)]
257    pub fn xtlvl(&self) -> XTLVL_R {
258        XTLVL_R::new(((self.bits >> 12) & 1) != 0)
259    }
260    #[doc = "Bits 13:14 - Trigger Operating Mode"]
261    #[inline(always)]
262    pub fn xtmode(&self) -> XTMODE_R {
263        XTMODE_R::new(((self.bits >> 13) & 3) as u8)
264    }
265    #[doc = "Bits 16:19 - Gate Input Selection"]
266    #[inline(always)]
267    pub fn gtsel(&self) -> GTSEL_R {
268        GTSEL_R::new(((self.bits >> 16) & 0x0f) as u8)
269    }
270    #[doc = "Bit 20 - Gate Input Level"]
271    #[inline(always)]
272    pub fn gtlvl(&self) -> GTLVL_R {
273        GTLVL_R::new(((self.bits >> 20) & 1) != 0)
274    }
275    #[doc = "Bit 28 - Timer Mode Enable"]
276    #[inline(always)]
277    pub fn tmen(&self) -> TMEN_R {
278        TMEN_R::new(((self.bits >> 28) & 1) != 0)
279    }
280}
281impl W {
282    #[doc = "Bits 8:11 - External Trigger Input Selection"]
283    #[inline(always)]
284    pub fn xtsel(&mut self) -> XTSEL_W<ASCTRL_SPEC> {
285        XTSEL_W::new(self, 8)
286    }
287    #[doc = "Bits 13:14 - Trigger Operating Mode"]
288    #[inline(always)]
289    pub fn xtmode(&mut self) -> XTMODE_W<ASCTRL_SPEC> {
290        XTMODE_W::new(self, 13)
291    }
292    #[doc = "Bit 15 - Write Control for Trigger Configuration"]
293    #[inline(always)]
294    pub fn xtwc(&mut self) -> XTWC_W<ASCTRL_SPEC> {
295        XTWC_W::new(self, 15)
296    }
297    #[doc = "Bits 16:19 - Gate Input Selection"]
298    #[inline(always)]
299    pub fn gtsel(&mut self) -> GTSEL_W<ASCTRL_SPEC> {
300        GTSEL_W::new(self, 16)
301    }
302    #[doc = "Bit 23 - Write Control for Gate Configuration"]
303    #[inline(always)]
304    pub fn gtwc(&mut self) -> GTWC_W<ASCTRL_SPEC> {
305        GTWC_W::new(self, 23)
306    }
307    #[doc = "Bit 28 - Timer Mode Enable"]
308    #[inline(always)]
309    pub fn tmen(&mut self) -> TMEN_W<ASCTRL_SPEC> {
310        TMEN_W::new(self, 28)
311    }
312    #[doc = "Bit 31 - Write Control for Timer Mode"]
313    #[inline(always)]
314    pub fn tmwc(&mut self) -> TMWC_W<ASCTRL_SPEC> {
315        TMWC_W::new(self, 31)
316    }
317}
318#[doc = "Autoscan Source Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`asctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`asctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
319pub struct ASCTRL_SPEC;
320impl crate::RegisterSpec for ASCTRL_SPEC {
321    type Ux = u32;
322}
323#[doc = "`read()` method returns [`asctrl::R`](R) reader structure"]
324impl crate::Readable for ASCTRL_SPEC {}
325#[doc = "`write(|w| ..)` method takes [`asctrl::W`](W) writer structure"]
326impl crate::Writable for ASCTRL_SPEC {
327    type Safety = crate::Unsafe;
328    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
329    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
330}
331#[doc = "`reset()` method sets ASCTRL to value 0"]
332impl crate::Resettable for ASCTRL_SPEC {
333    const RESET_VALUE: u32 = 0;
334}
xmc4500/vadc_g0/asctrl.rs

xmc4500/vadc_g0/
asctrl.rs
