xmc4500/scu_clk/
extclkcr.rs

1#[doc = "Register `EXTCLKCR` reader"]
2pub type R = crate::R<EXTCLKCR_SPEC>;
3#[doc = "Register `EXTCLKCR` writer"]
4pub type W = crate::W<EXTCLKCR_SPEC>;
5#[doc = "External Clock Selection Value\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum ECKSEL_A {
9    #[doc = "0: fSYS clock"]
10    VALUE1 = 0,
11    #[doc = "2: fUSB clock"]
12    VALUE3 = 2,
13    #[doc = "3: fPLL clock divided according to ECKDIV bit field configuration"]
14    VALUE4 = 3,
15}
16impl From<ECKSEL_A> for u8 {
17    #[inline(always)]
18    fn from(variant: ECKSEL_A) -> Self {
19        variant as _
20    }
21}
22impl crate::FieldSpec for ECKSEL_A {
23    type Ux = u8;
24}
25impl crate::IsEnum for ECKSEL_A {}
26#[doc = "Field `ECKSEL` reader - External Clock Selection Value"]
27pub type ECKSEL_R = crate::FieldReader<ECKSEL_A>;
28impl ECKSEL_R {
29    #[doc = "Get enumerated values variant"]
30    #[inline(always)]
31    pub const fn variant(&self) -> Option<ECKSEL_A> {
32        match self.bits {
33            0 => Some(ECKSEL_A::VALUE1),
34            2 => Some(ECKSEL_A::VALUE3),
35            3 => Some(ECKSEL_A::VALUE4),
36            _ => None,
37        }
38    }
39    #[doc = "fSYS clock"]
40    #[inline(always)]
41    pub fn is_value1(&self) -> bool {
42        *self == ECKSEL_A::VALUE1
43    }
44    #[doc = "fUSB clock"]
45    #[inline(always)]
46    pub fn is_value3(&self) -> bool {
47        *self == ECKSEL_A::VALUE3
48    }
49    #[doc = "fPLL clock divided according to ECKDIV bit field configuration"]
50    #[inline(always)]
51    pub fn is_value4(&self) -> bool {
52        *self == ECKSEL_A::VALUE4
53    }
54}
55#[doc = "Field `ECKSEL` writer - External Clock Selection Value"]
56pub type ECKSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ECKSEL_A>;
57impl<'a, REG> ECKSEL_W<'a, REG>
58where
59    REG: crate::Writable + crate::RegisterSpec,
60    REG::Ux: From<u8>,
61{
62    #[doc = "fSYS clock"]
63    #[inline(always)]
64    pub fn value1(self) -> &'a mut crate::W<REG> {
65        self.variant(ECKSEL_A::VALUE1)
66    }
67    #[doc = "fUSB clock"]
68    #[inline(always)]
69    pub fn value3(self) -> &'a mut crate::W<REG> {
70        self.variant(ECKSEL_A::VALUE3)
71    }
72    #[doc = "fPLL clock divided according to ECKDIV bit field configuration"]
73    #[inline(always)]
74    pub fn value4(self) -> &'a mut crate::W<REG> {
75        self.variant(ECKSEL_A::VALUE4)
76    }
77}
78#[doc = "Field `ECKDIV` reader - External Clock Divider Value"]
79pub type ECKDIV_R = crate::FieldReader<u16>;
80#[doc = "Field `ECKDIV` writer - External Clock Divider Value"]
81pub type ECKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
82impl R {
83    #[doc = "Bits 0:1 - External Clock Selection Value"]
84    #[inline(always)]
85    pub fn ecksel(&self) -> ECKSEL_R {
86        ECKSEL_R::new((self.bits & 3) as u8)
87    }
88    #[doc = "Bits 16:24 - External Clock Divider Value"]
89    #[inline(always)]
90    pub fn eckdiv(&self) -> ECKDIV_R {
91        ECKDIV_R::new(((self.bits >> 16) & 0x01ff) as u16)
92    }
93}
94impl W {
95    #[doc = "Bits 0:1 - External Clock Selection Value"]
96    #[inline(always)]
97    pub fn ecksel(&mut self) -> ECKSEL_W<EXTCLKCR_SPEC> {
98        ECKSEL_W::new(self, 0)
99    }
100    #[doc = "Bits 16:24 - External Clock Divider Value"]
101    #[inline(always)]
102    pub fn eckdiv(&mut self) -> ECKDIV_W<EXTCLKCR_SPEC> {
103        ECKDIV_W::new(self, 16)
104    }
105}
106#[doc = "External Clock Control\n\nYou can [`read`](crate::Reg::read) this register and get [`extclkcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extclkcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct EXTCLKCR_SPEC;
108impl crate::RegisterSpec for EXTCLKCR_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`extclkcr::R`](R) reader structure"]
112impl crate::Readable for EXTCLKCR_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`extclkcr::W`](W) writer structure"]
114impl crate::Writable for EXTCLKCR_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets EXTCLKCR to value 0"]
120impl crate::Resettable for EXTCLKCR_SPEC {
121    const RESET_VALUE: u32 = 0;
122}
xmc4500/scu_clk/extclkcr.rs

xmc4500/scu_clk/
extclkcr.rs
