xmc4500/port3/
out.rs

1#[doc = "Register `OUT` reader"]
2pub type R = crate::R<OUT_SPEC>;
3#[doc = "Register `OUT` writer"]
4pub type W = crate::W<OUT_SPEC>;
5#[doc = "Port n Output Bit 0\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum P0_A {
8    #[doc = "0: The output level of Pn.x is 0."]
9    VALUE1 = 0,
10    #[doc = "1: The output level of Pn.x is 1."]
11    VALUE2 = 1,
12}
13impl From<P0_A> for bool {
14    #[inline(always)]
15    fn from(variant: P0_A) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `P0` reader - Port n Output Bit 0"]
20pub type P0_R = crate::BitReader<P0_A>;
21impl P0_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> P0_A {
25        match self.bits {
26            false => P0_A::VALUE1,
27            true => P0_A::VALUE2,
28        }
29    }
30    #[doc = "The output level of Pn.x is 0."]
31    #[inline(always)]
32    pub fn is_value1(&self) -> bool {
33        *self == P0_A::VALUE1
34    }
35    #[doc = "The output level of Pn.x is 1."]
36    #[inline(always)]
37    pub fn is_value2(&self) -> bool {
38        *self == P0_A::VALUE2
39    }
40}
41#[doc = "Field `P0` writer - Port n Output Bit 0"]
42pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0_A>;
43impl<'a, REG> P0_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "The output level of Pn.x is 0."]
48    #[inline(always)]
49    pub fn value1(self) -> &'a mut crate::W<REG> {
50        self.variant(P0_A::VALUE1)
51    }
52    #[doc = "The output level of Pn.x is 1."]
53    #[inline(always)]
54    pub fn value2(self) -> &'a mut crate::W<REG> {
55        self.variant(P0_A::VALUE2)
56    }
57}
58#[doc = "Port n Output Bit 1\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum P1_A {
61    #[doc = "0: The output level of Pn.x is 0."]
62    VALUE1 = 0,
63    #[doc = "1: The output level of Pn.x is 1."]
64    VALUE2 = 1,
65}
66impl From<P1_A> for bool {
67    #[inline(always)]
68    fn from(variant: P1_A) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `P1` reader - Port n Output Bit 1"]
73pub type P1_R = crate::BitReader<P1_A>;
74impl P1_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> P1_A {
78        match self.bits {
79            false => P1_A::VALUE1,
80            true => P1_A::VALUE2,
81        }
82    }
83    #[doc = "The output level of Pn.x is 0."]
84    #[inline(always)]
85    pub fn is_value1(&self) -> bool {
86        *self == P1_A::VALUE1
87    }
88    #[doc = "The output level of Pn.x is 1."]
89    #[inline(always)]
90    pub fn is_value2(&self) -> bool {
91        *self == P1_A::VALUE2
92    }
93}
94#[doc = "Field `P1` writer - Port n Output Bit 1"]
95pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1_A>;
96impl<'a, REG> P1_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "The output level of Pn.x is 0."]
101    #[inline(always)]
102    pub fn value1(self) -> &'a mut crate::W<REG> {
103        self.variant(P1_A::VALUE1)
104    }
105    #[doc = "The output level of Pn.x is 1."]
106    #[inline(always)]
107    pub fn value2(self) -> &'a mut crate::W<REG> {
108        self.variant(P1_A::VALUE2)
109    }
110}
111#[doc = "Port n Output Bit 2\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum P2_A {
114    #[doc = "0: The output level of Pn.x is 0."]
115    VALUE1 = 0,
116    #[doc = "1: The output level of Pn.x is 1."]
117    VALUE2 = 1,
118}
119impl From<P2_A> for bool {
120    #[inline(always)]
121    fn from(variant: P2_A) -> Self {
122        variant as u8 != 0
123    }
124}
125#[doc = "Field `P2` reader - Port n Output Bit 2"]
126pub type P2_R = crate::BitReader<P2_A>;
127impl P2_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> P2_A {
131        match self.bits {
132            false => P2_A::VALUE1,
133            true => P2_A::VALUE2,
134        }
135    }
136    #[doc = "The output level of Pn.x is 0."]
137    #[inline(always)]
138    pub fn is_value1(&self) -> bool {
139        *self == P2_A::VALUE1
140    }
141    #[doc = "The output level of Pn.x is 1."]
142    #[inline(always)]
143    pub fn is_value2(&self) -> bool {
144        *self == P2_A::VALUE2
145    }
146}
147#[doc = "Field `P2` writer - Port n Output Bit 2"]
148pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2_A>;
149impl<'a, REG> P2_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "The output level of Pn.x is 0."]
154    #[inline(always)]
155    pub fn value1(self) -> &'a mut crate::W<REG> {
156        self.variant(P2_A::VALUE1)
157    }
158    #[doc = "The output level of Pn.x is 1."]
159    #[inline(always)]
160    pub fn value2(self) -> &'a mut crate::W<REG> {
161        self.variant(P2_A::VALUE2)
162    }
163}
164#[doc = "Port n Output Bit 3\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum P3_A {
167    #[doc = "0: The output level of Pn.x is 0."]
168    VALUE1 = 0,
169    #[doc = "1: The output level of Pn.x is 1."]
170    VALUE2 = 1,
171}
172impl From<P3_A> for bool {
173    #[inline(always)]
174    fn from(variant: P3_A) -> Self {
175        variant as u8 != 0
176    }
177}
178#[doc = "Field `P3` reader - Port n Output Bit 3"]
179pub type P3_R = crate::BitReader<P3_A>;
180impl P3_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> P3_A {
184        match self.bits {
185            false => P3_A::VALUE1,
186            true => P3_A::VALUE2,
187        }
188    }
189    #[doc = "The output level of Pn.x is 0."]
190    #[inline(always)]
191    pub fn is_value1(&self) -> bool {
192        *self == P3_A::VALUE1
193    }
194    #[doc = "The output level of Pn.x is 1."]
195    #[inline(always)]
196    pub fn is_value2(&self) -> bool {
197        *self == P3_A::VALUE2
198    }
199}
200#[doc = "Field `P3` writer - Port n Output Bit 3"]
201pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3_A>;
202impl<'a, REG> P3_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "The output level of Pn.x is 0."]
207    #[inline(always)]
208    pub fn value1(self) -> &'a mut crate::W<REG> {
209        self.variant(P3_A::VALUE1)
210    }
211    #[doc = "The output level of Pn.x is 1."]
212    #[inline(always)]
213    pub fn value2(self) -> &'a mut crate::W<REG> {
214        self.variant(P3_A::VALUE2)
215    }
216}
217#[doc = "Port n Output Bit 4\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219pub enum P4_A {
220    #[doc = "0: The output level of Pn.x is 0."]
221    VALUE1 = 0,
222    #[doc = "1: The output level of Pn.x is 1."]
223    VALUE2 = 1,
224}
225impl From<P4_A> for bool {
226    #[inline(always)]
227    fn from(variant: P4_A) -> Self {
228        variant as u8 != 0
229    }
230}
231#[doc = "Field `P4` reader - Port n Output Bit 4"]
232pub type P4_R = crate::BitReader<P4_A>;
233impl P4_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> P4_A {
237        match self.bits {
238            false => P4_A::VALUE1,
239            true => P4_A::VALUE2,
240        }
241    }
242    #[doc = "The output level of Pn.x is 0."]
243    #[inline(always)]
244    pub fn is_value1(&self) -> bool {
245        *self == P4_A::VALUE1
246    }
247    #[doc = "The output level of Pn.x is 1."]
248    #[inline(always)]
249    pub fn is_value2(&self) -> bool {
250        *self == P4_A::VALUE2
251    }
252}
253#[doc = "Field `P4` writer - Port n Output Bit 4"]
254pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4_A>;
255impl<'a, REG> P4_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "The output level of Pn.x is 0."]
260    #[inline(always)]
261    pub fn value1(self) -> &'a mut crate::W<REG> {
262        self.variant(P4_A::VALUE1)
263    }
264    #[doc = "The output level of Pn.x is 1."]
265    #[inline(always)]
266    pub fn value2(self) -> &'a mut crate::W<REG> {
267        self.variant(P4_A::VALUE2)
268    }
269}
270#[doc = "Port n Output Bit 5\n\nValue on reset: 0"]
271#[derive(Clone, Copy, Debug, PartialEq, Eq)]
272pub enum P5_A {
273    #[doc = "0: The output level of Pn.x is 0."]
274    VALUE1 = 0,
275    #[doc = "1: The output level of Pn.x is 1."]
276    VALUE2 = 1,
277}
278impl From<P5_A> for bool {
279    #[inline(always)]
280    fn from(variant: P5_A) -> Self {
281        variant as u8 != 0
282    }
283}
284#[doc = "Field `P5` reader - Port n Output Bit 5"]
285pub type P5_R = crate::BitReader<P5_A>;
286impl P5_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> P5_A {
290        match self.bits {
291            false => P5_A::VALUE1,
292            true => P5_A::VALUE2,
293        }
294    }
295    #[doc = "The output level of Pn.x is 0."]
296    #[inline(always)]
297    pub fn is_value1(&self) -> bool {
298        *self == P5_A::VALUE1
299    }
300    #[doc = "The output level of Pn.x is 1."]
301    #[inline(always)]
302    pub fn is_value2(&self) -> bool {
303        *self == P5_A::VALUE2
304    }
305}
306#[doc = "Field `P5` writer - Port n Output Bit 5"]
307pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5_A>;
308impl<'a, REG> P5_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "The output level of Pn.x is 0."]
313    #[inline(always)]
314    pub fn value1(self) -> &'a mut crate::W<REG> {
315        self.variant(P5_A::VALUE1)
316    }
317    #[doc = "The output level of Pn.x is 1."]
318    #[inline(always)]
319    pub fn value2(self) -> &'a mut crate::W<REG> {
320        self.variant(P5_A::VALUE2)
321    }
322}
323#[doc = "Port n Output Bit 6\n\nValue on reset: 0"]
324#[derive(Clone, Copy, Debug, PartialEq, Eq)]
325pub enum P6_A {
326    #[doc = "0: The output level of Pn.x is 0."]
327    VALUE1 = 0,
328    #[doc = "1: The output level of Pn.x is 1."]
329    VALUE2 = 1,
330}
331impl From<P6_A> for bool {
332    #[inline(always)]
333    fn from(variant: P6_A) -> Self {
334        variant as u8 != 0
335    }
336}
337#[doc = "Field `P6` reader - Port n Output Bit 6"]
338pub type P6_R = crate::BitReader<P6_A>;
339impl P6_R {
340    #[doc = "Get enumerated values variant"]
341    #[inline(always)]
342    pub const fn variant(&self) -> P6_A {
343        match self.bits {
344            false => P6_A::VALUE1,
345            true => P6_A::VALUE2,
346        }
347    }
348    #[doc = "The output level of Pn.x is 0."]
349    #[inline(always)]
350    pub fn is_value1(&self) -> bool {
351        *self == P6_A::VALUE1
352    }
353    #[doc = "The output level of Pn.x is 1."]
354    #[inline(always)]
355    pub fn is_value2(&self) -> bool {
356        *self == P6_A::VALUE2
357    }
358}
359#[doc = "Field `P6` writer - Port n Output Bit 6"]
360pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6_A>;
361impl<'a, REG> P6_W<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364{
365    #[doc = "The output level of Pn.x is 0."]
366    #[inline(always)]
367    pub fn value1(self) -> &'a mut crate::W<REG> {
368        self.variant(P6_A::VALUE1)
369    }
370    #[doc = "The output level of Pn.x is 1."]
371    #[inline(always)]
372    pub fn value2(self) -> &'a mut crate::W<REG> {
373        self.variant(P6_A::VALUE2)
374    }
375}
376#[doc = "Port n Output Bit 7\n\nValue on reset: 0"]
377#[derive(Clone, Copy, Debug, PartialEq, Eq)]
378pub enum P7_A {
379    #[doc = "0: The output level of Pn.x is 0."]
380    VALUE1 = 0,
381    #[doc = "1: The output level of Pn.x is 1."]
382    VALUE2 = 1,
383}
384impl From<P7_A> for bool {
385    #[inline(always)]
386    fn from(variant: P7_A) -> Self {
387        variant as u8 != 0
388    }
389}
390#[doc = "Field `P7` reader - Port n Output Bit 7"]
391pub type P7_R = crate::BitReader<P7_A>;
392impl P7_R {
393    #[doc = "Get enumerated values variant"]
394    #[inline(always)]
395    pub const fn variant(&self) -> P7_A {
396        match self.bits {
397            false => P7_A::VALUE1,
398            true => P7_A::VALUE2,
399        }
400    }
401    #[doc = "The output level of Pn.x is 0."]
402    #[inline(always)]
403    pub fn is_value1(&self) -> bool {
404        *self == P7_A::VALUE1
405    }
406    #[doc = "The output level of Pn.x is 1."]
407    #[inline(always)]
408    pub fn is_value2(&self) -> bool {
409        *self == P7_A::VALUE2
410    }
411}
412#[doc = "Field `P7` writer - Port n Output Bit 7"]
413pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7_A>;
414impl<'a, REG> P7_W<'a, REG>
415where
416    REG: crate::Writable + crate::RegisterSpec,
417{
418    #[doc = "The output level of Pn.x is 0."]
419    #[inline(always)]
420    pub fn value1(self) -> &'a mut crate::W<REG> {
421        self.variant(P7_A::VALUE1)
422    }
423    #[doc = "The output level of Pn.x is 1."]
424    #[inline(always)]
425    pub fn value2(self) -> &'a mut crate::W<REG> {
426        self.variant(P7_A::VALUE2)
427    }
428}
429#[doc = "Port n Output Bit 8\n\nValue on reset: 0"]
430#[derive(Clone, Copy, Debug, PartialEq, Eq)]
431pub enum P8_A {
432    #[doc = "0: The output level of Pn.x is 0."]
433    VALUE1 = 0,
434    #[doc = "1: The output level of Pn.x is 1."]
435    VALUE2 = 1,
436}
437impl From<P8_A> for bool {
438    #[inline(always)]
439    fn from(variant: P8_A) -> Self {
440        variant as u8 != 0
441    }
442}
443#[doc = "Field `P8` reader - Port n Output Bit 8"]
444pub type P8_R = crate::BitReader<P8_A>;
445impl P8_R {
446    #[doc = "Get enumerated values variant"]
447    #[inline(always)]
448    pub const fn variant(&self) -> P8_A {
449        match self.bits {
450            false => P8_A::VALUE1,
451            true => P8_A::VALUE2,
452        }
453    }
454    #[doc = "The output level of Pn.x is 0."]
455    #[inline(always)]
456    pub fn is_value1(&self) -> bool {
457        *self == P8_A::VALUE1
458    }
459    #[doc = "The output level of Pn.x is 1."]
460    #[inline(always)]
461    pub fn is_value2(&self) -> bool {
462        *self == P8_A::VALUE2
463    }
464}
465#[doc = "Field `P8` writer - Port n Output Bit 8"]
466pub type P8_W<'a, REG> = crate::BitWriter<'a, REG, P8_A>;
467impl<'a, REG> P8_W<'a, REG>
468where
469    REG: crate::Writable + crate::RegisterSpec,
470{
471    #[doc = "The output level of Pn.x is 0."]
472    #[inline(always)]
473    pub fn value1(self) -> &'a mut crate::W<REG> {
474        self.variant(P8_A::VALUE1)
475    }
476    #[doc = "The output level of Pn.x is 1."]
477    #[inline(always)]
478    pub fn value2(self) -> &'a mut crate::W<REG> {
479        self.variant(P8_A::VALUE2)
480    }
481}
482#[doc = "Port n Output Bit 9\n\nValue on reset: 0"]
483#[derive(Clone, Copy, Debug, PartialEq, Eq)]
484pub enum P9_A {
485    #[doc = "0: The output level of Pn.x is 0."]
486    VALUE1 = 0,
487    #[doc = "1: The output level of Pn.x is 1."]
488    VALUE2 = 1,
489}
490impl From<P9_A> for bool {
491    #[inline(always)]
492    fn from(variant: P9_A) -> Self {
493        variant as u8 != 0
494    }
495}
496#[doc = "Field `P9` reader - Port n Output Bit 9"]
497pub type P9_R = crate::BitReader<P9_A>;
498impl P9_R {
499    #[doc = "Get enumerated values variant"]
500    #[inline(always)]
501    pub const fn variant(&self) -> P9_A {
502        match self.bits {
503            false => P9_A::VALUE1,
504            true => P9_A::VALUE2,
505        }
506    }
507    #[doc = "The output level of Pn.x is 0."]
508    #[inline(always)]
509    pub fn is_value1(&self) -> bool {
510        *self == P9_A::VALUE1
511    }
512    #[doc = "The output level of Pn.x is 1."]
513    #[inline(always)]
514    pub fn is_value2(&self) -> bool {
515        *self == P9_A::VALUE2
516    }
517}
518#[doc = "Field `P9` writer - Port n Output Bit 9"]
519pub type P9_W<'a, REG> = crate::BitWriter<'a, REG, P9_A>;
520impl<'a, REG> P9_W<'a, REG>
521where
522    REG: crate::Writable + crate::RegisterSpec,
523{
524    #[doc = "The output level of Pn.x is 0."]
525    #[inline(always)]
526    pub fn value1(self) -> &'a mut crate::W<REG> {
527        self.variant(P9_A::VALUE1)
528    }
529    #[doc = "The output level of Pn.x is 1."]
530    #[inline(always)]
531    pub fn value2(self) -> &'a mut crate::W<REG> {
532        self.variant(P9_A::VALUE2)
533    }
534}
535#[doc = "Port n Output Bit 10\n\nValue on reset: 0"]
536#[derive(Clone, Copy, Debug, PartialEq, Eq)]
537pub enum P10_A {
538    #[doc = "0: The output level of Pn.x is 0."]
539    VALUE1 = 0,
540    #[doc = "1: The output level of Pn.x is 1."]
541    VALUE2 = 1,
542}
543impl From<P10_A> for bool {
544    #[inline(always)]
545    fn from(variant: P10_A) -> Self {
546        variant as u8 != 0
547    }
548}
549#[doc = "Field `P10` reader - Port n Output Bit 10"]
550pub type P10_R = crate::BitReader<P10_A>;
551impl P10_R {
552    #[doc = "Get enumerated values variant"]
553    #[inline(always)]
554    pub const fn variant(&self) -> P10_A {
555        match self.bits {
556            false => P10_A::VALUE1,
557            true => P10_A::VALUE2,
558        }
559    }
560    #[doc = "The output level of Pn.x is 0."]
561    #[inline(always)]
562    pub fn is_value1(&self) -> bool {
563        *self == P10_A::VALUE1
564    }
565    #[doc = "The output level of Pn.x is 1."]
566    #[inline(always)]
567    pub fn is_value2(&self) -> bool {
568        *self == P10_A::VALUE2
569    }
570}
571#[doc = "Field `P10` writer - Port n Output Bit 10"]
572pub type P10_W<'a, REG> = crate::BitWriter<'a, REG, P10_A>;
573impl<'a, REG> P10_W<'a, REG>
574where
575    REG: crate::Writable + crate::RegisterSpec,
576{
577    #[doc = "The output level of Pn.x is 0."]
578    #[inline(always)]
579    pub fn value1(self) -> &'a mut crate::W<REG> {
580        self.variant(P10_A::VALUE1)
581    }
582    #[doc = "The output level of Pn.x is 1."]
583    #[inline(always)]
584    pub fn value2(self) -> &'a mut crate::W<REG> {
585        self.variant(P10_A::VALUE2)
586    }
587}
588#[doc = "Port n Output Bit 11\n\nValue on reset: 0"]
589#[derive(Clone, Copy, Debug, PartialEq, Eq)]
590pub enum P11_A {
591    #[doc = "0: The output level of Pn.x is 0."]
592    VALUE1 = 0,
593    #[doc = "1: The output level of Pn.x is 1."]
594    VALUE2 = 1,
595}
596impl From<P11_A> for bool {
597    #[inline(always)]
598    fn from(variant: P11_A) -> Self {
599        variant as u8 != 0
600    }
601}
602#[doc = "Field `P11` reader - Port n Output Bit 11"]
603pub type P11_R = crate::BitReader<P11_A>;
604impl P11_R {
605    #[doc = "Get enumerated values variant"]
606    #[inline(always)]
607    pub const fn variant(&self) -> P11_A {
608        match self.bits {
609            false => P11_A::VALUE1,
610            true => P11_A::VALUE2,
611        }
612    }
613    #[doc = "The output level of Pn.x is 0."]
614    #[inline(always)]
615    pub fn is_value1(&self) -> bool {
616        *self == P11_A::VALUE1
617    }
618    #[doc = "The output level of Pn.x is 1."]
619    #[inline(always)]
620    pub fn is_value2(&self) -> bool {
621        *self == P11_A::VALUE2
622    }
623}
624#[doc = "Field `P11` writer - Port n Output Bit 11"]
625pub type P11_W<'a, REG> = crate::BitWriter<'a, REG, P11_A>;
626impl<'a, REG> P11_W<'a, REG>
627where
628    REG: crate::Writable + crate::RegisterSpec,
629{
630    #[doc = "The output level of Pn.x is 0."]
631    #[inline(always)]
632    pub fn value1(self) -> &'a mut crate::W<REG> {
633        self.variant(P11_A::VALUE1)
634    }
635    #[doc = "The output level of Pn.x is 1."]
636    #[inline(always)]
637    pub fn value2(self) -> &'a mut crate::W<REG> {
638        self.variant(P11_A::VALUE2)
639    }
640}
641#[doc = "Port n Output Bit 12\n\nValue on reset: 0"]
642#[derive(Clone, Copy, Debug, PartialEq, Eq)]
643pub enum P12_A {
644    #[doc = "0: The output level of Pn.x is 0."]
645    VALUE1 = 0,
646    #[doc = "1: The output level of Pn.x is 1."]
647    VALUE2 = 1,
648}
649impl From<P12_A> for bool {
650    #[inline(always)]
651    fn from(variant: P12_A) -> Self {
652        variant as u8 != 0
653    }
654}
655#[doc = "Field `P12` reader - Port n Output Bit 12"]
656pub type P12_R = crate::BitReader<P12_A>;
657impl P12_R {
658    #[doc = "Get enumerated values variant"]
659    #[inline(always)]
660    pub const fn variant(&self) -> P12_A {
661        match self.bits {
662            false => P12_A::VALUE1,
663            true => P12_A::VALUE2,
664        }
665    }
666    #[doc = "The output level of Pn.x is 0."]
667    #[inline(always)]
668    pub fn is_value1(&self) -> bool {
669        *self == P12_A::VALUE1
670    }
671    #[doc = "The output level of Pn.x is 1."]
672    #[inline(always)]
673    pub fn is_value2(&self) -> bool {
674        *self == P12_A::VALUE2
675    }
676}
677#[doc = "Field `P12` writer - Port n Output Bit 12"]
678pub type P12_W<'a, REG> = crate::BitWriter<'a, REG, P12_A>;
679impl<'a, REG> P12_W<'a, REG>
680where
681    REG: crate::Writable + crate::RegisterSpec,
682{
683    #[doc = "The output level of Pn.x is 0."]
684    #[inline(always)]
685    pub fn value1(self) -> &'a mut crate::W<REG> {
686        self.variant(P12_A::VALUE1)
687    }
688    #[doc = "The output level of Pn.x is 1."]
689    #[inline(always)]
690    pub fn value2(self) -> &'a mut crate::W<REG> {
691        self.variant(P12_A::VALUE2)
692    }
693}
694#[doc = "Port n Output Bit 13\n\nValue on reset: 0"]
695#[derive(Clone, Copy, Debug, PartialEq, Eq)]
696pub enum P13_A {
697    #[doc = "0: The output level of Pn.x is 0."]
698    VALUE1 = 0,
699    #[doc = "1: The output level of Pn.x is 1."]
700    VALUE2 = 1,
701}
702impl From<P13_A> for bool {
703    #[inline(always)]
704    fn from(variant: P13_A) -> Self {
705        variant as u8 != 0
706    }
707}
708#[doc = "Field `P13` reader - Port n Output Bit 13"]
709pub type P13_R = crate::BitReader<P13_A>;
710impl P13_R {
711    #[doc = "Get enumerated values variant"]
712    #[inline(always)]
713    pub const fn variant(&self) -> P13_A {
714        match self.bits {
715            false => P13_A::VALUE1,
716            true => P13_A::VALUE2,
717        }
718    }
719    #[doc = "The output level of Pn.x is 0."]
720    #[inline(always)]
721    pub fn is_value1(&self) -> bool {
722        *self == P13_A::VALUE1
723    }
724    #[doc = "The output level of Pn.x is 1."]
725    #[inline(always)]
726    pub fn is_value2(&self) -> bool {
727        *self == P13_A::VALUE2
728    }
729}
730#[doc = "Field `P13` writer - Port n Output Bit 13"]
731pub type P13_W<'a, REG> = crate::BitWriter<'a, REG, P13_A>;
732impl<'a, REG> P13_W<'a, REG>
733where
734    REG: crate::Writable + crate::RegisterSpec,
735{
736    #[doc = "The output level of Pn.x is 0."]
737    #[inline(always)]
738    pub fn value1(self) -> &'a mut crate::W<REG> {
739        self.variant(P13_A::VALUE1)
740    }
741    #[doc = "The output level of Pn.x is 1."]
742    #[inline(always)]
743    pub fn value2(self) -> &'a mut crate::W<REG> {
744        self.variant(P13_A::VALUE2)
745    }
746}
747#[doc = "Port n Output Bit 14\n\nValue on reset: 0"]
748#[derive(Clone, Copy, Debug, PartialEq, Eq)]
749pub enum P14_A {
750    #[doc = "0: The output level of Pn.x is 0."]
751    VALUE1 = 0,
752    #[doc = "1: The output level of Pn.x is 1."]
753    VALUE2 = 1,
754}
755impl From<P14_A> for bool {
756    #[inline(always)]
757    fn from(variant: P14_A) -> Self {
758        variant as u8 != 0
759    }
760}
761#[doc = "Field `P14` reader - Port n Output Bit 14"]
762pub type P14_R = crate::BitReader<P14_A>;
763impl P14_R {
764    #[doc = "Get enumerated values variant"]
765    #[inline(always)]
766    pub const fn variant(&self) -> P14_A {
767        match self.bits {
768            false => P14_A::VALUE1,
769            true => P14_A::VALUE2,
770        }
771    }
772    #[doc = "The output level of Pn.x is 0."]
773    #[inline(always)]
774    pub fn is_value1(&self) -> bool {
775        *self == P14_A::VALUE1
776    }
777    #[doc = "The output level of Pn.x is 1."]
778    #[inline(always)]
779    pub fn is_value2(&self) -> bool {
780        *self == P14_A::VALUE2
781    }
782}
783#[doc = "Field `P14` writer - Port n Output Bit 14"]
784pub type P14_W<'a, REG> = crate::BitWriter<'a, REG, P14_A>;
785impl<'a, REG> P14_W<'a, REG>
786where
787    REG: crate::Writable + crate::RegisterSpec,
788{
789    #[doc = "The output level of Pn.x is 0."]
790    #[inline(always)]
791    pub fn value1(self) -> &'a mut crate::W<REG> {
792        self.variant(P14_A::VALUE1)
793    }
794    #[doc = "The output level of Pn.x is 1."]
795    #[inline(always)]
796    pub fn value2(self) -> &'a mut crate::W<REG> {
797        self.variant(P14_A::VALUE2)
798    }
799}
800#[doc = "Port n Output Bit 15\n\nValue on reset: 0"]
801#[derive(Clone, Copy, Debug, PartialEq, Eq)]
802pub enum P15_A {
803    #[doc = "0: The output level of Pn.x is 0."]
804    VALUE1 = 0,
805    #[doc = "1: The output level of Pn.x is 1."]
806    VALUE2 = 1,
807}
808impl From<P15_A> for bool {
809    #[inline(always)]
810    fn from(variant: P15_A) -> Self {
811        variant as u8 != 0
812    }
813}
814#[doc = "Field `P15` reader - Port n Output Bit 15"]
815pub type P15_R = crate::BitReader<P15_A>;
816impl P15_R {
817    #[doc = "Get enumerated values variant"]
818    #[inline(always)]
819    pub const fn variant(&self) -> P15_A {
820        match self.bits {
821            false => P15_A::VALUE1,
822            true => P15_A::VALUE2,
823        }
824    }
825    #[doc = "The output level of Pn.x is 0."]
826    #[inline(always)]
827    pub fn is_value1(&self) -> bool {
828        *self == P15_A::VALUE1
829    }
830    #[doc = "The output level of Pn.x is 1."]
831    #[inline(always)]
832    pub fn is_value2(&self) -> bool {
833        *self == P15_A::VALUE2
834    }
835}
836#[doc = "Field `P15` writer - Port n Output Bit 15"]
837pub type P15_W<'a, REG> = crate::BitWriter<'a, REG, P15_A>;
838impl<'a, REG> P15_W<'a, REG>
839where
840    REG: crate::Writable + crate::RegisterSpec,
841{
842    #[doc = "The output level of Pn.x is 0."]
843    #[inline(always)]
844    pub fn value1(self) -> &'a mut crate::W<REG> {
845        self.variant(P15_A::VALUE1)
846    }
847    #[doc = "The output level of Pn.x is 1."]
848    #[inline(always)]
849    pub fn value2(self) -> &'a mut crate::W<REG> {
850        self.variant(P15_A::VALUE2)
851    }
852}
853impl R {
854    #[doc = "Bit 0 - Port n Output Bit 0"]
855    #[inline(always)]
856    pub fn p0(&self) -> P0_R {
857        P0_R::new((self.bits & 1) != 0)
858    }
859    #[doc = "Bit 1 - Port n Output Bit 1"]
860    #[inline(always)]
861    pub fn p1(&self) -> P1_R {
862        P1_R::new(((self.bits >> 1) & 1) != 0)
863    }
864    #[doc = "Bit 2 - Port n Output Bit 2"]
865    #[inline(always)]
866    pub fn p2(&self) -> P2_R {
867        P2_R::new(((self.bits >> 2) & 1) != 0)
868    }
869    #[doc = "Bit 3 - Port n Output Bit 3"]
870    #[inline(always)]
871    pub fn p3(&self) -> P3_R {
872        P3_R::new(((self.bits >> 3) & 1) != 0)
873    }
874    #[doc = "Bit 4 - Port n Output Bit 4"]
875    #[inline(always)]
876    pub fn p4(&self) -> P4_R {
877        P4_R::new(((self.bits >> 4) & 1) != 0)
878    }
879    #[doc = "Bit 5 - Port n Output Bit 5"]
880    #[inline(always)]
881    pub fn p5(&self) -> P5_R {
882        P5_R::new(((self.bits >> 5) & 1) != 0)
883    }
884    #[doc = "Bit 6 - Port n Output Bit 6"]
885    #[inline(always)]
886    pub fn p6(&self) -> P6_R {
887        P6_R::new(((self.bits >> 6) & 1) != 0)
888    }
889    #[doc = "Bit 7 - Port n Output Bit 7"]
890    #[inline(always)]
891    pub fn p7(&self) -> P7_R {
892        P7_R::new(((self.bits >> 7) & 1) != 0)
893    }
894    #[doc = "Bit 8 - Port n Output Bit 8"]
895    #[inline(always)]
896    pub fn p8(&self) -> P8_R {
897        P8_R::new(((self.bits >> 8) & 1) != 0)
898    }
899    #[doc = "Bit 9 - Port n Output Bit 9"]
900    #[inline(always)]
901    pub fn p9(&self) -> P9_R {
902        P9_R::new(((self.bits >> 9) & 1) != 0)
903    }
904    #[doc = "Bit 10 - Port n Output Bit 10"]
905    #[inline(always)]
906    pub fn p10(&self) -> P10_R {
907        P10_R::new(((self.bits >> 10) & 1) != 0)
908    }
909    #[doc = "Bit 11 - Port n Output Bit 11"]
910    #[inline(always)]
911    pub fn p11(&self) -> P11_R {
912        P11_R::new(((self.bits >> 11) & 1) != 0)
913    }
914    #[doc = "Bit 12 - Port n Output Bit 12"]
915    #[inline(always)]
916    pub fn p12(&self) -> P12_R {
917        P12_R::new(((self.bits >> 12) & 1) != 0)
918    }
919    #[doc = "Bit 13 - Port n Output Bit 13"]
920    #[inline(always)]
921    pub fn p13(&self) -> P13_R {
922        P13_R::new(((self.bits >> 13) & 1) != 0)
923    }
924    #[doc = "Bit 14 - Port n Output Bit 14"]
925    #[inline(always)]
926    pub fn p14(&self) -> P14_R {
927        P14_R::new(((self.bits >> 14) & 1) != 0)
928    }
929    #[doc = "Bit 15 - Port n Output Bit 15"]
930    #[inline(always)]
931    pub fn p15(&self) -> P15_R {
932        P15_R::new(((self.bits >> 15) & 1) != 0)
933    }
934}
935impl W {
936    #[doc = "Bit 0 - Port n Output Bit 0"]
937    #[inline(always)]
938    pub fn p0(&mut self) -> P0_W<OUT_SPEC> {
939        P0_W::new(self, 0)
940    }
941    #[doc = "Bit 1 - Port n Output Bit 1"]
942    #[inline(always)]
943    pub fn p1(&mut self) -> P1_W<OUT_SPEC> {
944        P1_W::new(self, 1)
945    }
946    #[doc = "Bit 2 - Port n Output Bit 2"]
947    #[inline(always)]
948    pub fn p2(&mut self) -> P2_W<OUT_SPEC> {
949        P2_W::new(self, 2)
950    }
951    #[doc = "Bit 3 - Port n Output Bit 3"]
952    #[inline(always)]
953    pub fn p3(&mut self) -> P3_W<OUT_SPEC> {
954        P3_W::new(self, 3)
955    }
956    #[doc = "Bit 4 - Port n Output Bit 4"]
957    #[inline(always)]
958    pub fn p4(&mut self) -> P4_W<OUT_SPEC> {
959        P4_W::new(self, 4)
960    }
961    #[doc = "Bit 5 - Port n Output Bit 5"]
962    #[inline(always)]
963    pub fn p5(&mut self) -> P5_W<OUT_SPEC> {
964        P5_W::new(self, 5)
965    }
966    #[doc = "Bit 6 - Port n Output Bit 6"]
967    #[inline(always)]
968    pub fn p6(&mut self) -> P6_W<OUT_SPEC> {
969        P6_W::new(self, 6)
970    }
971    #[doc = "Bit 7 - Port n Output Bit 7"]
972    #[inline(always)]
973    pub fn p7(&mut self) -> P7_W<OUT_SPEC> {
974        P7_W::new(self, 7)
975    }
976    #[doc = "Bit 8 - Port n Output Bit 8"]
977    #[inline(always)]
978    pub fn p8(&mut self) -> P8_W<OUT_SPEC> {
979        P8_W::new(self, 8)
980    }
981    #[doc = "Bit 9 - Port n Output Bit 9"]
982    #[inline(always)]
983    pub fn p9(&mut self) -> P9_W<OUT_SPEC> {
984        P9_W::new(self, 9)
985    }
986    #[doc = "Bit 10 - Port n Output Bit 10"]
987    #[inline(always)]
988    pub fn p10(&mut self) -> P10_W<OUT_SPEC> {
989        P10_W::new(self, 10)
990    }
991    #[doc = "Bit 11 - Port n Output Bit 11"]
992    #[inline(always)]
993    pub fn p11(&mut self) -> P11_W<OUT_SPEC> {
994        P11_W::new(self, 11)
995    }
996    #[doc = "Bit 12 - Port n Output Bit 12"]
997    #[inline(always)]
998    pub fn p12(&mut self) -> P12_W<OUT_SPEC> {
999        P12_W::new(self, 12)
1000    }
1001    #[doc = "Bit 13 - Port n Output Bit 13"]
1002    #[inline(always)]
1003    pub fn p13(&mut self) -> P13_W<OUT_SPEC> {
1004        P13_W::new(self, 13)
1005    }
1006    #[doc = "Bit 14 - Port n Output Bit 14"]
1007    #[inline(always)]
1008    pub fn p14(&mut self) -> P14_W<OUT_SPEC> {
1009        P14_W::new(self, 14)
1010    }
1011    #[doc = "Bit 15 - Port n Output Bit 15"]
1012    #[inline(always)]
1013    pub fn p15(&mut self) -> P15_W<OUT_SPEC> {
1014        P15_W::new(self, 15)
1015    }
1016}
1017#[doc = "Port 3 Output Register\n\nYou can [`read`](crate::Reg::read) this register and get [`out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1018pub struct OUT_SPEC;
1019impl crate::RegisterSpec for OUT_SPEC {
1020    type Ux = u32;
1021}
1022#[doc = "`read()` method returns [`out::R`](R) reader structure"]
1023impl crate::Readable for OUT_SPEC {}
1024#[doc = "`write(|w| ..)` method takes [`out::W`](W) writer structure"]
1025impl crate::Writable for OUT_SPEC {
1026    type Safety = crate::Unsafe;
1027    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1028    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1029}
1030#[doc = "`reset()` method sets OUT to value 0"]
1031impl crate::Resettable for OUT_SPEC {
1032    const RESET_VALUE: u32 = 0;
1033}
xmc4500/port3/out.rs

xmc4500/port3/
out.rs
