xmc4500/gpdma1/
clearblock.rs

1#[doc = "Register `CLEARBLOCK` writer"]
2pub type W = crate::W<CLEARBLOCK_SPEC>;
3#[doc = "Clear Interrupt Status and Raw Status for channel 0\n\nValue on reset: 0"]
4#[derive(Clone, Copy, Debug, PartialEq, Eq)]
5pub enum CH0_A {
6    #[doc = "0: no effect"]
7    VALUE1 = 0,
8    #[doc = "1: clear status"]
9    VALUE2 = 1,
10}
11impl From<CH0_A> for bool {
12    #[inline(always)]
13    fn from(variant: CH0_A) -> Self {
14        variant as u8 != 0
15    }
16}
17#[doc = "Field `CH0` writer - Clear Interrupt Status and Raw Status for channel 0"]
18pub type CH0_W<'a, REG> = crate::BitWriter<'a, REG, CH0_A>;
19impl<'a, REG> CH0_W<'a, REG>
20where
21    REG: crate::Writable + crate::RegisterSpec,
22{
23    #[doc = "no effect"]
24    #[inline(always)]
25    pub fn value1(self) -> &'a mut crate::W<REG> {
26        self.variant(CH0_A::VALUE1)
27    }
28    #[doc = "clear status"]
29    #[inline(always)]
30    pub fn value2(self) -> &'a mut crate::W<REG> {
31        self.variant(CH0_A::VALUE2)
32    }
33}
34#[doc = "Clear Interrupt Status and Raw Status for channel 1\n\nValue on reset: 0"]
35#[derive(Clone, Copy, Debug, PartialEq, Eq)]
36pub enum CH1_A {
37    #[doc = "0: no effect"]
38    VALUE1 = 0,
39    #[doc = "1: clear status"]
40    VALUE2 = 1,
41}
42impl From<CH1_A> for bool {
43    #[inline(always)]
44    fn from(variant: CH1_A) -> Self {
45        variant as u8 != 0
46    }
47}
48#[doc = "Field `CH1` writer - Clear Interrupt Status and Raw Status for channel 1"]
49pub type CH1_W<'a, REG> = crate::BitWriter<'a, REG, CH1_A>;
50impl<'a, REG> CH1_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    #[doc = "no effect"]
55    #[inline(always)]
56    pub fn value1(self) -> &'a mut crate::W<REG> {
57        self.variant(CH1_A::VALUE1)
58    }
59    #[doc = "clear status"]
60    #[inline(always)]
61    pub fn value2(self) -> &'a mut crate::W<REG> {
62        self.variant(CH1_A::VALUE2)
63    }
64}
65#[doc = "Clear Interrupt Status and Raw Status for channel 2\n\nValue on reset: 0"]
66#[derive(Clone, Copy, Debug, PartialEq, Eq)]
67pub enum CH2_A {
68    #[doc = "0: no effect"]
69    VALUE1 = 0,
70    #[doc = "1: clear status"]
71    VALUE2 = 1,
72}
73impl From<CH2_A> for bool {
74    #[inline(always)]
75    fn from(variant: CH2_A) -> Self {
76        variant as u8 != 0
77    }
78}
79#[doc = "Field `CH2` writer - Clear Interrupt Status and Raw Status for channel 2"]
80pub type CH2_W<'a, REG> = crate::BitWriter<'a, REG, CH2_A>;
81impl<'a, REG> CH2_W<'a, REG>
82where
83    REG: crate::Writable + crate::RegisterSpec,
84{
85    #[doc = "no effect"]
86    #[inline(always)]
87    pub fn value1(self) -> &'a mut crate::W<REG> {
88        self.variant(CH2_A::VALUE1)
89    }
90    #[doc = "clear status"]
91    #[inline(always)]
92    pub fn value2(self) -> &'a mut crate::W<REG> {
93        self.variant(CH2_A::VALUE2)
94    }
95}
96#[doc = "Clear Interrupt Status and Raw Status for channel 3\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98pub enum CH3_A {
99    #[doc = "0: no effect"]
100    VALUE1 = 0,
101    #[doc = "1: clear status"]
102    VALUE2 = 1,
103}
104impl From<CH3_A> for bool {
105    #[inline(always)]
106    fn from(variant: CH3_A) -> Self {
107        variant as u8 != 0
108    }
109}
110#[doc = "Field `CH3` writer - Clear Interrupt Status and Raw Status for channel 3"]
111pub type CH3_W<'a, REG> = crate::BitWriter<'a, REG, CH3_A>;
112impl<'a, REG> CH3_W<'a, REG>
113where
114    REG: crate::Writable + crate::RegisterSpec,
115{
116    #[doc = "no effect"]
117    #[inline(always)]
118    pub fn value1(self) -> &'a mut crate::W<REG> {
119        self.variant(CH3_A::VALUE1)
120    }
121    #[doc = "clear status"]
122    #[inline(always)]
123    pub fn value2(self) -> &'a mut crate::W<REG> {
124        self.variant(CH3_A::VALUE2)
125    }
126}
127impl W {
128    #[doc = "Bit 0 - Clear Interrupt Status and Raw Status for channel 0"]
129    #[inline(always)]
130    pub fn ch0(&mut self) -> CH0_W<CLEARBLOCK_SPEC> {
131        CH0_W::new(self, 0)
132    }
133    #[doc = "Bit 1 - Clear Interrupt Status and Raw Status for channel 1"]
134    #[inline(always)]
135    pub fn ch1(&mut self) -> CH1_W<CLEARBLOCK_SPEC> {
136        CH1_W::new(self, 1)
137    }
138    #[doc = "Bit 2 - Clear Interrupt Status and Raw Status for channel 2"]
139    #[inline(always)]
140    pub fn ch2(&mut self) -> CH2_W<CLEARBLOCK_SPEC> {
141        CH2_W::new(self, 2)
142    }
143    #[doc = "Bit 3 - Clear Interrupt Status and Raw Status for channel 3"]
144    #[inline(always)]
145    pub fn ch3(&mut self) -> CH3_W<CLEARBLOCK_SPEC> {
146        CH3_W::new(self, 3)
147    }
148}
149#[doc = "IntBlock Status\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clearblock::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
150pub struct CLEARBLOCK_SPEC;
151impl crate::RegisterSpec for CLEARBLOCK_SPEC {
152    type Ux = u32;
153}
154#[doc = "`write(|w| ..)` method takes [`clearblock::W`](W) writer structure"]
155impl crate::Writable for CLEARBLOCK_SPEC {
156    type Safety = crate::Unsafe;
157    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
158    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
159}
160#[doc = "`reset()` method sets CLEARBLOCK to value 0"]
161impl crate::Resettable for CLEARBLOCK_SPEC {
162    const RESET_VALUE: u32 = 0;
163}
xmc4500/gpdma1/clearblock.rs

xmc4500/gpdma1/
clearblock.rs
