1#[doc = "Register `STATUS` reader"]
2pub type R = crate::R<STATUS_SPEC>;
3#[doc = "Register `STATUS` writer"]
4pub type W = crate::W<STATUS_SPEC>;
5#[doc = "Field `TI` reader - Transmit Interrupt"]
6pub type TI_R = crate::BitReader;
7#[doc = "Field `TI` writer - Transmit Interrupt"]
8pub type TI_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TPS` reader - Transmit Process Stopped"]
10pub type TPS_R = crate::BitReader;
11#[doc = "Field `TPS` writer - Transmit Process Stopped"]
12pub type TPS_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TU` reader - Transmit Buffer Unavailable"]
14pub type TU_R = crate::BitReader;
15#[doc = "Field `TU` writer - Transmit Buffer Unavailable"]
16pub type TU_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TJT` reader - Transmit Jabber Timeout"]
18pub type TJT_R = crate::BitReader;
19#[doc = "Field `TJT` writer - Transmit Jabber Timeout"]
20pub type TJT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `OVF` reader - Receive Overflow"]
22pub type OVF_R = crate::BitReader;
23#[doc = "Field `OVF` writer - Receive Overflow"]
24pub type OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `UNF` reader - Transmit Underflow"]
26pub type UNF_R = crate::BitReader;
27#[doc = "Field `UNF` writer - Transmit Underflow"]
28pub type UNF_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RI` reader - Receive Interrupt"]
30pub type RI_R = crate::BitReader;
31#[doc = "Field `RI` writer - Receive Interrupt"]
32pub type RI_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `RU` reader - Receive Buffer Unavailable"]
34pub type RU_R = crate::BitReader;
35#[doc = "Field `RU` writer - Receive Buffer Unavailable"]
36pub type RU_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `RPS` reader - Receive Process Stopped"]
38pub type RPS_R = crate::BitReader;
39#[doc = "Field `RPS` writer - Receive Process Stopped"]
40pub type RPS_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `RWT` reader - Receive Watchdog Timeout"]
42pub type RWT_R = crate::BitReader;
43#[doc = "Field `RWT` writer - Receive Watchdog Timeout"]
44pub type RWT_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `ETI` reader - Early Transmit Interrupt"]
46pub type ETI_R = crate::BitReader;
47#[doc = "Field `ETI` writer - Early Transmit Interrupt"]
48pub type ETI_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `FBI` reader - Fatal Bus Error Interrupt"]
50pub type FBI_R = crate::BitReader;
51#[doc = "Field `FBI` writer - Fatal Bus Error Interrupt"]
52pub type FBI_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `ERI` reader - Early Receive Interrupt"]
54pub type ERI_R = crate::BitReader;
55#[doc = "Field `ERI` writer - Early Receive Interrupt"]
56pub type ERI_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `AIS` reader - Abnormal Interrupt Summary"]
58pub type AIS_R = crate::BitReader;
59#[doc = "Field `AIS` writer - Abnormal Interrupt Summary"]
60pub type AIS_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `NIS` reader - Normal Interrupt Summary"]
62pub type NIS_R = crate::BitReader;
63#[doc = "Field `NIS` writer - Normal Interrupt Summary"]
64pub type NIS_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `RS` reader - Received Process State"]
66pub type RS_R = crate::FieldReader;
67#[doc = "Field `TS` reader - Transmit Process State"]
68pub type TS_R = crate::FieldReader;
69#[doc = "Field `EB` reader - Error Bits"]
70pub type EB_R = crate::FieldReader;
71#[doc = "Field `EMI` reader - ETH MMC Interrupt"]
72pub type EMI_R = crate::BitReader;
73#[doc = "Field `EPI` reader - ETH PMT Interrupt"]
74pub type EPI_R = crate::BitReader;
75#[doc = "Field `TTI` reader - Timestamp Trigger Interrupt"]
76pub type TTI_R = crate::BitReader;
77impl R {
78 #[doc = "Bit 0 - Transmit Interrupt"]
79 #[inline(always)]
80 pub fn ti(&self) -> TI_R {
81 TI_R::new((self.bits & 1) != 0)
82 }
83 #[doc = "Bit 1 - Transmit Process Stopped"]
84 #[inline(always)]
85 pub fn tps(&self) -> TPS_R {
86 TPS_R::new(((self.bits >> 1) & 1) != 0)
87 }
88 #[doc = "Bit 2 - Transmit Buffer Unavailable"]
89 #[inline(always)]
90 pub fn tu(&self) -> TU_R {
91 TU_R::new(((self.bits >> 2) & 1) != 0)
92 }
93 #[doc = "Bit 3 - Transmit Jabber Timeout"]
94 #[inline(always)]
95 pub fn tjt(&self) -> TJT_R {
96 TJT_R::new(((self.bits >> 3) & 1) != 0)
97 }
98 #[doc = "Bit 4 - Receive Overflow"]
99 #[inline(always)]
100 pub fn ovf(&self) -> OVF_R {
101 OVF_R::new(((self.bits >> 4) & 1) != 0)
102 }
103 #[doc = "Bit 5 - Transmit Underflow"]
104 #[inline(always)]
105 pub fn unf(&self) -> UNF_R {
106 UNF_R::new(((self.bits >> 5) & 1) != 0)
107 }
108 #[doc = "Bit 6 - Receive Interrupt"]
109 #[inline(always)]
110 pub fn ri(&self) -> RI_R {
111 RI_R::new(((self.bits >> 6) & 1) != 0)
112 }
113 #[doc = "Bit 7 - Receive Buffer Unavailable"]
114 #[inline(always)]
115 pub fn ru(&self) -> RU_R {
116 RU_R::new(((self.bits >> 7) & 1) != 0)
117 }
118 #[doc = "Bit 8 - Receive Process Stopped"]
119 #[inline(always)]
120 pub fn rps(&self) -> RPS_R {
121 RPS_R::new(((self.bits >> 8) & 1) != 0)
122 }
123 #[doc = "Bit 9 - Receive Watchdog Timeout"]
124 #[inline(always)]
125 pub fn rwt(&self) -> RWT_R {
126 RWT_R::new(((self.bits >> 9) & 1) != 0)
127 }
128 #[doc = "Bit 10 - Early Transmit Interrupt"]
129 #[inline(always)]
130 pub fn eti(&self) -> ETI_R {
131 ETI_R::new(((self.bits >> 10) & 1) != 0)
132 }
133 #[doc = "Bit 13 - Fatal Bus Error Interrupt"]
134 #[inline(always)]
135 pub fn fbi(&self) -> FBI_R {
136 FBI_R::new(((self.bits >> 13) & 1) != 0)
137 }
138 #[doc = "Bit 14 - Early Receive Interrupt"]
139 #[inline(always)]
140 pub fn eri(&self) -> ERI_R {
141 ERI_R::new(((self.bits >> 14) & 1) != 0)
142 }
143 #[doc = "Bit 15 - Abnormal Interrupt Summary"]
144 #[inline(always)]
145 pub fn ais(&self) -> AIS_R {
146 AIS_R::new(((self.bits >> 15) & 1) != 0)
147 }
148 #[doc = "Bit 16 - Normal Interrupt Summary"]
149 #[inline(always)]
150 pub fn nis(&self) -> NIS_R {
151 NIS_R::new(((self.bits >> 16) & 1) != 0)
152 }
153 #[doc = "Bits 17:19 - Received Process State"]
154 #[inline(always)]
155 pub fn rs(&self) -> RS_R {
156 RS_R::new(((self.bits >> 17) & 7) as u8)
157 }
158 #[doc = "Bits 20:22 - Transmit Process State"]
159 #[inline(always)]
160 pub fn ts(&self) -> TS_R {
161 TS_R::new(((self.bits >> 20) & 7) as u8)
162 }
163 #[doc = "Bits 23:25 - Error Bits"]
164 #[inline(always)]
165 pub fn eb(&self) -> EB_R {
166 EB_R::new(((self.bits >> 23) & 7) as u8)
167 }
168 #[doc = "Bit 27 - ETH MMC Interrupt"]
169 #[inline(always)]
170 pub fn emi(&self) -> EMI_R {
171 EMI_R::new(((self.bits >> 27) & 1) != 0)
172 }
173 #[doc = "Bit 28 - ETH PMT Interrupt"]
174 #[inline(always)]
175 pub fn epi(&self) -> EPI_R {
176 EPI_R::new(((self.bits >> 28) & 1) != 0)
177 }
178 #[doc = "Bit 29 - Timestamp Trigger Interrupt"]
179 #[inline(always)]
180 pub fn tti(&self) -> TTI_R {
181 TTI_R::new(((self.bits >> 29) & 1) != 0)
182 }
183}
184impl W {
185 #[doc = "Bit 0 - Transmit Interrupt"]
186 #[inline(always)]
187 pub fn ti(&mut self) -> TI_W<STATUS_SPEC> {
188 TI_W::new(self, 0)
189 }
190 #[doc = "Bit 1 - Transmit Process Stopped"]
191 #[inline(always)]
192 pub fn tps(&mut self) -> TPS_W<STATUS_SPEC> {
193 TPS_W::new(self, 1)
194 }
195 #[doc = "Bit 2 - Transmit Buffer Unavailable"]
196 #[inline(always)]
197 pub fn tu(&mut self) -> TU_W<STATUS_SPEC> {
198 TU_W::new(self, 2)
199 }
200 #[doc = "Bit 3 - Transmit Jabber Timeout"]
201 #[inline(always)]
202 pub fn tjt(&mut self) -> TJT_W<STATUS_SPEC> {
203 TJT_W::new(self, 3)
204 }
205 #[doc = "Bit 4 - Receive Overflow"]
206 #[inline(always)]
207 pub fn ovf(&mut self) -> OVF_W<STATUS_SPEC> {
208 OVF_W::new(self, 4)
209 }
210 #[doc = "Bit 5 - Transmit Underflow"]
211 #[inline(always)]
212 pub fn unf(&mut self) -> UNF_W<STATUS_SPEC> {
213 UNF_W::new(self, 5)
214 }
215 #[doc = "Bit 6 - Receive Interrupt"]
216 #[inline(always)]
217 pub fn ri(&mut self) -> RI_W<STATUS_SPEC> {
218 RI_W::new(self, 6)
219 }
220 #[doc = "Bit 7 - Receive Buffer Unavailable"]
221 #[inline(always)]
222 pub fn ru(&mut self) -> RU_W<STATUS_SPEC> {
223 RU_W::new(self, 7)
224 }
225 #[doc = "Bit 8 - Receive Process Stopped"]
226 #[inline(always)]
227 pub fn rps(&mut self) -> RPS_W<STATUS_SPEC> {
228 RPS_W::new(self, 8)
229 }
230 #[doc = "Bit 9 - Receive Watchdog Timeout"]
231 #[inline(always)]
232 pub fn rwt(&mut self) -> RWT_W<STATUS_SPEC> {
233 RWT_W::new(self, 9)
234 }
235 #[doc = "Bit 10 - Early Transmit Interrupt"]
236 #[inline(always)]
237 pub fn eti(&mut self) -> ETI_W<STATUS_SPEC> {
238 ETI_W::new(self, 10)
239 }
240 #[doc = "Bit 13 - Fatal Bus Error Interrupt"]
241 #[inline(always)]
242 pub fn fbi(&mut self) -> FBI_W<STATUS_SPEC> {
243 FBI_W::new(self, 13)
244 }
245 #[doc = "Bit 14 - Early Receive Interrupt"]
246 #[inline(always)]
247 pub fn eri(&mut self) -> ERI_W<STATUS_SPEC> {
248 ERI_W::new(self, 14)
249 }
250 #[doc = "Bit 15 - Abnormal Interrupt Summary"]
251 #[inline(always)]
252 pub fn ais(&mut self) -> AIS_W<STATUS_SPEC> {
253 AIS_W::new(self, 15)
254 }
255 #[doc = "Bit 16 - Normal Interrupt Summary"]
256 #[inline(always)]
257 pub fn nis(&mut self) -> NIS_W<STATUS_SPEC> {
258 NIS_W::new(self, 16)
259 }
260}
261#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
262pub struct STATUS_SPEC;
263impl crate::RegisterSpec for STATUS_SPEC {
264 type Ux = u32;
265}
266#[doc = "`read()` method returns [`status::R`](R) reader structure"]
267impl crate::Readable for STATUS_SPEC {}
268#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
269impl crate::Writable for STATUS_SPEC {
270 type Safety = crate::Unsafe;
271 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
272 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
273}
274#[doc = "`reset()` method sets STATUS to value 0"]
275impl crate::Resettable for STATUS_SPEC {
276 const RESET_VALUE: u32 = 0;
277}