xmc4500/eth0/
receive_interrupt_watchdog_timer.rs

1#[doc = "Register `RECEIVE_INTERRUPT_WATCHDOG_TIMER` reader"]
2pub type R = crate::R<RECEIVE_INTERRUPT_WATCHDOG_TIMER_SPEC>;
3#[doc = "Register `RECEIVE_INTERRUPT_WATCHDOG_TIMER` writer"]
4pub type W = crate::W<RECEIVE_INTERRUPT_WATCHDOG_TIMER_SPEC>;
5#[doc = "Field `RIWT` reader - RI Watchdog Timer Count"]
6pub type RIWT_R = crate::FieldReader;
7#[doc = "Field `RIWT` writer - RI Watchdog Timer Count"]
8pub type RIWT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9impl R {
10    #[doc = "Bits 0:7 - RI Watchdog Timer Count"]
11    #[inline(always)]
12    pub fn riwt(&self) -> RIWT_R {
13        RIWT_R::new((self.bits & 0xff) as u8)
14    }
15}
16impl W {
17    #[doc = "Bits 0:7 - RI Watchdog Timer Count"]
18    #[inline(always)]
19    pub fn riwt(&mut self) -> RIWT_W<RECEIVE_INTERRUPT_WATCHDOG_TIMER_SPEC> {
20        RIWT_W::new(self, 0)
21    }
22}
23#[doc = "Receive Interrupt Watchdog Timer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`receive_interrupt_watchdog_timer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`receive_interrupt_watchdog_timer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24pub struct RECEIVE_INTERRUPT_WATCHDOG_TIMER_SPEC;
25impl crate::RegisterSpec for RECEIVE_INTERRUPT_WATCHDOG_TIMER_SPEC {
26    type Ux = u32;
27}
28#[doc = "`read()` method returns [`receive_interrupt_watchdog_timer::R`](R) reader structure"]
29impl crate::Readable for RECEIVE_INTERRUPT_WATCHDOG_TIMER_SPEC {}
30#[doc = "`write(|w| ..)` method takes [`receive_interrupt_watchdog_timer::W`](W) writer structure"]
31impl crate::Writable for RECEIVE_INTERRUPT_WATCHDOG_TIMER_SPEC {
32    type Safety = crate::Unsafe;
33    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
34    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
35}
36#[doc = "`reset()` method sets RECEIVE_INTERRUPT_WATCHDOG_TIMER to value 0"]
37impl crate::Resettable for RECEIVE_INTERRUPT_WATCHDOG_TIMER_SPEC {
38    const RESET_VALUE: u32 = 0;
39}
xmc4500/eth0/receive_interrupt_watchdog_timer.rs

xmc4500/eth0/
receive_interrupt_watchdog_timer.rs
