Type Alias xmc4400::usic0_ch0::pcr_sscmode::SLPHSEL_W

pub type SLPHSEL_W<'a, REG> = BitWriter<'a, REG, SLPHSEL_A>;

Field SLPHSEL writer - Slave Mode Clock Phase Select

Aliased Type

struct SLPHSEL_W<'a, REG> { /* private fields */ }

Implementations

impl<'a, REG> SLPHSEL_W<'a, REG>

where REG: Writable + RegisterSpec,

pub fn value1(self) -> &'a mut W<REG>

Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge.

pub fn value2(self) -> &'a mut W<REG>

The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2 stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are always latched in with the leading edge.