Enum xmc4400::usic0_ch0::pcr_sscmode::SLPHSEL_A
source · pub enum SLPHSEL_A {
VALUE1 = 0,
VALUE2 = 1,
}
Expand description
Slave Mode Clock Phase Select
Value on reset: 0
Variants§
VALUE1 = 0
0: Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge.
VALUE2 = 1
1: The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2 stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are always latched in with the leading edge.
Trait Implementations§
source§impl PartialEq for SLPHSEL_A
impl PartialEq for SLPHSEL_A
impl Copy for SLPHSEL_A
impl Eq for SLPHSEL_A
impl StructuralPartialEq for SLPHSEL_A
Auto Trait Implementations§
impl Freeze for SLPHSEL_A
impl RefUnwindSafe for SLPHSEL_A
impl Send for SLPHSEL_A
impl Sync for SLPHSEL_A
impl Unpin for SLPHSEL_A
impl UnwindSafe for SLPHSEL_A
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more