1#[doc = "Register `PDR0` reader"]
2pub type R = crate::R<PDR0_SPEC>;
3#[doc = "Register `PDR0` writer"]
4pub type W = crate::W<PDR0_SPEC>;
5#[doc = "Field `PD0` reader - Pad Driver Mode for Pn.0"]
6pub type PD0_R = crate::FieldReader;
7#[doc = "Field `PD0` writer - Pad Driver Mode for Pn.0"]
8pub type PD0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `PD1` reader - Pad Driver Mode for Pn.1"]
10pub type PD1_R = crate::FieldReader;
11#[doc = "Field `PD1` writer - Pad Driver Mode for Pn.1"]
12pub type PD1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `PD2` reader - Pad Driver Mode for Pn.2"]
14pub type PD2_R = crate::FieldReader;
15#[doc = "Field `PD2` writer - Pad Driver Mode for Pn.2"]
16pub type PD2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `PD3` reader - Pad Driver Mode for Pn.3"]
18pub type PD3_R = crate::FieldReader;
19#[doc = "Field `PD3` writer - Pad Driver Mode for Pn.3"]
20pub type PD3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `PD4` reader - Pad Driver Mode for Pn.4"]
22pub type PD4_R = crate::FieldReader;
23#[doc = "Field `PD4` writer - Pad Driver Mode for Pn.4"]
24pub type PD4_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
25#[doc = "Field `PD5` reader - Pad Driver Mode for Pn.5"]
26pub type PD5_R = crate::FieldReader;
27#[doc = "Field `PD5` writer - Pad Driver Mode for Pn.5"]
28pub type PD5_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29#[doc = "Field `PD6` reader - Pad Driver Mode for Pn.6"]
30pub type PD6_R = crate::FieldReader;
31#[doc = "Field `PD6` writer - Pad Driver Mode for Pn.6"]
32pub type PD6_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
33#[doc = "Field `PD7` reader - Pad Driver Mode for Pn.7"]
34pub type PD7_R = crate::FieldReader;
35#[doc = "Field `PD7` writer - Pad Driver Mode for Pn.7"]
36pub type PD7_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
37impl R {
38 #[doc = "Bits 0:2 - Pad Driver Mode for Pn.0"]
39 #[inline(always)]
40 pub fn pd0(&self) -> PD0_R {
41 PD0_R::new((self.bits & 7) as u8)
42 }
43 #[doc = "Bits 4:6 - Pad Driver Mode for Pn.1"]
44 #[inline(always)]
45 pub fn pd1(&self) -> PD1_R {
46 PD1_R::new(((self.bits >> 4) & 7) as u8)
47 }
48 #[doc = "Bits 8:10 - Pad Driver Mode for Pn.2"]
49 #[inline(always)]
50 pub fn pd2(&self) -> PD2_R {
51 PD2_R::new(((self.bits >> 8) & 7) as u8)
52 }
53 #[doc = "Bits 12:14 - Pad Driver Mode for Pn.3"]
54 #[inline(always)]
55 pub fn pd3(&self) -> PD3_R {
56 PD3_R::new(((self.bits >> 12) & 7) as u8)
57 }
58 #[doc = "Bits 16:18 - Pad Driver Mode for Pn.4"]
59 #[inline(always)]
60 pub fn pd4(&self) -> PD4_R {
61 PD4_R::new(((self.bits >> 16) & 7) as u8)
62 }
63 #[doc = "Bits 20:22 - Pad Driver Mode for Pn.5"]
64 #[inline(always)]
65 pub fn pd5(&self) -> PD5_R {
66 PD5_R::new(((self.bits >> 20) & 7) as u8)
67 }
68 #[doc = "Bits 24:26 - Pad Driver Mode for Pn.6"]
69 #[inline(always)]
70 pub fn pd6(&self) -> PD6_R {
71 PD6_R::new(((self.bits >> 24) & 7) as u8)
72 }
73 #[doc = "Bits 28:30 - Pad Driver Mode for Pn.7"]
74 #[inline(always)]
75 pub fn pd7(&self) -> PD7_R {
76 PD7_R::new(((self.bits >> 28) & 7) as u8)
77 }
78}
79impl W {
80 #[doc = "Bits 0:2 - Pad Driver Mode for Pn.0"]
81 #[inline(always)]
82 pub fn pd0(&mut self) -> PD0_W<PDR0_SPEC> {
83 PD0_W::new(self, 0)
84 }
85 #[doc = "Bits 4:6 - Pad Driver Mode for Pn.1"]
86 #[inline(always)]
87 pub fn pd1(&mut self) -> PD1_W<PDR0_SPEC> {
88 PD1_W::new(self, 4)
89 }
90 #[doc = "Bits 8:10 - Pad Driver Mode for Pn.2"]
91 #[inline(always)]
92 pub fn pd2(&mut self) -> PD2_W<PDR0_SPEC> {
93 PD2_W::new(self, 8)
94 }
95 #[doc = "Bits 12:14 - Pad Driver Mode for Pn.3"]
96 #[inline(always)]
97 pub fn pd3(&mut self) -> PD3_W<PDR0_SPEC> {
98 PD3_W::new(self, 12)
99 }
100 #[doc = "Bits 16:18 - Pad Driver Mode for Pn.4"]
101 #[inline(always)]
102 pub fn pd4(&mut self) -> PD4_W<PDR0_SPEC> {
103 PD4_W::new(self, 16)
104 }
105 #[doc = "Bits 20:22 - Pad Driver Mode for Pn.5"]
106 #[inline(always)]
107 pub fn pd5(&mut self) -> PD5_W<PDR0_SPEC> {
108 PD5_W::new(self, 20)
109 }
110 #[doc = "Bits 24:26 - Pad Driver Mode for Pn.6"]
111 #[inline(always)]
112 pub fn pd6(&mut self) -> PD6_W<PDR0_SPEC> {
113 PD6_W::new(self, 24)
114 }
115 #[doc = "Bits 28:30 - Pad Driver Mode for Pn.7"]
116 #[inline(always)]
117 pub fn pd7(&mut self) -> PD7_W<PDR0_SPEC> {
118 PD7_W::new(self, 28)
119 }
120}
121#[doc = "Port 4 Pad Driver Mode 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pdr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct PDR0_SPEC;
123impl crate::RegisterSpec for PDR0_SPEC {
124 type Ux = u32;
125}
126#[doc = "`read()` method returns [`pdr0::R`](R) reader structure"]
127impl crate::Readable for PDR0_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`pdr0::W`](W) writer structure"]
129impl crate::Writable for PDR0_SPEC {
130 type Safety = crate::Unsafe;
131 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
133}
134#[doc = "`reset()` method sets PDR0 to value 0x2222_2222"]
135impl crate::Resettable for PDR0_SPEC {
136 const RESET_VALUE: u32 = 0x2222_2222;
137}