xmc4400/
port0.rs

1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4    out: OUT,
5    omr: OMR,
6    _reserved2: [u8; 0x08],
7    iocr0: IOCR0,
8    iocr4: IOCR4,
9    iocr8: IOCR8,
10    iocr12: IOCR12,
11    _reserved6: [u8; 0x04],
12    in_: IN,
13    _reserved7: [u8; 0x18],
14    pdr0: PDR0,
15    pdr1: PDR1,
16    _reserved9: [u8; 0x18],
17    pdisc: PDISC,
18    _reserved10: [u8; 0x0c],
19    pps: PPS,
20    hwsel: HWSEL,
21}
22impl RegisterBlock {
23    #[doc = "0x00 - Port 0 Output Register"]
24    #[inline(always)]
25    pub const fn out(&self) -> &OUT {
26        &self.out
27    }
28    #[doc = "0x04 - Port 0 Output Modification Register"]
29    #[inline(always)]
30    pub const fn omr(&self) -> &OMR {
31        &self.omr
32    }
33    #[doc = "0x10 - Port 0 Input/Output Control Register 0"]
34    #[inline(always)]
35    pub const fn iocr0(&self) -> &IOCR0 {
36        &self.iocr0
37    }
38    #[doc = "0x14 - Port 0 Input/Output Control Register 4"]
39    #[inline(always)]
40    pub const fn iocr4(&self) -> &IOCR4 {
41        &self.iocr4
42    }
43    #[doc = "0x18 - Port 0 Input/Output Control Register 8"]
44    #[inline(always)]
45    pub const fn iocr8(&self) -> &IOCR8 {
46        &self.iocr8
47    }
48    #[doc = "0x1c - Port 0 Input/Output Control Register 12"]
49    #[inline(always)]
50    pub const fn iocr12(&self) -> &IOCR12 {
51        &self.iocr12
52    }
53    #[doc = "0x24 - Port 0 Input Register"]
54    #[inline(always)]
55    pub const fn in_(&self) -> &IN {
56        &self.in_
57    }
58    #[doc = "0x40 - Port 0 Pad Driver Mode 0 Register"]
59    #[inline(always)]
60    pub const fn pdr0(&self) -> &PDR0 {
61        &self.pdr0
62    }
63    #[doc = "0x44 - Port 0 Pad Driver Mode 1 Register"]
64    #[inline(always)]
65    pub const fn pdr1(&self) -> &PDR1 {
66        &self.pdr1
67    }
68    #[doc = "0x60 - Port 0 Pin Function Decision Control Register"]
69    #[inline(always)]
70    pub const fn pdisc(&self) -> &PDISC {
71        &self.pdisc
72    }
73    #[doc = "0x70 - Port 0 Pin Power Save Register"]
74    #[inline(always)]
75    pub const fn pps(&self) -> &PPS {
76        &self.pps
77    }
78    #[doc = "0x74 - Port 0 Pin Hardware Select Register"]
79    #[inline(always)]
80    pub const fn hwsel(&self) -> &HWSEL {
81        &self.hwsel
82    }
83}
84#[doc = "OUT (rw) register accessor: Port 0 Output Register\n\nYou can [`read`](crate::Reg::read) this register and get [`out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out`]
85module"]
86pub type OUT = crate::Reg<out::OUT_SPEC>;
87#[doc = "Port 0 Output Register"]
88pub mod out;
89#[doc = "OMR (w) register accessor: Port 0 Output Modification Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`omr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@omr`]
90module"]
91pub type OMR = crate::Reg<omr::OMR_SPEC>;
92#[doc = "Port 0 Output Modification Register"]
93pub mod omr;
94#[doc = "IOCR0 (rw) register accessor: Port 0 Input/Output Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`iocr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iocr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iocr0`]
95module"]
96pub type IOCR0 = crate::Reg<iocr0::IOCR0_SPEC>;
97#[doc = "Port 0 Input/Output Control Register 0"]
98pub mod iocr0;
99#[doc = "IOCR4 (rw) register accessor: Port 0 Input/Output Control Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`iocr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iocr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iocr4`]
100module"]
101pub type IOCR4 = crate::Reg<iocr4::IOCR4_SPEC>;
102#[doc = "Port 0 Input/Output Control Register 4"]
103pub mod iocr4;
104#[doc = "IOCR8 (rw) register accessor: Port 0 Input/Output Control Register 8\n\nYou can [`read`](crate::Reg::read) this register and get [`iocr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iocr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iocr8`]
105module"]
106pub type IOCR8 = crate::Reg<iocr8::IOCR8_SPEC>;
107#[doc = "Port 0 Input/Output Control Register 8"]
108pub mod iocr8;
109#[doc = "IOCR12 (rw) register accessor: Port 0 Input/Output Control Register 12\n\nYou can [`read`](crate::Reg::read) this register and get [`iocr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iocr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iocr12`]
110module"]
111pub type IOCR12 = crate::Reg<iocr12::IOCR12_SPEC>;
112#[doc = "Port 0 Input/Output Control Register 12"]
113pub mod iocr12;
114#[doc = "IN (r) register accessor: Port 0 Input Register\n\nYou can [`read`](crate::Reg::read) this register and get [`in_::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_`]
115module"]
116pub type IN = crate::Reg<in_::IN_SPEC>;
117#[doc = "Port 0 Input Register"]
118pub mod in_;
119#[doc = "PDR0 (rw) register accessor: Port 0 Pad Driver Mode 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pdr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdr0`]
120module"]
121pub type PDR0 = crate::Reg<pdr0::PDR0_SPEC>;
122#[doc = "Port 0 Pad Driver Mode 0 Register"]
123pub mod pdr0;
124#[doc = "PDR1 (rw) register accessor: Port 0 Pad Driver Mode 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pdr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdr1`]
125module"]
126pub type PDR1 = crate::Reg<pdr1::PDR1_SPEC>;
127#[doc = "Port 0 Pad Driver Mode 1 Register"]
128pub mod pdr1;
129#[doc = "PDISC (r) register accessor: Port 0 Pin Function Decision Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pdisc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdisc`]
130module"]
131pub type PDISC = crate::Reg<pdisc::PDISC_SPEC>;
132#[doc = "Port 0 Pin Function Decision Control Register"]
133pub mod pdisc;
134#[doc = "PPS (rw) register accessor: Port 0 Pin Power Save Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pps::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pps::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pps`]
135module"]
136pub type PPS = crate::Reg<pps::PPS_SPEC>;
137#[doc = "Port 0 Pin Power Save Register"]
138pub mod pps;
139#[doc = "HWSEL (rw) register accessor: Port 0 Pin Hardware Select Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hwsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwsel`]
140module"]
141pub type HWSEL = crate::Reg<hwsel::HWSEL_SPEC>;
142#[doc = "Port 0 Pin Hardware Select Register"]
143pub mod hwsel;