1#[doc = "Register `NCR` reader"]
2pub type R = crate::R<NCR_SPEC>;
3#[doc = "Register `NCR` writer"]
4pub type W = crate::W<NCR_SPEC>;
5#[doc = "Node Initialization\n\nValue on reset: 1"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum INIT_A {
8 #[doc = "0: Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus-off state, the ongoing bus-off recovery (which does not depend on the INIT bit) is continued. With the end of the bus-off recovery sequence the CAN node is allowed to take part in the CAN traffic. If the CAN node is not in the bus-off state, a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic."]
9 VALUE1 = 0,
10 #[doc = "1: Setting this bit terminates the participation of this node in the CAN traffic. Any ongoing frame transfer is cancelled and the transmit line goes recessive. If the CAN node is in the bus-off state, then the running bus-off recovery sequence is continued. If the INIT bit is still set after the successful completion of the bus-off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 1), then the CAN node leaves the bus-off state but remains inactive as long as INIT remains set."]
11 VALUE2 = 1,
12}
13impl From<INIT_A> for bool {
14 #[inline(always)]
15 fn from(variant: INIT_A) -> Self {
16 variant as u8 != 0
17 }
18}
19#[doc = "Field `INIT` reader - Node Initialization"]
20pub type INIT_R = crate::BitReader<INIT_A>;
21impl INIT_R {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> INIT_A {
25 match self.bits {
26 false => INIT_A::VALUE1,
27 true => INIT_A::VALUE2,
28 }
29 }
30 #[doc = "Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus-off state, the ongoing bus-off recovery (which does not depend on the INIT bit) is continued. With the end of the bus-off recovery sequence the CAN node is allowed to take part in the CAN traffic. If the CAN node is not in the bus-off state, a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic."]
31 #[inline(always)]
32 pub fn is_value1(&self) -> bool {
33 *self == INIT_A::VALUE1
34 }
35 #[doc = "Setting this bit terminates the participation of this node in the CAN traffic. Any ongoing frame transfer is cancelled and the transmit line goes recessive. If the CAN node is in the bus-off state, then the running bus-off recovery sequence is continued. If the INIT bit is still set after the successful completion of the bus-off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 1), then the CAN node leaves the bus-off state but remains inactive as long as INIT remains set."]
36 #[inline(always)]
37 pub fn is_value2(&self) -> bool {
38 *self == INIT_A::VALUE2
39 }
40}
41#[doc = "Field `INIT` writer - Node Initialization"]
42pub type INIT_W<'a, REG> = crate::BitWriter<'a, REG, INIT_A>;
43impl<'a, REG> INIT_W<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "Resetting bit INIT enables the participation of the node in the CAN traffic. If the CAN node is in the bus-off state, the ongoing bus-off recovery (which does not depend on the INIT bit) is continued. With the end of the bus-off recovery sequence the CAN node is allowed to take part in the CAN traffic. If the CAN node is not in the bus-off state, a sequence of 11 consecutive recessive bits must be detected before the node is allowed to take part in the CAN traffic."]
48 #[inline(always)]
49 pub fn value1(self) -> &'a mut crate::W<REG> {
50 self.variant(INIT_A::VALUE1)
51 }
52 #[doc = "Setting this bit terminates the participation of this node in the CAN traffic. Any ongoing frame transfer is cancelled and the transmit line goes recessive. If the CAN node is in the bus-off state, then the running bus-off recovery sequence is continued. If the INIT bit is still set after the successful completion of the bus-off recovery sequence, i.e. after detecting 128 sequences of 11 consecutive recessive bits (11 1), then the CAN node leaves the bus-off state but remains inactive as long as INIT remains set."]
53 #[inline(always)]
54 pub fn value2(self) -> &'a mut crate::W<REG> {
55 self.variant(INIT_A::VALUE2)
56 }
57}
58#[doc = "Transfer Interrupt Enable\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum TRIE_A {
61 #[doc = "0: Transfer interrupt is disabled."]
62 VALUE1 = 0,
63 #[doc = "1: Transfer interrupt is enabled."]
64 VALUE2 = 1,
65}
66impl From<TRIE_A> for bool {
67 #[inline(always)]
68 fn from(variant: TRIE_A) -> Self {
69 variant as u8 != 0
70 }
71}
72#[doc = "Field `TRIE` reader - Transfer Interrupt Enable"]
73pub type TRIE_R = crate::BitReader<TRIE_A>;
74impl TRIE_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub const fn variant(&self) -> TRIE_A {
78 match self.bits {
79 false => TRIE_A::VALUE1,
80 true => TRIE_A::VALUE2,
81 }
82 }
83 #[doc = "Transfer interrupt is disabled."]
84 #[inline(always)]
85 pub fn is_value1(&self) -> bool {
86 *self == TRIE_A::VALUE1
87 }
88 #[doc = "Transfer interrupt is enabled."]
89 #[inline(always)]
90 pub fn is_value2(&self) -> bool {
91 *self == TRIE_A::VALUE2
92 }
93}
94#[doc = "Field `TRIE` writer - Transfer Interrupt Enable"]
95pub type TRIE_W<'a, REG> = crate::BitWriter<'a, REG, TRIE_A>;
96impl<'a, REG> TRIE_W<'a, REG>
97where
98 REG: crate::Writable + crate::RegisterSpec,
99{
100 #[doc = "Transfer interrupt is disabled."]
101 #[inline(always)]
102 pub fn value1(self) -> &'a mut crate::W<REG> {
103 self.variant(TRIE_A::VALUE1)
104 }
105 #[doc = "Transfer interrupt is enabled."]
106 #[inline(always)]
107 pub fn value2(self) -> &'a mut crate::W<REG> {
108 self.variant(TRIE_A::VALUE2)
109 }
110}
111#[doc = "LEC Indicated Error Interrupt Enable\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum LECIE_A {
114 #[doc = "0: Last error code interrupt is disabled."]
115 VALUE1 = 0,
116 #[doc = "1: Last error code interrupt is enabled."]
117 VALUE2 = 1,
118}
119impl From<LECIE_A> for bool {
120 #[inline(always)]
121 fn from(variant: LECIE_A) -> Self {
122 variant as u8 != 0
123 }
124}
125#[doc = "Field `LECIE` reader - LEC Indicated Error Interrupt Enable"]
126pub type LECIE_R = crate::BitReader<LECIE_A>;
127impl LECIE_R {
128 #[doc = "Get enumerated values variant"]
129 #[inline(always)]
130 pub const fn variant(&self) -> LECIE_A {
131 match self.bits {
132 false => LECIE_A::VALUE1,
133 true => LECIE_A::VALUE2,
134 }
135 }
136 #[doc = "Last error code interrupt is disabled."]
137 #[inline(always)]
138 pub fn is_value1(&self) -> bool {
139 *self == LECIE_A::VALUE1
140 }
141 #[doc = "Last error code interrupt is enabled."]
142 #[inline(always)]
143 pub fn is_value2(&self) -> bool {
144 *self == LECIE_A::VALUE2
145 }
146}
147#[doc = "Field `LECIE` writer - LEC Indicated Error Interrupt Enable"]
148pub type LECIE_W<'a, REG> = crate::BitWriter<'a, REG, LECIE_A>;
149impl<'a, REG> LECIE_W<'a, REG>
150where
151 REG: crate::Writable + crate::RegisterSpec,
152{
153 #[doc = "Last error code interrupt is disabled."]
154 #[inline(always)]
155 pub fn value1(self) -> &'a mut crate::W<REG> {
156 self.variant(LECIE_A::VALUE1)
157 }
158 #[doc = "Last error code interrupt is enabled."]
159 #[inline(always)]
160 pub fn value2(self) -> &'a mut crate::W<REG> {
161 self.variant(LECIE_A::VALUE2)
162 }
163}
164#[doc = "Alert Interrupt Enable\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum ALIE_A {
167 #[doc = "0: Alert interrupt is disabled."]
168 VALUE1 = 0,
169 #[doc = "1: Alert interrupt is enabled."]
170 VALUE2 = 1,
171}
172impl From<ALIE_A> for bool {
173 #[inline(always)]
174 fn from(variant: ALIE_A) -> Self {
175 variant as u8 != 0
176 }
177}
178#[doc = "Field `ALIE` reader - Alert Interrupt Enable"]
179pub type ALIE_R = crate::BitReader<ALIE_A>;
180impl ALIE_R {
181 #[doc = "Get enumerated values variant"]
182 #[inline(always)]
183 pub const fn variant(&self) -> ALIE_A {
184 match self.bits {
185 false => ALIE_A::VALUE1,
186 true => ALIE_A::VALUE2,
187 }
188 }
189 #[doc = "Alert interrupt is disabled."]
190 #[inline(always)]
191 pub fn is_value1(&self) -> bool {
192 *self == ALIE_A::VALUE1
193 }
194 #[doc = "Alert interrupt is enabled."]
195 #[inline(always)]
196 pub fn is_value2(&self) -> bool {
197 *self == ALIE_A::VALUE2
198 }
199}
200#[doc = "Field `ALIE` writer - Alert Interrupt Enable"]
201pub type ALIE_W<'a, REG> = crate::BitWriter<'a, REG, ALIE_A>;
202impl<'a, REG> ALIE_W<'a, REG>
203where
204 REG: crate::Writable + crate::RegisterSpec,
205{
206 #[doc = "Alert interrupt is disabled."]
207 #[inline(always)]
208 pub fn value1(self) -> &'a mut crate::W<REG> {
209 self.variant(ALIE_A::VALUE1)
210 }
211 #[doc = "Alert interrupt is enabled."]
212 #[inline(always)]
213 pub fn value2(self) -> &'a mut crate::W<REG> {
214 self.variant(ALIE_A::VALUE2)
215 }
216}
217#[doc = "Field `CANDIS` reader - CAN Disable"]
218pub type CANDIS_R = crate::BitReader;
219#[doc = "Field `CANDIS` writer - CAN Disable"]
220pub type CANDIS_W<'a, REG> = crate::BitWriter<'a, REG>;
221#[doc = "Configuration Change Enable\n\nValue on reset: 0"]
222#[derive(Clone, Copy, Debug, PartialEq, Eq)]
223pub enum CCE_A {
224 #[doc = "0: The Bit Timing Register, the Port Control Register, and the Error Counter Register may only be read. All attempts to modify them are ignored."]
225 VALUE1 = 0,
226 #[doc = "1: The Bit Timing Register, the Port Control Register, and the Error Counter Register may be read and written."]
227 VALUE2 = 1,
228}
229impl From<CCE_A> for bool {
230 #[inline(always)]
231 fn from(variant: CCE_A) -> Self {
232 variant as u8 != 0
233 }
234}
235#[doc = "Field `CCE` reader - Configuration Change Enable"]
236pub type CCE_R = crate::BitReader<CCE_A>;
237impl CCE_R {
238 #[doc = "Get enumerated values variant"]
239 #[inline(always)]
240 pub const fn variant(&self) -> CCE_A {
241 match self.bits {
242 false => CCE_A::VALUE1,
243 true => CCE_A::VALUE2,
244 }
245 }
246 #[doc = "The Bit Timing Register, the Port Control Register, and the Error Counter Register may only be read. All attempts to modify them are ignored."]
247 #[inline(always)]
248 pub fn is_value1(&self) -> bool {
249 *self == CCE_A::VALUE1
250 }
251 #[doc = "The Bit Timing Register, the Port Control Register, and the Error Counter Register may be read and written."]
252 #[inline(always)]
253 pub fn is_value2(&self) -> bool {
254 *self == CCE_A::VALUE2
255 }
256}
257#[doc = "Field `CCE` writer - Configuration Change Enable"]
258pub type CCE_W<'a, REG> = crate::BitWriter<'a, REG, CCE_A>;
259impl<'a, REG> CCE_W<'a, REG>
260where
261 REG: crate::Writable + crate::RegisterSpec,
262{
263 #[doc = "The Bit Timing Register, the Port Control Register, and the Error Counter Register may only be read. All attempts to modify them are ignored."]
264 #[inline(always)]
265 pub fn value1(self) -> &'a mut crate::W<REG> {
266 self.variant(CCE_A::VALUE1)
267 }
268 #[doc = "The Bit Timing Register, the Port Control Register, and the Error Counter Register may be read and written."]
269 #[inline(always)]
270 pub fn value2(self) -> &'a mut crate::W<REG> {
271 self.variant(CCE_A::VALUE2)
272 }
273}
274#[doc = "Field `CALM` reader - CAN Analyzer Mode"]
275pub type CALM_R = crate::BitReader;
276#[doc = "Field `CALM` writer - CAN Analyzer Mode"]
277pub type CALM_W<'a, REG> = crate::BitWriter<'a, REG>;
278#[doc = "Suspend Enable\n\nValue on reset: 0"]
279#[derive(Clone, Copy, Debug, PartialEq, Eq)]
280pub enum SUSEN_A {
281 #[doc = "0: An OCDS suspend trigger is ignored by the CAN node."]
282 VALUE1 = 0,
283 #[doc = "1: An OCDS suspend trigger disables the CAN node: As soon as the CAN node becomes bus-idle or bus-off, bit INIT is internally forced to 1 to disable the CAN node. The actual value of bit INIT remains unchanged."]
284 VALUE2 = 1,
285}
286impl From<SUSEN_A> for bool {
287 #[inline(always)]
288 fn from(variant: SUSEN_A) -> Self {
289 variant as u8 != 0
290 }
291}
292#[doc = "Field `SUSEN` reader - Suspend Enable"]
293pub type SUSEN_R = crate::BitReader<SUSEN_A>;
294impl SUSEN_R {
295 #[doc = "Get enumerated values variant"]
296 #[inline(always)]
297 pub const fn variant(&self) -> SUSEN_A {
298 match self.bits {
299 false => SUSEN_A::VALUE1,
300 true => SUSEN_A::VALUE2,
301 }
302 }
303 #[doc = "An OCDS suspend trigger is ignored by the CAN node."]
304 #[inline(always)]
305 pub fn is_value1(&self) -> bool {
306 *self == SUSEN_A::VALUE1
307 }
308 #[doc = "An OCDS suspend trigger disables the CAN node: As soon as the CAN node becomes bus-idle or bus-off, bit INIT is internally forced to 1 to disable the CAN node. The actual value of bit INIT remains unchanged."]
309 #[inline(always)]
310 pub fn is_value2(&self) -> bool {
311 *self == SUSEN_A::VALUE2
312 }
313}
314#[doc = "Field `SUSEN` writer - Suspend Enable"]
315pub type SUSEN_W<'a, REG> = crate::BitWriter<'a, REG, SUSEN_A>;
316impl<'a, REG> SUSEN_W<'a, REG>
317where
318 REG: crate::Writable + crate::RegisterSpec,
319{
320 #[doc = "An OCDS suspend trigger is ignored by the CAN node."]
321 #[inline(always)]
322 pub fn value1(self) -> &'a mut crate::W<REG> {
323 self.variant(SUSEN_A::VALUE1)
324 }
325 #[doc = "An OCDS suspend trigger disables the CAN node: As soon as the CAN node becomes bus-idle or bus-off, bit INIT is internally forced to 1 to disable the CAN node. The actual value of bit INIT remains unchanged."]
326 #[inline(always)]
327 pub fn value2(self) -> &'a mut crate::W<REG> {
328 self.variant(SUSEN_A::VALUE2)
329 }
330}
331impl R {
332 #[doc = "Bit 0 - Node Initialization"]
333 #[inline(always)]
334 pub fn init(&self) -> INIT_R {
335 INIT_R::new((self.bits & 1) != 0)
336 }
337 #[doc = "Bit 1 - Transfer Interrupt Enable"]
338 #[inline(always)]
339 pub fn trie(&self) -> TRIE_R {
340 TRIE_R::new(((self.bits >> 1) & 1) != 0)
341 }
342 #[doc = "Bit 2 - LEC Indicated Error Interrupt Enable"]
343 #[inline(always)]
344 pub fn lecie(&self) -> LECIE_R {
345 LECIE_R::new(((self.bits >> 2) & 1) != 0)
346 }
347 #[doc = "Bit 3 - Alert Interrupt Enable"]
348 #[inline(always)]
349 pub fn alie(&self) -> ALIE_R {
350 ALIE_R::new(((self.bits >> 3) & 1) != 0)
351 }
352 #[doc = "Bit 4 - CAN Disable"]
353 #[inline(always)]
354 pub fn candis(&self) -> CANDIS_R {
355 CANDIS_R::new(((self.bits >> 4) & 1) != 0)
356 }
357 #[doc = "Bit 6 - Configuration Change Enable"]
358 #[inline(always)]
359 pub fn cce(&self) -> CCE_R {
360 CCE_R::new(((self.bits >> 6) & 1) != 0)
361 }
362 #[doc = "Bit 7 - CAN Analyzer Mode"]
363 #[inline(always)]
364 pub fn calm(&self) -> CALM_R {
365 CALM_R::new(((self.bits >> 7) & 1) != 0)
366 }
367 #[doc = "Bit 8 - Suspend Enable"]
368 #[inline(always)]
369 pub fn susen(&self) -> SUSEN_R {
370 SUSEN_R::new(((self.bits >> 8) & 1) != 0)
371 }
372}
373impl W {
374 #[doc = "Bit 0 - Node Initialization"]
375 #[inline(always)]
376 pub fn init(&mut self) -> INIT_W<NCR_SPEC> {
377 INIT_W::new(self, 0)
378 }
379 #[doc = "Bit 1 - Transfer Interrupt Enable"]
380 #[inline(always)]
381 pub fn trie(&mut self) -> TRIE_W<NCR_SPEC> {
382 TRIE_W::new(self, 1)
383 }
384 #[doc = "Bit 2 - LEC Indicated Error Interrupt Enable"]
385 #[inline(always)]
386 pub fn lecie(&mut self) -> LECIE_W<NCR_SPEC> {
387 LECIE_W::new(self, 2)
388 }
389 #[doc = "Bit 3 - Alert Interrupt Enable"]
390 #[inline(always)]
391 pub fn alie(&mut self) -> ALIE_W<NCR_SPEC> {
392 ALIE_W::new(self, 3)
393 }
394 #[doc = "Bit 4 - CAN Disable"]
395 #[inline(always)]
396 pub fn candis(&mut self) -> CANDIS_W<NCR_SPEC> {
397 CANDIS_W::new(self, 4)
398 }
399 #[doc = "Bit 6 - Configuration Change Enable"]
400 #[inline(always)]
401 pub fn cce(&mut self) -> CCE_W<NCR_SPEC> {
402 CCE_W::new(self, 6)
403 }
404 #[doc = "Bit 7 - CAN Analyzer Mode"]
405 #[inline(always)]
406 pub fn calm(&mut self) -> CALM_W<NCR_SPEC> {
407 CALM_W::new(self, 7)
408 }
409 #[doc = "Bit 8 - Suspend Enable"]
410 #[inline(always)]
411 pub fn susen(&mut self) -> SUSEN_W<NCR_SPEC> {
412 SUSEN_W::new(self, 8)
413 }
414}
415#[doc = "Node Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ncr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ncr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
416pub struct NCR_SPEC;
417impl crate::RegisterSpec for NCR_SPEC {
418 type Ux = u32;
419}
420#[doc = "`read()` method returns [`ncr::R`](R) reader structure"]
421impl crate::Readable for NCR_SPEC {}
422#[doc = "`write(|w| ..)` method takes [`ncr::W`](W) writer structure"]
423impl crate::Writable for NCR_SPEC {
424 type Safety = crate::Unsafe;
425 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
426 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
427}
428#[doc = "`reset()` method sets NCR to value 0x01"]
429impl crate::Resettable for NCR_SPEC {
430 const RESET_VALUE: u32 = 0x01;
431}