xmc4400/ppb/
mpu_rasr.rs

1#[doc = "Register `MPU_RASR` reader"]
2pub type R = crate::R<MPU_RASR_SPEC>;
3#[doc = "Register `MPU_RASR` writer"]
4pub type W = crate::W<MPU_RASR_SPEC>;
5#[doc = "Field `ENABLE` reader - Region enable bit."]
6pub type ENABLE_R = crate::BitReader;
7#[doc = "Field `ENABLE` writer - Region enable bit."]
8pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SIZE` reader - MPU protection region size"]
10pub type SIZE_R = crate::FieldReader;
11#[doc = "Field `SIZE` writer - MPU protection region size"]
12pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Subregion disable bits\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum SRD_A {
17    #[doc = "0: corresponding sub-region is enabled"]
18    VALUE1 = 0,
19    #[doc = "1: corresponding sub-region is disabled"]
20    VALUE2 = 1,
21}
22impl From<SRD_A> for u8 {
23    #[inline(always)]
24    fn from(variant: SRD_A) -> Self {
25        variant as _
26    }
27}
28impl crate::FieldSpec for SRD_A {
29    type Ux = u8;
30}
31impl crate::IsEnum for SRD_A {}
32#[doc = "Field `SRD` reader - Subregion disable bits"]
33pub type SRD_R = crate::FieldReader<SRD_A>;
34impl SRD_R {
35    #[doc = "Get enumerated values variant"]
36    #[inline(always)]
37    pub const fn variant(&self) -> Option<SRD_A> {
38        match self.bits {
39            0 => Some(SRD_A::VALUE1),
40            1 => Some(SRD_A::VALUE2),
41            _ => None,
42        }
43    }
44    #[doc = "corresponding sub-region is enabled"]
45    #[inline(always)]
46    pub fn is_value1(&self) -> bool {
47        *self == SRD_A::VALUE1
48    }
49    #[doc = "corresponding sub-region is disabled"]
50    #[inline(always)]
51    pub fn is_value2(&self) -> bool {
52        *self == SRD_A::VALUE2
53    }
54}
55#[doc = "Field `SRD` writer - Subregion disable bits"]
56pub type SRD_W<'a, REG> = crate::FieldWriter<'a, REG, 8, SRD_A>;
57impl<'a, REG> SRD_W<'a, REG>
58where
59    REG: crate::Writable + crate::RegisterSpec,
60    REG::Ux: From<u8>,
61{
62    #[doc = "corresponding sub-region is enabled"]
63    #[inline(always)]
64    pub fn value1(self) -> &'a mut crate::W<REG> {
65        self.variant(SRD_A::VALUE1)
66    }
67    #[doc = "corresponding sub-region is disabled"]
68    #[inline(always)]
69    pub fn value2(self) -> &'a mut crate::W<REG> {
70        self.variant(SRD_A::VALUE2)
71    }
72}
73#[doc = "Field `B` reader - Memory access attribute"]
74pub type B_R = crate::BitReader;
75#[doc = "Field `B` writer - Memory access attribute"]
76pub type B_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `C` reader - Memory access attribute"]
78pub type C_R = crate::BitReader;
79#[doc = "Field `C` writer - Memory access attribute"]
80pub type C_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `S` reader - Shareable bit"]
82pub type S_R = crate::BitReader;
83#[doc = "Field `S` writer - Shareable bit"]
84pub type S_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `TEX` reader - Memory access attribute"]
86pub type TEX_R = crate::FieldReader;
87#[doc = "Field `TEX` writer - Memory access attribute"]
88pub type TEX_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
89#[doc = "Field `AP` reader - Access permission field"]
90pub type AP_R = crate::FieldReader;
91#[doc = "Field `AP` writer - Access permission field"]
92pub type AP_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
93#[doc = "Instruction access disable bit\n\nValue on reset: 0"]
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum XN_A {
96    #[doc = "0: instruction fetches enabled"]
97    VALUE1 = 0,
98    #[doc = "1: instruction fetches disabled."]
99    VALUE2 = 1,
100}
101impl From<XN_A> for bool {
102    #[inline(always)]
103    fn from(variant: XN_A) -> Self {
104        variant as u8 != 0
105    }
106}
107#[doc = "Field `XN` reader - Instruction access disable bit"]
108pub type XN_R = crate::BitReader<XN_A>;
109impl XN_R {
110    #[doc = "Get enumerated values variant"]
111    #[inline(always)]
112    pub const fn variant(&self) -> XN_A {
113        match self.bits {
114            false => XN_A::VALUE1,
115            true => XN_A::VALUE2,
116        }
117    }
118    #[doc = "instruction fetches enabled"]
119    #[inline(always)]
120    pub fn is_value1(&self) -> bool {
121        *self == XN_A::VALUE1
122    }
123    #[doc = "instruction fetches disabled."]
124    #[inline(always)]
125    pub fn is_value2(&self) -> bool {
126        *self == XN_A::VALUE2
127    }
128}
129#[doc = "Field `XN` writer - Instruction access disable bit"]
130pub type XN_W<'a, REG> = crate::BitWriter<'a, REG, XN_A>;
131impl<'a, REG> XN_W<'a, REG>
132where
133    REG: crate::Writable + crate::RegisterSpec,
134{
135    #[doc = "instruction fetches enabled"]
136    #[inline(always)]
137    pub fn value1(self) -> &'a mut crate::W<REG> {
138        self.variant(XN_A::VALUE1)
139    }
140    #[doc = "instruction fetches disabled."]
141    #[inline(always)]
142    pub fn value2(self) -> &'a mut crate::W<REG> {
143        self.variant(XN_A::VALUE2)
144    }
145}
146impl R {
147    #[doc = "Bit 0 - Region enable bit."]
148    #[inline(always)]
149    pub fn enable(&self) -> ENABLE_R {
150        ENABLE_R::new((self.bits & 1) != 0)
151    }
152    #[doc = "Bits 1:5 - MPU protection region size"]
153    #[inline(always)]
154    pub fn size(&self) -> SIZE_R {
155        SIZE_R::new(((self.bits >> 1) & 0x1f) as u8)
156    }
157    #[doc = "Bits 8:15 - Subregion disable bits"]
158    #[inline(always)]
159    pub fn srd(&self) -> SRD_R {
160        SRD_R::new(((self.bits >> 8) & 0xff) as u8)
161    }
162    #[doc = "Bit 16 - Memory access attribute"]
163    #[inline(always)]
164    pub fn b(&self) -> B_R {
165        B_R::new(((self.bits >> 16) & 1) != 0)
166    }
167    #[doc = "Bit 17 - Memory access attribute"]
168    #[inline(always)]
169    pub fn c(&self) -> C_R {
170        C_R::new(((self.bits >> 17) & 1) != 0)
171    }
172    #[doc = "Bit 18 - Shareable bit"]
173    #[inline(always)]
174    pub fn s(&self) -> S_R {
175        S_R::new(((self.bits >> 18) & 1) != 0)
176    }
177    #[doc = "Bits 19:21 - Memory access attribute"]
178    #[inline(always)]
179    pub fn tex(&self) -> TEX_R {
180        TEX_R::new(((self.bits >> 19) & 7) as u8)
181    }
182    #[doc = "Bits 24:26 - Access permission field"]
183    #[inline(always)]
184    pub fn ap(&self) -> AP_R {
185        AP_R::new(((self.bits >> 24) & 7) as u8)
186    }
187    #[doc = "Bit 28 - Instruction access disable bit"]
188    #[inline(always)]
189    pub fn xn(&self) -> XN_R {
190        XN_R::new(((self.bits >> 28) & 1) != 0)
191    }
192}
193impl W {
194    #[doc = "Bit 0 - Region enable bit."]
195    #[inline(always)]
196    pub fn enable(&mut self) -> ENABLE_W<MPU_RASR_SPEC> {
197        ENABLE_W::new(self, 0)
198    }
199    #[doc = "Bits 1:5 - MPU protection region size"]
200    #[inline(always)]
201    pub fn size(&mut self) -> SIZE_W<MPU_RASR_SPEC> {
202        SIZE_W::new(self, 1)
203    }
204    #[doc = "Bits 8:15 - Subregion disable bits"]
205    #[inline(always)]
206    pub fn srd(&mut self) -> SRD_W<MPU_RASR_SPEC> {
207        SRD_W::new(self, 8)
208    }
209    #[doc = "Bit 16 - Memory access attribute"]
210    #[inline(always)]
211    pub fn b(&mut self) -> B_W<MPU_RASR_SPEC> {
212        B_W::new(self, 16)
213    }
214    #[doc = "Bit 17 - Memory access attribute"]
215    #[inline(always)]
216    pub fn c(&mut self) -> C_W<MPU_RASR_SPEC> {
217        C_W::new(self, 17)
218    }
219    #[doc = "Bit 18 - Shareable bit"]
220    #[inline(always)]
221    pub fn s(&mut self) -> S_W<MPU_RASR_SPEC> {
222        S_W::new(self, 18)
223    }
224    #[doc = "Bits 19:21 - Memory access attribute"]
225    #[inline(always)]
226    pub fn tex(&mut self) -> TEX_W<MPU_RASR_SPEC> {
227        TEX_W::new(self, 19)
228    }
229    #[doc = "Bits 24:26 - Access permission field"]
230    #[inline(always)]
231    pub fn ap(&mut self) -> AP_W<MPU_RASR_SPEC> {
232        AP_W::new(self, 24)
233    }
234    #[doc = "Bit 28 - Instruction access disable bit"]
235    #[inline(always)]
236    pub fn xn(&mut self) -> XN_W<MPU_RASR_SPEC> {
237        XN_W::new(self, 28)
238    }
239}
240#[doc = "MPU Region Attribute and Size Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpu_rasr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rasr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
241pub struct MPU_RASR_SPEC;
242impl crate::RegisterSpec for MPU_RASR_SPEC {
243    type Ux = u32;
244}
245#[doc = "`read()` method returns [`mpu_rasr::R`](R) reader structure"]
246impl crate::Readable for MPU_RASR_SPEC {}
247#[doc = "`write(|w| ..)` method takes [`mpu_rasr::W`](W) writer structure"]
248impl crate::Writable for MPU_RASR_SPEC {
249    type Safety = crate::Unsafe;
250    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
251    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
252}
253#[doc = "`reset()` method sets MPU_RASR to value 0"]
254impl crate::Resettable for MPU_RASR_SPEC {
255    const RESET_VALUE: u32 = 0;
256}
xmc4400/ppb/mpu_rasr.rs

xmc4400/ppb/
mpu_rasr.rs
