1#[doc = "Register `CEFCLR` writer"]
2pub type W = crate::W<CEFCLR_SPEC>;
3#[doc = "Clear Channel Event for Channel 0\n\nValue on reset: 0"]
4#[derive(Clone, Copy, Debug, PartialEq, Eq)]
5pub enum CEV0_A {
6 #[doc = "0: No action"]
7 VALUE1 = 0,
8 #[doc = "1: Clear the channel event flag in GxCEFLAG"]
9 VALUE2 = 1,
10}
11impl From<CEV0_A> for bool {
12 #[inline(always)]
13 fn from(variant: CEV0_A) -> Self {
14 variant as u8 != 0
15 }
16}
17#[doc = "Field `CEV0` writer - Clear Channel Event for Channel 0"]
18pub type CEV0_W<'a, REG> = crate::BitWriter<'a, REG, CEV0_A>;
19impl<'a, REG> CEV0_W<'a, REG>
20where
21 REG: crate::Writable + crate::RegisterSpec,
22{
23 #[doc = "No action"]
24 #[inline(always)]
25 pub fn value1(self) -> &'a mut crate::W<REG> {
26 self.variant(CEV0_A::VALUE1)
27 }
28 #[doc = "Clear the channel event flag in GxCEFLAG"]
29 #[inline(always)]
30 pub fn value2(self) -> &'a mut crate::W<REG> {
31 self.variant(CEV0_A::VALUE2)
32 }
33}
34#[doc = "Clear Channel Event for Channel 1\n\nValue on reset: 0"]
35#[derive(Clone, Copy, Debug, PartialEq, Eq)]
36pub enum CEV1_A {
37 #[doc = "0: No action"]
38 VALUE1 = 0,
39 #[doc = "1: Clear the channel event flag in GxCEFLAG"]
40 VALUE2 = 1,
41}
42impl From<CEV1_A> for bool {
43 #[inline(always)]
44 fn from(variant: CEV1_A) -> Self {
45 variant as u8 != 0
46 }
47}
48#[doc = "Field `CEV1` writer - Clear Channel Event for Channel 1"]
49pub type CEV1_W<'a, REG> = crate::BitWriter<'a, REG, CEV1_A>;
50impl<'a, REG> CEV1_W<'a, REG>
51where
52 REG: crate::Writable + crate::RegisterSpec,
53{
54 #[doc = "No action"]
55 #[inline(always)]
56 pub fn value1(self) -> &'a mut crate::W<REG> {
57 self.variant(CEV1_A::VALUE1)
58 }
59 #[doc = "Clear the channel event flag in GxCEFLAG"]
60 #[inline(always)]
61 pub fn value2(self) -> &'a mut crate::W<REG> {
62 self.variant(CEV1_A::VALUE2)
63 }
64}
65#[doc = "Clear Channel Event for Channel 2\n\nValue on reset: 0"]
66#[derive(Clone, Copy, Debug, PartialEq, Eq)]
67pub enum CEV2_A {
68 #[doc = "0: No action"]
69 VALUE1 = 0,
70 #[doc = "1: Clear the channel event flag in GxCEFLAG"]
71 VALUE2 = 1,
72}
73impl From<CEV2_A> for bool {
74 #[inline(always)]
75 fn from(variant: CEV2_A) -> Self {
76 variant as u8 != 0
77 }
78}
79#[doc = "Field `CEV2` writer - Clear Channel Event for Channel 2"]
80pub type CEV2_W<'a, REG> = crate::BitWriter<'a, REG, CEV2_A>;
81impl<'a, REG> CEV2_W<'a, REG>
82where
83 REG: crate::Writable + crate::RegisterSpec,
84{
85 #[doc = "No action"]
86 #[inline(always)]
87 pub fn value1(self) -> &'a mut crate::W<REG> {
88 self.variant(CEV2_A::VALUE1)
89 }
90 #[doc = "Clear the channel event flag in GxCEFLAG"]
91 #[inline(always)]
92 pub fn value2(self) -> &'a mut crate::W<REG> {
93 self.variant(CEV2_A::VALUE2)
94 }
95}
96#[doc = "Clear Channel Event for Channel 3\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98pub enum CEV3_A {
99 #[doc = "0: No action"]
100 VALUE1 = 0,
101 #[doc = "1: Clear the channel event flag in GxCEFLAG"]
102 VALUE2 = 1,
103}
104impl From<CEV3_A> for bool {
105 #[inline(always)]
106 fn from(variant: CEV3_A) -> Self {
107 variant as u8 != 0
108 }
109}
110#[doc = "Field `CEV3` writer - Clear Channel Event for Channel 3"]
111pub type CEV3_W<'a, REG> = crate::BitWriter<'a, REG, CEV3_A>;
112impl<'a, REG> CEV3_W<'a, REG>
113where
114 REG: crate::Writable + crate::RegisterSpec,
115{
116 #[doc = "No action"]
117 #[inline(always)]
118 pub fn value1(self) -> &'a mut crate::W<REG> {
119 self.variant(CEV3_A::VALUE1)
120 }
121 #[doc = "Clear the channel event flag in GxCEFLAG"]
122 #[inline(always)]
123 pub fn value2(self) -> &'a mut crate::W<REG> {
124 self.variant(CEV3_A::VALUE2)
125 }
126}
127#[doc = "Clear Channel Event for Channel 4\n\nValue on reset: 0"]
128#[derive(Clone, Copy, Debug, PartialEq, Eq)]
129pub enum CEV4_A {
130 #[doc = "0: No action"]
131 VALUE1 = 0,
132 #[doc = "1: Clear the channel event flag in GxCEFLAG"]
133 VALUE2 = 1,
134}
135impl From<CEV4_A> for bool {
136 #[inline(always)]
137 fn from(variant: CEV4_A) -> Self {
138 variant as u8 != 0
139 }
140}
141#[doc = "Field `CEV4` writer - Clear Channel Event for Channel 4"]
142pub type CEV4_W<'a, REG> = crate::BitWriter<'a, REG, CEV4_A>;
143impl<'a, REG> CEV4_W<'a, REG>
144where
145 REG: crate::Writable + crate::RegisterSpec,
146{
147 #[doc = "No action"]
148 #[inline(always)]
149 pub fn value1(self) -> &'a mut crate::W<REG> {
150 self.variant(CEV4_A::VALUE1)
151 }
152 #[doc = "Clear the channel event flag in GxCEFLAG"]
153 #[inline(always)]
154 pub fn value2(self) -> &'a mut crate::W<REG> {
155 self.variant(CEV4_A::VALUE2)
156 }
157}
158#[doc = "Clear Channel Event for Channel 5\n\nValue on reset: 0"]
159#[derive(Clone, Copy, Debug, PartialEq, Eq)]
160pub enum CEV5_A {
161 #[doc = "0: No action"]
162 VALUE1 = 0,
163 #[doc = "1: Clear the channel event flag in GxCEFLAG"]
164 VALUE2 = 1,
165}
166impl From<CEV5_A> for bool {
167 #[inline(always)]
168 fn from(variant: CEV5_A) -> Self {
169 variant as u8 != 0
170 }
171}
172#[doc = "Field `CEV5` writer - Clear Channel Event for Channel 5"]
173pub type CEV5_W<'a, REG> = crate::BitWriter<'a, REG, CEV5_A>;
174impl<'a, REG> CEV5_W<'a, REG>
175where
176 REG: crate::Writable + crate::RegisterSpec,
177{
178 #[doc = "No action"]
179 #[inline(always)]
180 pub fn value1(self) -> &'a mut crate::W<REG> {
181 self.variant(CEV5_A::VALUE1)
182 }
183 #[doc = "Clear the channel event flag in GxCEFLAG"]
184 #[inline(always)]
185 pub fn value2(self) -> &'a mut crate::W<REG> {
186 self.variant(CEV5_A::VALUE2)
187 }
188}
189#[doc = "Clear Channel Event for Channel 6\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum CEV6_A {
192 #[doc = "0: No action"]
193 VALUE1 = 0,
194 #[doc = "1: Clear the channel event flag in GxCEFLAG"]
195 VALUE2 = 1,
196}
197impl From<CEV6_A> for bool {
198 #[inline(always)]
199 fn from(variant: CEV6_A) -> Self {
200 variant as u8 != 0
201 }
202}
203#[doc = "Field `CEV6` writer - Clear Channel Event for Channel 6"]
204pub type CEV6_W<'a, REG> = crate::BitWriter<'a, REG, CEV6_A>;
205impl<'a, REG> CEV6_W<'a, REG>
206where
207 REG: crate::Writable + crate::RegisterSpec,
208{
209 #[doc = "No action"]
210 #[inline(always)]
211 pub fn value1(self) -> &'a mut crate::W<REG> {
212 self.variant(CEV6_A::VALUE1)
213 }
214 #[doc = "Clear the channel event flag in GxCEFLAG"]
215 #[inline(always)]
216 pub fn value2(self) -> &'a mut crate::W<REG> {
217 self.variant(CEV6_A::VALUE2)
218 }
219}
220#[doc = "Clear Channel Event for Channel 7\n\nValue on reset: 0"]
221#[derive(Clone, Copy, Debug, PartialEq, Eq)]
222pub enum CEV7_A {
223 #[doc = "0: No action"]
224 VALUE1 = 0,
225 #[doc = "1: Clear the channel event flag in GxCEFLAG"]
226 VALUE2 = 1,
227}
228impl From<CEV7_A> for bool {
229 #[inline(always)]
230 fn from(variant: CEV7_A) -> Self {
231 variant as u8 != 0
232 }
233}
234#[doc = "Field `CEV7` writer - Clear Channel Event for Channel 7"]
235pub type CEV7_W<'a, REG> = crate::BitWriter<'a, REG, CEV7_A>;
236impl<'a, REG> CEV7_W<'a, REG>
237where
238 REG: crate::Writable + crate::RegisterSpec,
239{
240 #[doc = "No action"]
241 #[inline(always)]
242 pub fn value1(self) -> &'a mut crate::W<REG> {
243 self.variant(CEV7_A::VALUE1)
244 }
245 #[doc = "Clear the channel event flag in GxCEFLAG"]
246 #[inline(always)]
247 pub fn value2(self) -> &'a mut crate::W<REG> {
248 self.variant(CEV7_A::VALUE2)
249 }
250}
251impl W {
252 #[doc = "Bit 0 - Clear Channel Event for Channel 0"]
253 #[inline(always)]
254 pub fn cev0(&mut self) -> CEV0_W<CEFCLR_SPEC> {
255 CEV0_W::new(self, 0)
256 }
257 #[doc = "Bit 1 - Clear Channel Event for Channel 1"]
258 #[inline(always)]
259 pub fn cev1(&mut self) -> CEV1_W<CEFCLR_SPEC> {
260 CEV1_W::new(self, 1)
261 }
262 #[doc = "Bit 2 - Clear Channel Event for Channel 2"]
263 #[inline(always)]
264 pub fn cev2(&mut self) -> CEV2_W<CEFCLR_SPEC> {
265 CEV2_W::new(self, 2)
266 }
267 #[doc = "Bit 3 - Clear Channel Event for Channel 3"]
268 #[inline(always)]
269 pub fn cev3(&mut self) -> CEV3_W<CEFCLR_SPEC> {
270 CEV3_W::new(self, 3)
271 }
272 #[doc = "Bit 4 - Clear Channel Event for Channel 4"]
273 #[inline(always)]
274 pub fn cev4(&mut self) -> CEV4_W<CEFCLR_SPEC> {
275 CEV4_W::new(self, 4)
276 }
277 #[doc = "Bit 5 - Clear Channel Event for Channel 5"]
278 #[inline(always)]
279 pub fn cev5(&mut self) -> CEV5_W<CEFCLR_SPEC> {
280 CEV5_W::new(self, 5)
281 }
282 #[doc = "Bit 6 - Clear Channel Event for Channel 6"]
283 #[inline(always)]
284 pub fn cev6(&mut self) -> CEV6_W<CEFCLR_SPEC> {
285 CEV6_W::new(self, 6)
286 }
287 #[doc = "Bit 7 - Clear Channel Event for Channel 7"]
288 #[inline(always)]
289 pub fn cev7(&mut self) -> CEV7_W<CEFCLR_SPEC> {
290 CEV7_W::new(self, 7)
291 }
292}
293#[doc = "Channel Event Flag Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cefclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
294pub struct CEFCLR_SPEC;
295impl crate::RegisterSpec for CEFCLR_SPEC {
296 type Ux = u32;
297}
298#[doc = "`write(|w| ..)` method takes [`cefclr::W`](W) writer structure"]
299impl crate::Writable for CEFCLR_SPEC {
300 type Safety = crate::Unsafe;
301 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
302 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
303}
304#[doc = "`reset()` method sets CEFCLR to value 0"]
305impl crate::Resettable for CEFCLR_SPEC {
306 const RESET_VALUE: u32 = 0;
307}