1#[doc = "Register `CLC` reader"]
2pub type R = crate::R<CLC_SPEC>;
3#[doc = "Register `CLC` writer"]
4pub type W = crate::W<CLC_SPEC>;
5#[doc = "Module Disable Request Bit\n\nValue on reset: 1"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum DISR_A {
8 #[doc = "0: On request: enable the module clock"]
9 VALUE1 = 0,
10 #[doc = "1: Off request: stop the module clock"]
11 VALUE2 = 1,
12}
13impl From<DISR_A> for bool {
14 #[inline(always)]
15 fn from(variant: DISR_A) -> Self {
16 variant as u8 != 0
17 }
18}
19#[doc = "Field `DISR` reader - Module Disable Request Bit"]
20pub type DISR_R = crate::BitReader<DISR_A>;
21impl DISR_R {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> DISR_A {
25 match self.bits {
26 false => DISR_A::VALUE1,
27 true => DISR_A::VALUE2,
28 }
29 }
30 #[doc = "On request: enable the module clock"]
31 #[inline(always)]
32 pub fn is_value1(&self) -> bool {
33 *self == DISR_A::VALUE1
34 }
35 #[doc = "Off request: stop the module clock"]
36 #[inline(always)]
37 pub fn is_value2(&self) -> bool {
38 *self == DISR_A::VALUE2
39 }
40}
41#[doc = "Field `DISR` writer - Module Disable Request Bit"]
42pub type DISR_W<'a, REG> = crate::BitWriter<'a, REG, DISR_A>;
43impl<'a, REG> DISR_W<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "On request: enable the module clock"]
48 #[inline(always)]
49 pub fn value1(self) -> &'a mut crate::W<REG> {
50 self.variant(DISR_A::VALUE1)
51 }
52 #[doc = "Off request: stop the module clock"]
53 #[inline(always)]
54 pub fn value2(self) -> &'a mut crate::W<REG> {
55 self.variant(DISR_A::VALUE2)
56 }
57}
58#[doc = "Module Disable Status Bit\n\nValue on reset: 1"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum DISS_A {
61 #[doc = "0: Module clock is enabled"]
62 VALUE1 = 0,
63 #[doc = "1: Off: module is not clocked"]
64 VALUE2 = 1,
65}
66impl From<DISS_A> for bool {
67 #[inline(always)]
68 fn from(variant: DISS_A) -> Self {
69 variant as u8 != 0
70 }
71}
72#[doc = "Field `DISS` reader - Module Disable Status Bit"]
73pub type DISS_R = crate::BitReader<DISS_A>;
74impl DISS_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub const fn variant(&self) -> DISS_A {
78 match self.bits {
79 false => DISS_A::VALUE1,
80 true => DISS_A::VALUE2,
81 }
82 }
83 #[doc = "Module clock is enabled"]
84 #[inline(always)]
85 pub fn is_value1(&self) -> bool {
86 *self == DISS_A::VALUE1
87 }
88 #[doc = "Off: module is not clocked"]
89 #[inline(always)]
90 pub fn is_value2(&self) -> bool {
91 *self == DISS_A::VALUE2
92 }
93}
94#[doc = "Sleep Mode Enable Control\n\nValue on reset: 0"]
95#[derive(Clone, Copy, Debug, PartialEq, Eq)]
96pub enum EDIS_A {
97 #[doc = "0: Sleep mode request is enabled and functional"]
98 VALUE1 = 0,
99 #[doc = "1: Module disregards the sleep mode control signal"]
100 VALUE2 = 1,
101}
102impl From<EDIS_A> for bool {
103 #[inline(always)]
104 fn from(variant: EDIS_A) -> Self {
105 variant as u8 != 0
106 }
107}
108#[doc = "Field `EDIS` reader - Sleep Mode Enable Control"]
109pub type EDIS_R = crate::BitReader<EDIS_A>;
110impl EDIS_R {
111 #[doc = "Get enumerated values variant"]
112 #[inline(always)]
113 pub const fn variant(&self) -> EDIS_A {
114 match self.bits {
115 false => EDIS_A::VALUE1,
116 true => EDIS_A::VALUE2,
117 }
118 }
119 #[doc = "Sleep mode request is enabled and functional"]
120 #[inline(always)]
121 pub fn is_value1(&self) -> bool {
122 *self == EDIS_A::VALUE1
123 }
124 #[doc = "Module disregards the sleep mode control signal"]
125 #[inline(always)]
126 pub fn is_value2(&self) -> bool {
127 *self == EDIS_A::VALUE2
128 }
129}
130#[doc = "Field `EDIS` writer - Sleep Mode Enable Control"]
131pub type EDIS_W<'a, REG> = crate::BitWriter<'a, REG, EDIS_A>;
132impl<'a, REG> EDIS_W<'a, REG>
133where
134 REG: crate::Writable + crate::RegisterSpec,
135{
136 #[doc = "Sleep mode request is enabled and functional"]
137 #[inline(always)]
138 pub fn value1(self) -> &'a mut crate::W<REG> {
139 self.variant(EDIS_A::VALUE1)
140 }
141 #[doc = "Module disregards the sleep mode control signal"]
142 #[inline(always)]
143 pub fn value2(self) -> &'a mut crate::W<REG> {
144 self.variant(EDIS_A::VALUE2)
145 }
146}
147impl R {
148 #[doc = "Bit 0 - Module Disable Request Bit"]
149 #[inline(always)]
150 pub fn disr(&self) -> DISR_R {
151 DISR_R::new((self.bits & 1) != 0)
152 }
153 #[doc = "Bit 1 - Module Disable Status Bit"]
154 #[inline(always)]
155 pub fn diss(&self) -> DISS_R {
156 DISS_R::new(((self.bits >> 1) & 1) != 0)
157 }
158 #[doc = "Bit 3 - Sleep Mode Enable Control"]
159 #[inline(always)]
160 pub fn edis(&self) -> EDIS_R {
161 EDIS_R::new(((self.bits >> 3) & 1) != 0)
162 }
163}
164impl W {
165 #[doc = "Bit 0 - Module Disable Request Bit"]
166 #[inline(always)]
167 pub fn disr(&mut self) -> DISR_W<CLC_SPEC> {
168 DISR_W::new(self, 0)
169 }
170 #[doc = "Bit 3 - Sleep Mode Enable Control"]
171 #[inline(always)]
172 pub fn edis(&mut self) -> EDIS_W<CLC_SPEC> {
173 EDIS_W::new(self, 3)
174 }
175}
176#[doc = "Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
177pub struct CLC_SPEC;
178impl crate::RegisterSpec for CLC_SPEC {
179 type Ux = u32;
180}
181#[doc = "`read()` method returns [`clc::R`](R) reader structure"]
182impl crate::Readable for CLC_SPEC {}
183#[doc = "`write(|w| ..)` method takes [`clc::W`](W) writer structure"]
184impl crate::Writable for CLC_SPEC {
185 type Safety = crate::Unsafe;
186 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
187 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
188}
189#[doc = "`reset()` method sets CLC to value 0x03"]
190impl crate::Resettable for CLC_SPEC {
191 const RESET_VALUE: u32 = 0x03;
192}