xmc4400/ppb/
icsr.rs

1#[doc = "Register `ICSR` reader"]
2pub type R = crate::R<ICSR_SPEC>;
3#[doc = "Register `ICSR` writer"]
4pub type W = crate::W<ICSR_SPEC>;
5#[doc = "Active exception number\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u16)]
8pub enum VECTACTIVE_A {
9    #[doc = "0: Thread mode"]
10    VALUE1 = 0,
11}
12impl From<VECTACTIVE_A> for u16 {
13    #[inline(always)]
14    fn from(variant: VECTACTIVE_A) -> Self {
15        variant as _
16    }
17}
18impl crate::FieldSpec for VECTACTIVE_A {
19    type Ux = u16;
20}
21impl crate::IsEnum for VECTACTIVE_A {}
22#[doc = "Field `VECTACTIVE` reader - Active exception number"]
23pub type VECTACTIVE_R = crate::FieldReader<VECTACTIVE_A>;
24impl VECTACTIVE_R {
25    #[doc = "Get enumerated values variant"]
26    #[inline(always)]
27    pub const fn variant(&self) -> Option<VECTACTIVE_A> {
28        match self.bits {
29            0 => Some(VECTACTIVE_A::VALUE1),
30            _ => None,
31        }
32    }
33    #[doc = "Thread mode"]
34    #[inline(always)]
35    pub fn is_value1(&self) -> bool {
36        *self == VECTACTIVE_A::VALUE1
37    }
38}
39#[doc = "Return to Base\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum RETTOBASE_A {
42    #[doc = "0: there are preempted active exceptions to execute"]
43    VALUE1 = 0,
44    #[doc = "1: there are no active exceptions, or the currently-executing exception is the only active exception."]
45    VALUE2 = 1,
46}
47impl From<RETTOBASE_A> for bool {
48    #[inline(always)]
49    fn from(variant: RETTOBASE_A) -> Self {
50        variant as u8 != 0
51    }
52}
53#[doc = "Field `RETTOBASE` reader - Return to Base"]
54pub type RETTOBASE_R = crate::BitReader<RETTOBASE_A>;
55impl RETTOBASE_R {
56    #[doc = "Get enumerated values variant"]
57    #[inline(always)]
58    pub const fn variant(&self) -> RETTOBASE_A {
59        match self.bits {
60            false => RETTOBASE_A::VALUE1,
61            true => RETTOBASE_A::VALUE2,
62        }
63    }
64    #[doc = "there are preempted active exceptions to execute"]
65    #[inline(always)]
66    pub fn is_value1(&self) -> bool {
67        *self == RETTOBASE_A::VALUE1
68    }
69    #[doc = "there are no active exceptions, or the currently-executing exception is the only active exception."]
70    #[inline(always)]
71    pub fn is_value2(&self) -> bool {
72        *self == RETTOBASE_A::VALUE2
73    }
74}
75#[doc = "Vector Pending\n\nValue on reset: 0"]
76#[derive(Clone, Copy, Debug, PartialEq, Eq)]
77#[repr(u8)]
78pub enum VECTPENDING_A {
79    #[doc = "0: no pending exceptions"]
80    VALUE1 = 0,
81}
82impl From<VECTPENDING_A> for u8 {
83    #[inline(always)]
84    fn from(variant: VECTPENDING_A) -> Self {
85        variant as _
86    }
87}
88impl crate::FieldSpec for VECTPENDING_A {
89    type Ux = u8;
90}
91impl crate::IsEnum for VECTPENDING_A {}
92#[doc = "Field `VECTPENDING` reader - Vector Pending"]
93pub type VECTPENDING_R = crate::FieldReader<VECTPENDING_A>;
94impl VECTPENDING_R {
95    #[doc = "Get enumerated values variant"]
96    #[inline(always)]
97    pub const fn variant(&self) -> Option<VECTPENDING_A> {
98        match self.bits {
99            0 => Some(VECTPENDING_A::VALUE1),
100            _ => None,
101        }
102    }
103    #[doc = "no pending exceptions"]
104    #[inline(always)]
105    pub fn is_value1(&self) -> bool {
106        *self == VECTPENDING_A::VALUE1
107    }
108}
109#[doc = "Interrupt pending flag\n\nValue on reset: 0"]
110#[derive(Clone, Copy, Debug, PartialEq, Eq)]
111pub enum ISRPENDING_A {
112    #[doc = "0: interrupt not pending"]
113    VALUE1 = 0,
114    #[doc = "1: interrupt pending."]
115    VALUE2 = 1,
116}
117impl From<ISRPENDING_A> for bool {
118    #[inline(always)]
119    fn from(variant: ISRPENDING_A) -> Self {
120        variant as u8 != 0
121    }
122}
123#[doc = "Field `ISRPENDING` reader - Interrupt pending flag"]
124pub type ISRPENDING_R = crate::BitReader<ISRPENDING_A>;
125impl ISRPENDING_R {
126    #[doc = "Get enumerated values variant"]
127    #[inline(always)]
128    pub const fn variant(&self) -> ISRPENDING_A {
129        match self.bits {
130            false => ISRPENDING_A::VALUE1,
131            true => ISRPENDING_A::VALUE2,
132        }
133    }
134    #[doc = "interrupt not pending"]
135    #[inline(always)]
136    pub fn is_value1(&self) -> bool {
137        *self == ISRPENDING_A::VALUE1
138    }
139    #[doc = "interrupt pending."]
140    #[inline(always)]
141    pub fn is_value2(&self) -> bool {
142        *self == ISRPENDING_A::VALUE2
143    }
144}
145#[doc = "SysTick exception clear-pending bit\n\nValue on reset: 0"]
146#[derive(Clone, Copy, Debug, PartialEq, Eq)]
147pub enum PENDSTCLR_A {
148    #[doc = "0: no effect"]
149    VALUE1 = 0,
150    #[doc = "1: removes the pending state from the SysTick exception."]
151    VALUE2 = 1,
152}
153impl From<PENDSTCLR_A> for bool {
154    #[inline(always)]
155    fn from(variant: PENDSTCLR_A) -> Self {
156        variant as u8 != 0
157    }
158}
159#[doc = "Field `PENDSTCLR` writer - SysTick exception clear-pending bit"]
160pub type PENDSTCLR_W<'a, REG> = crate::BitWriter<'a, REG, PENDSTCLR_A>;
161impl<'a, REG> PENDSTCLR_W<'a, REG>
162where
163    REG: crate::Writable + crate::RegisterSpec,
164{
165    #[doc = "no effect"]
166    #[inline(always)]
167    pub fn value1(self) -> &'a mut crate::W<REG> {
168        self.variant(PENDSTCLR_A::VALUE1)
169    }
170    #[doc = "removes the pending state from the SysTick exception."]
171    #[inline(always)]
172    pub fn value2(self) -> &'a mut crate::W<REG> {
173        self.variant(PENDSTCLR_A::VALUE2)
174    }
175}
176#[doc = "SysTick exception set-pending bit\n\nValue on reset: 0"]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum PENDSTSET_A {
179    #[doc = "0: no effect"]
180    VALUE1 = 0,
181    #[doc = "1: changes SysTick exception state to pending."]
182    VALUE2 = 1,
183}
184impl From<PENDSTSET_A> for bool {
185    #[inline(always)]
186    fn from(variant: PENDSTSET_A) -> Self {
187        variant as u8 != 0
188    }
189}
190#[doc = "Field `PENDSTSET` reader - SysTick exception set-pending bit"]
191pub type PENDSTSET_R = crate::BitReader<PENDSTSET_A>;
192impl PENDSTSET_R {
193    #[doc = "Get enumerated values variant"]
194    #[inline(always)]
195    pub const fn variant(&self) -> PENDSTSET_A {
196        match self.bits {
197            false => PENDSTSET_A::VALUE1,
198            true => PENDSTSET_A::VALUE2,
199        }
200    }
201    #[doc = "no effect"]
202    #[inline(always)]
203    pub fn is_value1(&self) -> bool {
204        *self == PENDSTSET_A::VALUE1
205    }
206    #[doc = "changes SysTick exception state to pending."]
207    #[inline(always)]
208    pub fn is_value2(&self) -> bool {
209        *self == PENDSTSET_A::VALUE2
210    }
211}
212#[doc = "Field `PENDSTSET` writer - SysTick exception set-pending bit"]
213pub type PENDSTSET_W<'a, REG> = crate::BitWriter<'a, REG, PENDSTSET_A>;
214impl<'a, REG> PENDSTSET_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    #[doc = "no effect"]
219    #[inline(always)]
220    pub fn value1(self) -> &'a mut crate::W<REG> {
221        self.variant(PENDSTSET_A::VALUE1)
222    }
223    #[doc = "changes SysTick exception state to pending."]
224    #[inline(always)]
225    pub fn value2(self) -> &'a mut crate::W<REG> {
226        self.variant(PENDSTSET_A::VALUE2)
227    }
228}
229#[doc = "PendSV clear-pending bit\n\nValue on reset: 0"]
230#[derive(Clone, Copy, Debug, PartialEq, Eq)]
231pub enum PENDSVCLR_A {
232    #[doc = "0: no effect"]
233    VALUE1 = 0,
234    #[doc = "1: removes the pending state from the PendSV exception."]
235    VALUE2 = 1,
236}
237impl From<PENDSVCLR_A> for bool {
238    #[inline(always)]
239    fn from(variant: PENDSVCLR_A) -> Self {
240        variant as u8 != 0
241    }
242}
243#[doc = "Field `PENDSVCLR` writer - PendSV clear-pending bit"]
244pub type PENDSVCLR_W<'a, REG> = crate::BitWriter<'a, REG, PENDSVCLR_A>;
245impl<'a, REG> PENDSVCLR_W<'a, REG>
246where
247    REG: crate::Writable + crate::RegisterSpec,
248{
249    #[doc = "no effect"]
250    #[inline(always)]
251    pub fn value1(self) -> &'a mut crate::W<REG> {
252        self.variant(PENDSVCLR_A::VALUE1)
253    }
254    #[doc = "removes the pending state from the PendSV exception."]
255    #[inline(always)]
256    pub fn value2(self) -> &'a mut crate::W<REG> {
257        self.variant(PENDSVCLR_A::VALUE2)
258    }
259}
260#[doc = "Field `PENDSVSET` reader - PendSV set-pending bit: 0b0=no effect, 0b1=changes PendSV exception state to pending., 0b0=PendSV exception is not pending, 0b1=PendSV exception is pending.,"]
261pub type PENDSVSET_R = crate::BitReader;
262#[doc = "Field `PENDSVSET` writer - PendSV set-pending bit: 0b0=no effect, 0b1=changes PendSV exception state to pending., 0b0=PendSV exception is not pending, 0b1=PendSV exception is pending.,"]
263pub type PENDSVSET_W<'a, REG> = crate::BitWriter<'a, REG>;
264#[doc = "Field `NMIPENDSET` reader - NMI set-pending bit: 0b0=no effect, 0b1=changes NMI exception state to pending., 0b0=NMI exception is not pending, 0b1=NMI exception is pending.,"]
265pub type NMIPENDSET_R = crate::BitReader;
266#[doc = "Field `NMIPENDSET` writer - NMI set-pending bit: 0b0=no effect, 0b1=changes NMI exception state to pending., 0b0=NMI exception is not pending, 0b1=NMI exception is pending.,"]
267pub type NMIPENDSET_W<'a, REG> = crate::BitWriter<'a, REG>;
268impl R {
269    #[doc = "Bits 0:8 - Active exception number"]
270    #[inline(always)]
271    pub fn vectactive(&self) -> VECTACTIVE_R {
272        VECTACTIVE_R::new((self.bits & 0x01ff) as u16)
273    }
274    #[doc = "Bit 11 - Return to Base"]
275    #[inline(always)]
276    pub fn rettobase(&self) -> RETTOBASE_R {
277        RETTOBASE_R::new(((self.bits >> 11) & 1) != 0)
278    }
279    #[doc = "Bits 12:17 - Vector Pending"]
280    #[inline(always)]
281    pub fn vectpending(&self) -> VECTPENDING_R {
282        VECTPENDING_R::new(((self.bits >> 12) & 0x3f) as u8)
283    }
284    #[doc = "Bit 22 - Interrupt pending flag"]
285    #[inline(always)]
286    pub fn isrpending(&self) -> ISRPENDING_R {
287        ISRPENDING_R::new(((self.bits >> 22) & 1) != 0)
288    }
289    #[doc = "Bit 26 - SysTick exception set-pending bit"]
290    #[inline(always)]
291    pub fn pendstset(&self) -> PENDSTSET_R {
292        PENDSTSET_R::new(((self.bits >> 26) & 1) != 0)
293    }
294    #[doc = "Bit 28 - PendSV set-pending bit: 0b0=no effect, 0b1=changes PendSV exception state to pending., 0b0=PendSV exception is not pending, 0b1=PendSV exception is pending.,"]
295    #[inline(always)]
296    pub fn pendsvset(&self) -> PENDSVSET_R {
297        PENDSVSET_R::new(((self.bits >> 28) & 1) != 0)
298    }
299    #[doc = "Bit 31 - NMI set-pending bit: 0b0=no effect, 0b1=changes NMI exception state to pending., 0b0=NMI exception is not pending, 0b1=NMI exception is pending.,"]
300    #[inline(always)]
301    pub fn nmipendset(&self) -> NMIPENDSET_R {
302        NMIPENDSET_R::new(((self.bits >> 31) & 1) != 0)
303    }
304}
305impl W {
306    #[doc = "Bit 25 - SysTick exception clear-pending bit"]
307    #[inline(always)]
308    pub fn pendstclr(&mut self) -> PENDSTCLR_W<ICSR_SPEC> {
309        PENDSTCLR_W::new(self, 25)
310    }
311    #[doc = "Bit 26 - SysTick exception set-pending bit"]
312    #[inline(always)]
313    pub fn pendstset(&mut self) -> PENDSTSET_W<ICSR_SPEC> {
314        PENDSTSET_W::new(self, 26)
315    }
316    #[doc = "Bit 27 - PendSV clear-pending bit"]
317    #[inline(always)]
318    pub fn pendsvclr(&mut self) -> PENDSVCLR_W<ICSR_SPEC> {
319        PENDSVCLR_W::new(self, 27)
320    }
321    #[doc = "Bit 28 - PendSV set-pending bit: 0b0=no effect, 0b1=changes PendSV exception state to pending., 0b0=PendSV exception is not pending, 0b1=PendSV exception is pending.,"]
322    #[inline(always)]
323    pub fn pendsvset(&mut self) -> PENDSVSET_W<ICSR_SPEC> {
324        PENDSVSET_W::new(self, 28)
325    }
326    #[doc = "Bit 31 - NMI set-pending bit: 0b0=no effect, 0b1=changes NMI exception state to pending., 0b0=NMI exception is not pending, 0b1=NMI exception is pending.,"]
327    #[inline(always)]
328    pub fn nmipendset(&mut self) -> NMIPENDSET_W<ICSR_SPEC> {
329        NMIPENDSET_W::new(self, 31)
330    }
331}
332#[doc = "Interrupt Control and State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`icsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
333pub struct ICSR_SPEC;
334impl crate::RegisterSpec for ICSR_SPEC {
335    type Ux = u32;
336}
337#[doc = "`read()` method returns [`icsr::R`](R) reader structure"]
338impl crate::Readable for ICSR_SPEC {}
339#[doc = "`write(|w| ..)` method takes [`icsr::W`](W) writer structure"]
340impl crate::Writable for ICSR_SPEC {
341    type Safety = crate::Unsafe;
342    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
343    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
344}
345#[doc = "`reset()` method sets ICSR to value 0"]
346impl crate::Resettable for ICSR_SPEC {
347    const RESET_VALUE: u32 = 0;
348}
xmc4400/ppb/icsr.rs

xmc4400/ppb/
icsr.rs
