xmc4400/eth0/
hw_feature.rs1#[doc = "Register `HW_FEATURE` reader"]
2pub type R = crate::R<HW_FEATURE_SPEC>;
3#[doc = "Register `HW_FEATURE` writer"]
4pub type W = crate::W<HW_FEATURE_SPEC>;
5#[doc = "Field `MIISEL` reader - 10 or 100 Mbps support"]
6pub type MIISEL_R = crate::BitReader;
7#[doc = "Field `GMIISEL` reader - 1000 Mbps support"]
8pub type GMIISEL_R = crate::BitReader;
9#[doc = "Field `HDSEL` reader - Half-Duplex support"]
10pub type HDSEL_R = crate::BitReader;
11#[doc = "Field `EXTHASHEN` reader - Expanded DA Hash Filter"]
12pub type EXTHASHEN_R = crate::BitReader;
13#[doc = "Field `HASHSEL` reader - HASH Filter"]
14pub type HASHSEL_R = crate::BitReader;
15#[doc = "Field `ADDMACADRSEL` reader - Multiple MAC Address Registers"]
16pub type ADDMACADRSEL_R = crate::BitReader;
17#[doc = "Field `PCSSEL` reader - PCS registers (TBI, SGMII, or RTBI PHY interface)"]
18pub type PCSSEL_R = crate::BitReader;
19#[doc = "Field `L3L4FLTREN` reader - Layer 3 and Layer 4 Filter Feature"]
20pub type L3L4FLTREN_R = crate::BitReader;
21#[doc = "Field `SMASEL` reader - SMA (MDIO) Interface"]
22pub type SMASEL_R = crate::BitReader;
23#[doc = "Field `RWKSEL` reader - PMT Remote Wakeup"]
24pub type RWKSEL_R = crate::BitReader;
25#[doc = "Field `MGKSEL` reader - PMT Magic Packet"]
26pub type MGKSEL_R = crate::BitReader;
27#[doc = "Field `MMCSEL` reader - RMON Module"]
28pub type MMCSEL_R = crate::BitReader;
29#[doc = "Field `TSVER1SEL` reader - Only IEEE 1588-2002 Timestamp"]
30pub type TSVER1SEL_R = crate::BitReader;
31#[doc = "Field `TSVER2SEL` reader - IEEE 1588-2008 Advanced Timestamp"]
32pub type TSVER2SEL_R = crate::BitReader;
33#[doc = "Field `EEESEL` reader - Energy Efficient Ethernet"]
34pub type EEESEL_R = crate::BitReader;
35#[doc = "Field `AVSEL` reader - AV Feature"]
36pub type AVSEL_R = crate::BitReader;
37#[doc = "Field `TXCOESEL` reader - Checksum Offload in Tx"]
38pub type TXCOESEL_R = crate::BitReader;
39#[doc = "Field `RXTYP1COE` reader - IP Checksum Offload (Type 1) in Rx"]
40pub type RXTYP1COE_R = crate::BitReader;
41#[doc = "Field `RXTYP2COE` reader - IP Checksum Offload (Type 2) in Rx"]
42pub type RXTYP2COE_R = crate::BitReader;
43#[doc = "Field `RXFIFOSIZE` reader - Rx FIFO > 2,048 Bytes"]
44pub type RXFIFOSIZE_R = crate::BitReader;
45#[doc = "Field `RXFIFOSIZE` writer - Rx FIFO > 2,048 Bytes"]
46pub type RXFIFOSIZE_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `RXCHCNT` reader - Number of additional Rx channels"]
48pub type RXCHCNT_R = crate::FieldReader;
49#[doc = "Field `TXCHCNT` reader - Number of additional Tx channels"]
50pub type TXCHCNT_R = crate::FieldReader;
51#[doc = "Field `ENHDESSEL` reader - Alternate (Enhanced Descriptor)"]
52pub type ENHDESSEL_R = crate::BitReader;
53#[doc = "Field `INTTSEN` reader - Timestamping with Internal System Time"]
54pub type INTTSEN_R = crate::BitReader;
55#[doc = "Field `FLEXIPPSEN` reader - Flexible Pulse-Per-Second Output"]
56pub type FLEXIPPSEN_R = crate::BitReader;
57#[doc = "Field `SAVLANINS` reader - Source Address or VLAN Insertion"]
58pub type SAVLANINS_R = crate::BitReader;
59#[doc = "Field `ACTPHYIF` reader - Active or Selected PHY interface"]
60pub type ACTPHYIF_R = crate::FieldReader;
61impl R {
62 #[doc = "Bit 0 - 10 or 100 Mbps support"]
63 #[inline(always)]
64 pub fn miisel(&self) -> MIISEL_R {
65 MIISEL_R::new((self.bits & 1) != 0)
66 }
67 #[doc = "Bit 1 - 1000 Mbps support"]
68 #[inline(always)]
69 pub fn gmiisel(&self) -> GMIISEL_R {
70 GMIISEL_R::new(((self.bits >> 1) & 1) != 0)
71 }
72 #[doc = "Bit 2 - Half-Duplex support"]
73 #[inline(always)]
74 pub fn hdsel(&self) -> HDSEL_R {
75 HDSEL_R::new(((self.bits >> 2) & 1) != 0)
76 }
77 #[doc = "Bit 3 - Expanded DA Hash Filter"]
78 #[inline(always)]
79 pub fn exthashen(&self) -> EXTHASHEN_R {
80 EXTHASHEN_R::new(((self.bits >> 3) & 1) != 0)
81 }
82 #[doc = "Bit 4 - HASH Filter"]
83 #[inline(always)]
84 pub fn hashsel(&self) -> HASHSEL_R {
85 HASHSEL_R::new(((self.bits >> 4) & 1) != 0)
86 }
87 #[doc = "Bit 5 - Multiple MAC Address Registers"]
88 #[inline(always)]
89 pub fn addmacadrsel(&self) -> ADDMACADRSEL_R {
90 ADDMACADRSEL_R::new(((self.bits >> 5) & 1) != 0)
91 }
92 #[doc = "Bit 6 - PCS registers (TBI, SGMII, or RTBI PHY interface)"]
93 #[inline(always)]
94 pub fn pcssel(&self) -> PCSSEL_R {
95 PCSSEL_R::new(((self.bits >> 6) & 1) != 0)
96 }
97 #[doc = "Bit 7 - Layer 3 and Layer 4 Filter Feature"]
98 #[inline(always)]
99 pub fn l3l4fltren(&self) -> L3L4FLTREN_R {
100 L3L4FLTREN_R::new(((self.bits >> 7) & 1) != 0)
101 }
102 #[doc = "Bit 8 - SMA (MDIO) Interface"]
103 #[inline(always)]
104 pub fn smasel(&self) -> SMASEL_R {
105 SMASEL_R::new(((self.bits >> 8) & 1) != 0)
106 }
107 #[doc = "Bit 9 - PMT Remote Wakeup"]
108 #[inline(always)]
109 pub fn rwksel(&self) -> RWKSEL_R {
110 RWKSEL_R::new(((self.bits >> 9) & 1) != 0)
111 }
112 #[doc = "Bit 10 - PMT Magic Packet"]
113 #[inline(always)]
114 pub fn mgksel(&self) -> MGKSEL_R {
115 MGKSEL_R::new(((self.bits >> 10) & 1) != 0)
116 }
117 #[doc = "Bit 11 - RMON Module"]
118 #[inline(always)]
119 pub fn mmcsel(&self) -> MMCSEL_R {
120 MMCSEL_R::new(((self.bits >> 11) & 1) != 0)
121 }
122 #[doc = "Bit 12 - Only IEEE 1588-2002 Timestamp"]
123 #[inline(always)]
124 pub fn tsver1sel(&self) -> TSVER1SEL_R {
125 TSVER1SEL_R::new(((self.bits >> 12) & 1) != 0)
126 }
127 #[doc = "Bit 13 - IEEE 1588-2008 Advanced Timestamp"]
128 #[inline(always)]
129 pub fn tsver2sel(&self) -> TSVER2SEL_R {
130 TSVER2SEL_R::new(((self.bits >> 13) & 1) != 0)
131 }
132 #[doc = "Bit 14 - Energy Efficient Ethernet"]
133 #[inline(always)]
134 pub fn eeesel(&self) -> EEESEL_R {
135 EEESEL_R::new(((self.bits >> 14) & 1) != 0)
136 }
137 #[doc = "Bit 15 - AV Feature"]
138 #[inline(always)]
139 pub fn avsel(&self) -> AVSEL_R {
140 AVSEL_R::new(((self.bits >> 15) & 1) != 0)
141 }
142 #[doc = "Bit 16 - Checksum Offload in Tx"]
143 #[inline(always)]
144 pub fn txcoesel(&self) -> TXCOESEL_R {
145 TXCOESEL_R::new(((self.bits >> 16) & 1) != 0)
146 }
147 #[doc = "Bit 17 - IP Checksum Offload (Type 1) in Rx"]
148 #[inline(always)]
149 pub fn rxtyp1coe(&self) -> RXTYP1COE_R {
150 RXTYP1COE_R::new(((self.bits >> 17) & 1) != 0)
151 }
152 #[doc = "Bit 18 - IP Checksum Offload (Type 2) in Rx"]
153 #[inline(always)]
154 pub fn rxtyp2coe(&self) -> RXTYP2COE_R {
155 RXTYP2COE_R::new(((self.bits >> 18) & 1) != 0)
156 }
157 #[doc = "Bit 19 - Rx FIFO > 2,048 Bytes"]
158 #[inline(always)]
159 pub fn rxfifosize(&self) -> RXFIFOSIZE_R {
160 RXFIFOSIZE_R::new(((self.bits >> 19) & 1) != 0)
161 }
162 #[doc = "Bits 20:21 - Number of additional Rx channels"]
163 #[inline(always)]
164 pub fn rxchcnt(&self) -> RXCHCNT_R {
165 RXCHCNT_R::new(((self.bits >> 20) & 3) as u8)
166 }
167 #[doc = "Bits 22:23 - Number of additional Tx channels"]
168 #[inline(always)]
169 pub fn txchcnt(&self) -> TXCHCNT_R {
170 TXCHCNT_R::new(((self.bits >> 22) & 3) as u8)
171 }
172 #[doc = "Bit 24 - Alternate (Enhanced Descriptor)"]
173 #[inline(always)]
174 pub fn enhdessel(&self) -> ENHDESSEL_R {
175 ENHDESSEL_R::new(((self.bits >> 24) & 1) != 0)
176 }
177 #[doc = "Bit 25 - Timestamping with Internal System Time"]
178 #[inline(always)]
179 pub fn inttsen(&self) -> INTTSEN_R {
180 INTTSEN_R::new(((self.bits >> 25) & 1) != 0)
181 }
182 #[doc = "Bit 26 - Flexible Pulse-Per-Second Output"]
183 #[inline(always)]
184 pub fn flexippsen(&self) -> FLEXIPPSEN_R {
185 FLEXIPPSEN_R::new(((self.bits >> 26) & 1) != 0)
186 }
187 #[doc = "Bit 27 - Source Address or VLAN Insertion"]
188 #[inline(always)]
189 pub fn savlanins(&self) -> SAVLANINS_R {
190 SAVLANINS_R::new(((self.bits >> 27) & 1) != 0)
191 }
192 #[doc = "Bits 28:30 - Active or Selected PHY interface"]
193 #[inline(always)]
194 pub fn actphyif(&self) -> ACTPHYIF_R {
195 ACTPHYIF_R::new(((self.bits >> 28) & 7) as u8)
196 }
197}
198impl W {
199 #[doc = "Bit 19 - Rx FIFO > 2,048 Bytes"]
200 #[inline(always)]
201 pub fn rxfifosize(&mut self) -> RXFIFOSIZE_W<HW_FEATURE_SPEC> {
202 RXFIFOSIZE_W::new(self, 19)
203 }
204}
205#[doc = "HW Feature Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hw_feature::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hw_feature::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
206pub struct HW_FEATURE_SPEC;
207impl crate::RegisterSpec for HW_FEATURE_SPEC {
208 type Ux = u32;
209}
210#[doc = "`read()` method returns [`hw_feature::R`](R) reader structure"]
211impl crate::Readable for HW_FEATURE_SPEC {}
212#[doc = "`write(|w| ..)` method takes [`hw_feature::W`](W) writer structure"]
213impl crate::Writable for HW_FEATURE_SPEC {
214 type Safety = crate::Unsafe;
215 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
216 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
217}
218#[doc = "`reset()` method sets HW_FEATURE to value 0x0305_2f35"]
219impl crate::Resettable for HW_FEATURE_SPEC {
220 const RESET_VALUE: u32 = 0x0305_2f35;
221}