1#[doc = "Register `GCTRL` reader"]
2pub type R = crate::R<GCTRL_SPEC>;
3#[doc = "Register `GCTRL` writer"]
4pub type W = crate::W<GCTRL_SPEC>;
5#[doc = "Prescaler Clear Configuration\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum PRBC_A {
9 #[doc = "0: SW only"]
10 VALUE1 = 0,
11 #[doc = "1: GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC40 is cleared."]
12 VALUE2 = 1,
13 #[doc = "2: GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC41 is cleared."]
14 VALUE3 = 2,
15 #[doc = "3: GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC42 is cleared."]
16 VALUE4 = 3,
17 #[doc = "4: GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC43 is cleared."]
18 VALUE5 = 4,
19}
20impl From<PRBC_A> for u8 {
21 #[inline(always)]
22 fn from(variant: PRBC_A) -> Self {
23 variant as _
24 }
25}
26impl crate::FieldSpec for PRBC_A {
27 type Ux = u8;
28}
29impl crate::IsEnum for PRBC_A {}
30#[doc = "Field `PRBC` reader - Prescaler Clear Configuration"]
31pub type PRBC_R = crate::FieldReader<PRBC_A>;
32impl PRBC_R {
33 #[doc = "Get enumerated values variant"]
34 #[inline(always)]
35 pub const fn variant(&self) -> Option<PRBC_A> {
36 match self.bits {
37 0 => Some(PRBC_A::VALUE1),
38 1 => Some(PRBC_A::VALUE2),
39 2 => Some(PRBC_A::VALUE3),
40 3 => Some(PRBC_A::VALUE4),
41 4 => Some(PRBC_A::VALUE5),
42 _ => None,
43 }
44 }
45 #[doc = "SW only"]
46 #[inline(always)]
47 pub fn is_value1(&self) -> bool {
48 *self == PRBC_A::VALUE1
49 }
50 #[doc = "GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC40 is cleared."]
51 #[inline(always)]
52 pub fn is_value2(&self) -> bool {
53 *self == PRBC_A::VALUE2
54 }
55 #[doc = "GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC41 is cleared."]
56 #[inline(always)]
57 pub fn is_value3(&self) -> bool {
58 *self == PRBC_A::VALUE3
59 }
60 #[doc = "GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC42 is cleared."]
61 #[inline(always)]
62 pub fn is_value4(&self) -> bool {
63 *self == PRBC_A::VALUE4
64 }
65 #[doc = "GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC43 is cleared."]
66 #[inline(always)]
67 pub fn is_value5(&self) -> bool {
68 *self == PRBC_A::VALUE5
69 }
70}
71#[doc = "Field `PRBC` writer - Prescaler Clear Configuration"]
72pub type PRBC_W<'a, REG> = crate::FieldWriter<'a, REG, 3, PRBC_A>;
73impl<'a, REG> PRBC_W<'a, REG>
74where
75 REG: crate::Writable + crate::RegisterSpec,
76 REG::Ux: From<u8>,
77{
78 #[doc = "SW only"]
79 #[inline(always)]
80 pub fn value1(self) -> &'a mut crate::W<REG> {
81 self.variant(PRBC_A::VALUE1)
82 }
83 #[doc = "GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC40 is cleared."]
84 #[inline(always)]
85 pub fn value2(self) -> &'a mut crate::W<REG> {
86 self.variant(PRBC_A::VALUE2)
87 }
88 #[doc = "GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC41 is cleared."]
89 #[inline(always)]
90 pub fn value3(self) -> &'a mut crate::W<REG> {
91 self.variant(PRBC_A::VALUE3)
92 }
93 #[doc = "GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC42 is cleared."]
94 #[inline(always)]
95 pub fn value4(self) -> &'a mut crate::W<REG> {
96 self.variant(PRBC_A::VALUE4)
97 }
98 #[doc = "GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC43 is cleared."]
99 #[inline(always)]
100 pub fn value5(self) -> &'a mut crate::W<REG> {
101 self.variant(PRBC_A::VALUE5)
102 }
103}
104#[doc = "Prescaler Input Clock Selection\n\nValue on reset: 0"]
105#[derive(Clone, Copy, Debug, PartialEq, Eq)]
106#[repr(u8)]
107pub enum PCIS_A {
108 #[doc = "0: Module clock"]
109 VALUE1 = 0,
110 #[doc = "1: CCU4x.ECLKA"]
111 VALUE2 = 1,
112 #[doc = "2: CCU4x.ECLKB"]
113 VALUE3 = 2,
114 #[doc = "3: CCU4x.ECLKC"]
115 VALUE4 = 3,
116}
117impl From<PCIS_A> for u8 {
118 #[inline(always)]
119 fn from(variant: PCIS_A) -> Self {
120 variant as _
121 }
122}
123impl crate::FieldSpec for PCIS_A {
124 type Ux = u8;
125}
126impl crate::IsEnum for PCIS_A {}
127#[doc = "Field `PCIS` reader - Prescaler Input Clock Selection"]
128pub type PCIS_R = crate::FieldReader<PCIS_A>;
129impl PCIS_R {
130 #[doc = "Get enumerated values variant"]
131 #[inline(always)]
132 pub const fn variant(&self) -> PCIS_A {
133 match self.bits {
134 0 => PCIS_A::VALUE1,
135 1 => PCIS_A::VALUE2,
136 2 => PCIS_A::VALUE3,
137 3 => PCIS_A::VALUE4,
138 _ => unreachable!(),
139 }
140 }
141 #[doc = "Module clock"]
142 #[inline(always)]
143 pub fn is_value1(&self) -> bool {
144 *self == PCIS_A::VALUE1
145 }
146 #[doc = "CCU4x.ECLKA"]
147 #[inline(always)]
148 pub fn is_value2(&self) -> bool {
149 *self == PCIS_A::VALUE2
150 }
151 #[doc = "CCU4x.ECLKB"]
152 #[inline(always)]
153 pub fn is_value3(&self) -> bool {
154 *self == PCIS_A::VALUE3
155 }
156 #[doc = "CCU4x.ECLKC"]
157 #[inline(always)]
158 pub fn is_value4(&self) -> bool {
159 *self == PCIS_A::VALUE4
160 }
161}
162#[doc = "Field `PCIS` writer - Prescaler Input Clock Selection"]
163pub type PCIS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PCIS_A, crate::Safe>;
164impl<'a, REG> PCIS_W<'a, REG>
165where
166 REG: crate::Writable + crate::RegisterSpec,
167 REG::Ux: From<u8>,
168{
169 #[doc = "Module clock"]
170 #[inline(always)]
171 pub fn value1(self) -> &'a mut crate::W<REG> {
172 self.variant(PCIS_A::VALUE1)
173 }
174 #[doc = "CCU4x.ECLKA"]
175 #[inline(always)]
176 pub fn value2(self) -> &'a mut crate::W<REG> {
177 self.variant(PCIS_A::VALUE2)
178 }
179 #[doc = "CCU4x.ECLKB"]
180 #[inline(always)]
181 pub fn value3(self) -> &'a mut crate::W<REG> {
182 self.variant(PCIS_A::VALUE3)
183 }
184 #[doc = "CCU4x.ECLKC"]
185 #[inline(always)]
186 pub fn value4(self) -> &'a mut crate::W<REG> {
187 self.variant(PCIS_A::VALUE4)
188 }
189}
190#[doc = "Suspend Mode Configuration\n\nValue on reset: 0"]
191#[derive(Clone, Copy, Debug, PartialEq, Eq)]
192#[repr(u8)]
193pub enum SUSCFG_A {
194 #[doc = "0: Suspend request ignored. The module never enters in suspend"]
195 VALUE1 = 0,
196 #[doc = "1: Stops all the running slices immediately. Safe stop is not applied."]
197 VALUE2 = 1,
198 #[doc = "2: Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied."]
199 VALUE3 = 2,
200 #[doc = "3: Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied."]
201 VALUE4 = 3,
202}
203impl From<SUSCFG_A> for u8 {
204 #[inline(always)]
205 fn from(variant: SUSCFG_A) -> Self {
206 variant as _
207 }
208}
209impl crate::FieldSpec for SUSCFG_A {
210 type Ux = u8;
211}
212impl crate::IsEnum for SUSCFG_A {}
213#[doc = "Field `SUSCFG` reader - Suspend Mode Configuration"]
214pub type SUSCFG_R = crate::FieldReader<SUSCFG_A>;
215impl SUSCFG_R {
216 #[doc = "Get enumerated values variant"]
217 #[inline(always)]
218 pub const fn variant(&self) -> SUSCFG_A {
219 match self.bits {
220 0 => SUSCFG_A::VALUE1,
221 1 => SUSCFG_A::VALUE2,
222 2 => SUSCFG_A::VALUE3,
223 3 => SUSCFG_A::VALUE4,
224 _ => unreachable!(),
225 }
226 }
227 #[doc = "Suspend request ignored. The module never enters in suspend"]
228 #[inline(always)]
229 pub fn is_value1(&self) -> bool {
230 *self == SUSCFG_A::VALUE1
231 }
232 #[doc = "Stops all the running slices immediately. Safe stop is not applied."]
233 #[inline(always)]
234 pub fn is_value2(&self) -> bool {
235 *self == SUSCFG_A::VALUE2
236 }
237 #[doc = "Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied."]
238 #[inline(always)]
239 pub fn is_value3(&self) -> bool {
240 *self == SUSCFG_A::VALUE3
241 }
242 #[doc = "Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied."]
243 #[inline(always)]
244 pub fn is_value4(&self) -> bool {
245 *self == SUSCFG_A::VALUE4
246 }
247}
248#[doc = "Field `SUSCFG` writer - Suspend Mode Configuration"]
249pub type SUSCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SUSCFG_A, crate::Safe>;
250impl<'a, REG> SUSCFG_W<'a, REG>
251where
252 REG: crate::Writable + crate::RegisterSpec,
253 REG::Ux: From<u8>,
254{
255 #[doc = "Suspend request ignored. The module never enters in suspend"]
256 #[inline(always)]
257 pub fn value1(self) -> &'a mut crate::W<REG> {
258 self.variant(SUSCFG_A::VALUE1)
259 }
260 #[doc = "Stops all the running slices immediately. Safe stop is not applied."]
261 #[inline(always)]
262 pub fn value2(self) -> &'a mut crate::W<REG> {
263 self.variant(SUSCFG_A::VALUE2)
264 }
265 #[doc = "Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied."]
266 #[inline(always)]
267 pub fn value3(self) -> &'a mut crate::W<REG> {
268 self.variant(SUSCFG_A::VALUE3)
269 }
270 #[doc = "Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied."]
271 #[inline(always)]
272 pub fn value4(self) -> &'a mut crate::W<REG> {
273 self.variant(SUSCFG_A::VALUE4)
274 }
275}
276#[doc = "Slice 0 Multi Channel shadow transfer enable\n\nValue on reset: 0"]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum MSE0_A {
279 #[doc = "0: Shadow transfer can only be requested by SW"]
280 VALUE1 = 0,
281 #[doc = "1: Shadow transfer can be requested via SW and via the CCU4x.MCSS input."]
282 VALUE2 = 1,
283}
284impl From<MSE0_A> for bool {
285 #[inline(always)]
286 fn from(variant: MSE0_A) -> Self {
287 variant as u8 != 0
288 }
289}
290#[doc = "Field `MSE0` reader - Slice 0 Multi Channel shadow transfer enable"]
291pub type MSE0_R = crate::BitReader<MSE0_A>;
292impl MSE0_R {
293 #[doc = "Get enumerated values variant"]
294 #[inline(always)]
295 pub const fn variant(&self) -> MSE0_A {
296 match self.bits {
297 false => MSE0_A::VALUE1,
298 true => MSE0_A::VALUE2,
299 }
300 }
301 #[doc = "Shadow transfer can only be requested by SW"]
302 #[inline(always)]
303 pub fn is_value1(&self) -> bool {
304 *self == MSE0_A::VALUE1
305 }
306 #[doc = "Shadow transfer can be requested via SW and via the CCU4x.MCSS input."]
307 #[inline(always)]
308 pub fn is_value2(&self) -> bool {
309 *self == MSE0_A::VALUE2
310 }
311}
312#[doc = "Field `MSE0` writer - Slice 0 Multi Channel shadow transfer enable"]
313pub type MSE0_W<'a, REG> = crate::BitWriter<'a, REG, MSE0_A>;
314impl<'a, REG> MSE0_W<'a, REG>
315where
316 REG: crate::Writable + crate::RegisterSpec,
317{
318 #[doc = "Shadow transfer can only be requested by SW"]
319 #[inline(always)]
320 pub fn value1(self) -> &'a mut crate::W<REG> {
321 self.variant(MSE0_A::VALUE1)
322 }
323 #[doc = "Shadow transfer can be requested via SW and via the CCU4x.MCSS input."]
324 #[inline(always)]
325 pub fn value2(self) -> &'a mut crate::W<REG> {
326 self.variant(MSE0_A::VALUE2)
327 }
328}
329#[doc = "Slice 1 Multi Channel shadow transfer enable\n\nValue on reset: 0"]
330#[derive(Clone, Copy, Debug, PartialEq, Eq)]
331pub enum MSE1_A {
332 #[doc = "0: Shadow transfer can only be requested by SW"]
333 VALUE1 = 0,
334 #[doc = "1: Shadow transfer can be requested via SW and via the CCU4x.MCSS input."]
335 VALUE2 = 1,
336}
337impl From<MSE1_A> for bool {
338 #[inline(always)]
339 fn from(variant: MSE1_A) -> Self {
340 variant as u8 != 0
341 }
342}
343#[doc = "Field `MSE1` reader - Slice 1 Multi Channel shadow transfer enable"]
344pub type MSE1_R = crate::BitReader<MSE1_A>;
345impl MSE1_R {
346 #[doc = "Get enumerated values variant"]
347 #[inline(always)]
348 pub const fn variant(&self) -> MSE1_A {
349 match self.bits {
350 false => MSE1_A::VALUE1,
351 true => MSE1_A::VALUE2,
352 }
353 }
354 #[doc = "Shadow transfer can only be requested by SW"]
355 #[inline(always)]
356 pub fn is_value1(&self) -> bool {
357 *self == MSE1_A::VALUE1
358 }
359 #[doc = "Shadow transfer can be requested via SW and via the CCU4x.MCSS input."]
360 #[inline(always)]
361 pub fn is_value2(&self) -> bool {
362 *self == MSE1_A::VALUE2
363 }
364}
365#[doc = "Field `MSE1` writer - Slice 1 Multi Channel shadow transfer enable"]
366pub type MSE1_W<'a, REG> = crate::BitWriter<'a, REG, MSE1_A>;
367impl<'a, REG> MSE1_W<'a, REG>
368where
369 REG: crate::Writable + crate::RegisterSpec,
370{
371 #[doc = "Shadow transfer can only be requested by SW"]
372 #[inline(always)]
373 pub fn value1(self) -> &'a mut crate::W<REG> {
374 self.variant(MSE1_A::VALUE1)
375 }
376 #[doc = "Shadow transfer can be requested via SW and via the CCU4x.MCSS input."]
377 #[inline(always)]
378 pub fn value2(self) -> &'a mut crate::W<REG> {
379 self.variant(MSE1_A::VALUE2)
380 }
381}
382#[doc = "Slice 2 Multi Channel shadow transfer enable\n\nValue on reset: 0"]
383#[derive(Clone, Copy, Debug, PartialEq, Eq)]
384pub enum MSE2_A {
385 #[doc = "0: Shadow transfer can only be requested by SW"]
386 VALUE1 = 0,
387 #[doc = "1: Shadow transfer can be requested via SW and via the CCU4x.MCSS input."]
388 VALUE2 = 1,
389}
390impl From<MSE2_A> for bool {
391 #[inline(always)]
392 fn from(variant: MSE2_A) -> Self {
393 variant as u8 != 0
394 }
395}
396#[doc = "Field `MSE2` reader - Slice 2 Multi Channel shadow transfer enable"]
397pub type MSE2_R = crate::BitReader<MSE2_A>;
398impl MSE2_R {
399 #[doc = "Get enumerated values variant"]
400 #[inline(always)]
401 pub const fn variant(&self) -> MSE2_A {
402 match self.bits {
403 false => MSE2_A::VALUE1,
404 true => MSE2_A::VALUE2,
405 }
406 }
407 #[doc = "Shadow transfer can only be requested by SW"]
408 #[inline(always)]
409 pub fn is_value1(&self) -> bool {
410 *self == MSE2_A::VALUE1
411 }
412 #[doc = "Shadow transfer can be requested via SW and via the CCU4x.MCSS input."]
413 #[inline(always)]
414 pub fn is_value2(&self) -> bool {
415 *self == MSE2_A::VALUE2
416 }
417}
418#[doc = "Field `MSE2` writer - Slice 2 Multi Channel shadow transfer enable"]
419pub type MSE2_W<'a, REG> = crate::BitWriter<'a, REG, MSE2_A>;
420impl<'a, REG> MSE2_W<'a, REG>
421where
422 REG: crate::Writable + crate::RegisterSpec,
423{
424 #[doc = "Shadow transfer can only be requested by SW"]
425 #[inline(always)]
426 pub fn value1(self) -> &'a mut crate::W<REG> {
427 self.variant(MSE2_A::VALUE1)
428 }
429 #[doc = "Shadow transfer can be requested via SW and via the CCU4x.MCSS input."]
430 #[inline(always)]
431 pub fn value2(self) -> &'a mut crate::W<REG> {
432 self.variant(MSE2_A::VALUE2)
433 }
434}
435#[doc = "Slice 3 Multi Channel shadow transfer enable\n\nValue on reset: 0"]
436#[derive(Clone, Copy, Debug, PartialEq, Eq)]
437pub enum MSE3_A {
438 #[doc = "0: Shadow transfer can only be requested by SW"]
439 VALUE1 = 0,
440 #[doc = "1: Shadow transfer can be requested via SW and via the CCU4x.MCSS input."]
441 VALUE2 = 1,
442}
443impl From<MSE3_A> for bool {
444 #[inline(always)]
445 fn from(variant: MSE3_A) -> Self {
446 variant as u8 != 0
447 }
448}
449#[doc = "Field `MSE3` reader - Slice 3 Multi Channel shadow transfer enable"]
450pub type MSE3_R = crate::BitReader<MSE3_A>;
451impl MSE3_R {
452 #[doc = "Get enumerated values variant"]
453 #[inline(always)]
454 pub const fn variant(&self) -> MSE3_A {
455 match self.bits {
456 false => MSE3_A::VALUE1,
457 true => MSE3_A::VALUE2,
458 }
459 }
460 #[doc = "Shadow transfer can only be requested by SW"]
461 #[inline(always)]
462 pub fn is_value1(&self) -> bool {
463 *self == MSE3_A::VALUE1
464 }
465 #[doc = "Shadow transfer can be requested via SW and via the CCU4x.MCSS input."]
466 #[inline(always)]
467 pub fn is_value2(&self) -> bool {
468 *self == MSE3_A::VALUE2
469 }
470}
471#[doc = "Field `MSE3` writer - Slice 3 Multi Channel shadow transfer enable"]
472pub type MSE3_W<'a, REG> = crate::BitWriter<'a, REG, MSE3_A>;
473impl<'a, REG> MSE3_W<'a, REG>
474where
475 REG: crate::Writable + crate::RegisterSpec,
476{
477 #[doc = "Shadow transfer can only be requested by SW"]
478 #[inline(always)]
479 pub fn value1(self) -> &'a mut crate::W<REG> {
480 self.variant(MSE3_A::VALUE1)
481 }
482 #[doc = "Shadow transfer can be requested via SW and via the CCU4x.MCSS input."]
483 #[inline(always)]
484 pub fn value2(self) -> &'a mut crate::W<REG> {
485 self.variant(MSE3_A::VALUE2)
486 }
487}
488#[doc = "Multi Channel shadow transfer request configuration\n\nValue on reset: 0"]
489#[derive(Clone, Copy, Debug, PartialEq, Eq)]
490#[repr(u8)]
491pub enum MSDE_A {
492 #[doc = "0: Only the shadow transfer for period and compare values is requested"]
493 VALUE1 = 0,
494 #[doc = "1: Shadow transfer for the compare, period and prescaler compare values is requested"]
495 VALUE2 = 1,
496 #[doc = "3: Shadow transfer for the compare, period, prescaler and dither compare values is requested"]
497 VALUE4 = 3,
498}
499impl From<MSDE_A> for u8 {
500 #[inline(always)]
501 fn from(variant: MSDE_A) -> Self {
502 variant as _
503 }
504}
505impl crate::FieldSpec for MSDE_A {
506 type Ux = u8;
507}
508impl crate::IsEnum for MSDE_A {}
509#[doc = "Field `MSDE` reader - Multi Channel shadow transfer request configuration"]
510pub type MSDE_R = crate::FieldReader<MSDE_A>;
511impl MSDE_R {
512 #[doc = "Get enumerated values variant"]
513 #[inline(always)]
514 pub const fn variant(&self) -> Option<MSDE_A> {
515 match self.bits {
516 0 => Some(MSDE_A::VALUE1),
517 1 => Some(MSDE_A::VALUE2),
518 3 => Some(MSDE_A::VALUE4),
519 _ => None,
520 }
521 }
522 #[doc = "Only the shadow transfer for period and compare values is requested"]
523 #[inline(always)]
524 pub fn is_value1(&self) -> bool {
525 *self == MSDE_A::VALUE1
526 }
527 #[doc = "Shadow transfer for the compare, period and prescaler compare values is requested"]
528 #[inline(always)]
529 pub fn is_value2(&self) -> bool {
530 *self == MSDE_A::VALUE2
531 }
532 #[doc = "Shadow transfer for the compare, period, prescaler and dither compare values is requested"]
533 #[inline(always)]
534 pub fn is_value4(&self) -> bool {
535 *self == MSDE_A::VALUE4
536 }
537}
538#[doc = "Field `MSDE` writer - Multi Channel shadow transfer request configuration"]
539pub type MSDE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, MSDE_A>;
540impl<'a, REG> MSDE_W<'a, REG>
541where
542 REG: crate::Writable + crate::RegisterSpec,
543 REG::Ux: From<u8>,
544{
545 #[doc = "Only the shadow transfer for period and compare values is requested"]
546 #[inline(always)]
547 pub fn value1(self) -> &'a mut crate::W<REG> {
548 self.variant(MSDE_A::VALUE1)
549 }
550 #[doc = "Shadow transfer for the compare, period and prescaler compare values is requested"]
551 #[inline(always)]
552 pub fn value2(self) -> &'a mut crate::W<REG> {
553 self.variant(MSDE_A::VALUE2)
554 }
555 #[doc = "Shadow transfer for the compare, period, prescaler and dither compare values is requested"]
556 #[inline(always)]
557 pub fn value4(self) -> &'a mut crate::W<REG> {
558 self.variant(MSDE_A::VALUE4)
559 }
560}
561impl R {
562 #[doc = "Bits 0:2 - Prescaler Clear Configuration"]
563 #[inline(always)]
564 pub fn prbc(&self) -> PRBC_R {
565 PRBC_R::new((self.bits & 7) as u8)
566 }
567 #[doc = "Bits 4:5 - Prescaler Input Clock Selection"]
568 #[inline(always)]
569 pub fn pcis(&self) -> PCIS_R {
570 PCIS_R::new(((self.bits >> 4) & 3) as u8)
571 }
572 #[doc = "Bits 8:9 - Suspend Mode Configuration"]
573 #[inline(always)]
574 pub fn suscfg(&self) -> SUSCFG_R {
575 SUSCFG_R::new(((self.bits >> 8) & 3) as u8)
576 }
577 #[doc = "Bit 10 - Slice 0 Multi Channel shadow transfer enable"]
578 #[inline(always)]
579 pub fn mse0(&self) -> MSE0_R {
580 MSE0_R::new(((self.bits >> 10) & 1) != 0)
581 }
582 #[doc = "Bit 11 - Slice 1 Multi Channel shadow transfer enable"]
583 #[inline(always)]
584 pub fn mse1(&self) -> MSE1_R {
585 MSE1_R::new(((self.bits >> 11) & 1) != 0)
586 }
587 #[doc = "Bit 12 - Slice 2 Multi Channel shadow transfer enable"]
588 #[inline(always)]
589 pub fn mse2(&self) -> MSE2_R {
590 MSE2_R::new(((self.bits >> 12) & 1) != 0)
591 }
592 #[doc = "Bit 13 - Slice 3 Multi Channel shadow transfer enable"]
593 #[inline(always)]
594 pub fn mse3(&self) -> MSE3_R {
595 MSE3_R::new(((self.bits >> 13) & 1) != 0)
596 }
597 #[doc = "Bits 14:15 - Multi Channel shadow transfer request configuration"]
598 #[inline(always)]
599 pub fn msde(&self) -> MSDE_R {
600 MSDE_R::new(((self.bits >> 14) & 3) as u8)
601 }
602}
603impl W {
604 #[doc = "Bits 0:2 - Prescaler Clear Configuration"]
605 #[inline(always)]
606 pub fn prbc(&mut self) -> PRBC_W<GCTRL_SPEC> {
607 PRBC_W::new(self, 0)
608 }
609 #[doc = "Bits 4:5 - Prescaler Input Clock Selection"]
610 #[inline(always)]
611 pub fn pcis(&mut self) -> PCIS_W<GCTRL_SPEC> {
612 PCIS_W::new(self, 4)
613 }
614 #[doc = "Bits 8:9 - Suspend Mode Configuration"]
615 #[inline(always)]
616 pub fn suscfg(&mut self) -> SUSCFG_W<GCTRL_SPEC> {
617 SUSCFG_W::new(self, 8)
618 }
619 #[doc = "Bit 10 - Slice 0 Multi Channel shadow transfer enable"]
620 #[inline(always)]
621 pub fn mse0(&mut self) -> MSE0_W<GCTRL_SPEC> {
622 MSE0_W::new(self, 10)
623 }
624 #[doc = "Bit 11 - Slice 1 Multi Channel shadow transfer enable"]
625 #[inline(always)]
626 pub fn mse1(&mut self) -> MSE1_W<GCTRL_SPEC> {
627 MSE1_W::new(self, 11)
628 }
629 #[doc = "Bit 12 - Slice 2 Multi Channel shadow transfer enable"]
630 #[inline(always)]
631 pub fn mse2(&mut self) -> MSE2_W<GCTRL_SPEC> {
632 MSE2_W::new(self, 12)
633 }
634 #[doc = "Bit 13 - Slice 3 Multi Channel shadow transfer enable"]
635 #[inline(always)]
636 pub fn mse3(&mut self) -> MSE3_W<GCTRL_SPEC> {
637 MSE3_W::new(self, 13)
638 }
639 #[doc = "Bits 14:15 - Multi Channel shadow transfer request configuration"]
640 #[inline(always)]
641 pub fn msde(&mut self) -> MSDE_W<GCTRL_SPEC> {
642 MSDE_W::new(self, 14)
643 }
644}
645#[doc = "Global Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
646pub struct GCTRL_SPEC;
647impl crate::RegisterSpec for GCTRL_SPEC {
648 type Ux = u32;
649}
650#[doc = "`read()` method returns [`gctrl::R`](R) reader structure"]
651impl crate::Readable for GCTRL_SPEC {}
652#[doc = "`write(|w| ..)` method takes [`gctrl::W`](W) writer structure"]
653impl crate::Writable for GCTRL_SPEC {
654 type Safety = crate::Unsafe;
655 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
656 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
657}
658#[doc = "`reset()` method sets GCTRL to value 0"]
659impl crate::Resettable for GCTRL_SPEC {
660 const RESET_VALUE: u32 = 0;
661}