xmc4300/
usb0_ch0.rs

1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4    hcchar: HCCHAR,
5    _reserved1: [u8; 0x04],
6    hcint: HCINT,
7    hcintmsk: HCINTMSK,
8    _reserved_3_hctsiz: [u8; 0x04],
9    _reserved_4_hcdma: [u8; 0x04],
10    _reserved5: [u8; 0x04],
11    hcdmab: HCDMAB,
12}
13impl RegisterBlock {
14    #[doc = "0x00 - Host Channel Characteristics Register"]
15    #[inline(always)]
16    pub const fn hcchar(&self) -> &HCCHAR {
17        &self.hcchar
18    }
19    #[doc = "0x08 - Host Channel Interrupt Register"]
20    #[inline(always)]
21    pub const fn hcint(&self) -> &HCINT {
22        &self.hcint
23    }
24    #[doc = "0x0c - Host Channel Interrupt Mask Register"]
25    #[inline(always)]
26    pub const fn hcintmsk(&self) -> &HCINTMSK {
27        &self.hcintmsk
28    }
29    #[doc = "0x10 - Host Channel Transfer Size Register \\[SCATGATHER\\]"]
30    #[inline(always)]
31    pub const fn hctsiz_scatgather(&self) -> &HCTSIZ_SCATGATHER {
32        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).cast() }
33    }
34    #[doc = "0x10 - Host Channel Transfer Size Register \\[BUFFERMODE\\]"]
35    #[inline(always)]
36    pub const fn hctsiz_buffermode(&self) -> &HCTSIZ_BUFFERMODE {
37        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).cast() }
38    }
39    #[doc = "0x14 - Host Channel DMA Address Register \\[SCATGATHER\\]"]
40    #[inline(always)]
41    pub const fn hcdma_scatgather(&self) -> &HCDMA_SCATGATHER {
42        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).cast() }
43    }
44    #[doc = "0x14 - Host Channel DMA Address Register \\[BUFFERMODE\\]"]
45    #[inline(always)]
46    pub const fn hcdma_buffermode(&self) -> &HCDMA_BUFFERMODE {
47        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).cast() }
48    }
49    #[doc = "0x1c - Host Channel DMA Buffer Address Register"]
50    #[inline(always)]
51    pub const fn hcdmab(&self) -> &HCDMAB {
52        &self.hcdmab
53    }
54}
55#[doc = "HCCHAR (rw) register accessor: Host Channel Characteristics Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hcchar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hcchar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcchar`]
56module"]
57pub type HCCHAR = crate::Reg<hcchar::HCCHAR_SPEC>;
58#[doc = "Host Channel Characteristics Register"]
59pub mod hcchar;
60#[doc = "HCINT (rw) register accessor: Host Channel Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hcint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hcint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcint`]
61module"]
62pub type HCINT = crate::Reg<hcint::HCINT_SPEC>;
63#[doc = "Host Channel Interrupt Register"]
64pub mod hcint;
65#[doc = "HCINTMSK (rw) register accessor: Host Channel Interrupt Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hcintmsk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hcintmsk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcintmsk`]
66module"]
67pub type HCINTMSK = crate::Reg<hcintmsk::HCINTMSK_SPEC>;
68#[doc = "Host Channel Interrupt Mask Register"]
69pub mod hcintmsk;
70#[doc = "HCTSIZ_BUFFERMODE (rw) register accessor: Host Channel Transfer Size Register \\[BUFFERMODE\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`hctsiz_buffermode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hctsiz_buffermode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hctsiz_buffermode`]
71module"]
72pub type HCTSIZ_BUFFERMODE = crate::Reg<hctsiz_buffermode::HCTSIZ_BUFFERMODE_SPEC>;
73#[doc = "Host Channel Transfer Size Register \\[BUFFERMODE\\]"]
74pub mod hctsiz_buffermode;
75#[doc = "HCTSIZ_SCATGATHER (rw) register accessor: Host Channel Transfer Size Register \\[SCATGATHER\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`hctsiz_scatgather::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hctsiz_scatgather::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hctsiz_scatgather`]
76module"]
77pub type HCTSIZ_SCATGATHER = crate::Reg<hctsiz_scatgather::HCTSIZ_SCATGATHER_SPEC>;
78#[doc = "Host Channel Transfer Size Register \\[SCATGATHER\\]"]
79pub mod hctsiz_scatgather;
80#[doc = "HCDMA_BUFFERMODE (rw) register accessor: Host Channel DMA Address Register \\[BUFFERMODE\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`hcdma_buffermode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hcdma_buffermode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\n<div class=\"warning\">One or more dependent resources other than the current register are immediately affected by a read operation.</div>\n\nFor information about available fields see [`mod@hcdma_buffermode`]
81module"]
82pub type HCDMA_BUFFERMODE = crate::Reg<hcdma_buffermode::HCDMA_BUFFERMODE_SPEC>;
83#[doc = "Host Channel DMA Address Register \\[BUFFERMODE\\]"]
84pub mod hcdma_buffermode;
85#[doc = "HCDMA_SCATGATHER (rw) register accessor: Host Channel DMA Address Register \\[SCATGATHER\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`hcdma_scatgather::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hcdma_scatgather::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\n<div class=\"warning\">One or more dependent resources other than the current register are immediately affected by a read operation.</div>\n\nFor information about available fields see [`mod@hcdma_scatgather`]
86module"]
87pub type HCDMA_SCATGATHER = crate::Reg<hcdma_scatgather::HCDMA_SCATGATHER_SPEC>;
88#[doc = "Host Channel DMA Address Register \\[SCATGATHER\\]"]
89pub mod hcdma_scatgather;
90#[doc = "HCDMAB (r) register accessor: Host Channel DMA Buffer Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hcdmab::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcdmab`]
91module"]
92pub type HCDMAB = crate::Reg<hcdmab::HCDMAB_SPEC>;
93#[doc = "Host Channel DMA Buffer Address Register"]
94pub mod hcdmab;
xmc4300/usb0_ch0.rs

xmc4300/
usb0_ch0.rs
