xmc4300/usb0/
dcfg.rs

1#[doc = "Register `DCFG` reader"]
2pub type R = crate::R<DCFG_SPEC>;
3#[doc = "Register `DCFG` writer"]
4pub type W = crate::W<DCFG_SPEC>;
5#[doc = "Device Speed\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum DEV_SPD_A {
9    #[doc = "3: Full speed (USB 1.1 transceiver clock is 48 MHz)"]
10    VALUE4 = 3,
11}
12impl From<DEV_SPD_A> for u8 {
13    #[inline(always)]
14    fn from(variant: DEV_SPD_A) -> Self {
15        variant as _
16    }
17}
18impl crate::FieldSpec for DEV_SPD_A {
19    type Ux = u8;
20}
21impl crate::IsEnum for DEV_SPD_A {}
22#[doc = "Field `DevSpd` reader - Device Speed"]
23pub type DEV_SPD_R = crate::FieldReader<DEV_SPD_A>;
24impl DEV_SPD_R {
25    #[doc = "Get enumerated values variant"]
26    #[inline(always)]
27    pub const fn variant(&self) -> Option<DEV_SPD_A> {
28        match self.bits {
29            3 => Some(DEV_SPD_A::VALUE4),
30            _ => None,
31        }
32    }
33    #[doc = "Full speed (USB 1.1 transceiver clock is 48 MHz)"]
34    #[inline(always)]
35    pub fn is_value4(&self) -> bool {
36        *self == DEV_SPD_A::VALUE4
37    }
38}
39#[doc = "Field `DevSpd` writer - Device Speed"]
40pub type DEV_SPD_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DEV_SPD_A>;
41impl<'a, REG> DEV_SPD_W<'a, REG>
42where
43    REG: crate::Writable + crate::RegisterSpec,
44    REG::Ux: From<u8>,
45{
46    #[doc = "Full speed (USB 1.1 transceiver clock is 48 MHz)"]
47    #[inline(always)]
48    pub fn value4(self) -> &'a mut crate::W<REG> {
49        self.variant(DEV_SPD_A::VALUE4)
50    }
51}
52#[doc = "Non-Zero-Length Status OUT Handshake\n\nValue on reset: 0"]
53#[derive(Clone, Copy, Debug, PartialEq, Eq)]
54pub enum NZSTS_OUTHSHK_A {
55    #[doc = "1: Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application."]
56    VALUE1 = 1,
57    #[doc = "0: Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register."]
58    VALUE2 = 0,
59}
60impl From<NZSTS_OUTHSHK_A> for bool {
61    #[inline(always)]
62    fn from(variant: NZSTS_OUTHSHK_A) -> Self {
63        variant as u8 != 0
64    }
65}
66#[doc = "Field `NZStsOUTHShk` reader - Non-Zero-Length Status OUT Handshake"]
67pub type NZSTS_OUTHSHK_R = crate::BitReader<NZSTS_OUTHSHK_A>;
68impl NZSTS_OUTHSHK_R {
69    #[doc = "Get enumerated values variant"]
70    #[inline(always)]
71    pub const fn variant(&self) -> NZSTS_OUTHSHK_A {
72        match self.bits {
73            true => NZSTS_OUTHSHK_A::VALUE1,
74            false => NZSTS_OUTHSHK_A::VALUE2,
75        }
76    }
77    #[doc = "Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application."]
78    #[inline(always)]
79    pub fn is_value1(&self) -> bool {
80        *self == NZSTS_OUTHSHK_A::VALUE1
81    }
82    #[doc = "Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register."]
83    #[inline(always)]
84    pub fn is_value2(&self) -> bool {
85        *self == NZSTS_OUTHSHK_A::VALUE2
86    }
87}
88#[doc = "Field `NZStsOUTHShk` writer - Non-Zero-Length Status OUT Handshake"]
89pub type NZSTS_OUTHSHK_W<'a, REG> = crate::BitWriter<'a, REG, NZSTS_OUTHSHK_A>;
90impl<'a, REG> NZSTS_OUTHSHK_W<'a, REG>
91where
92    REG: crate::Writable + crate::RegisterSpec,
93{
94    #[doc = "Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application."]
95    #[inline(always)]
96    pub fn value1(self) -> &'a mut crate::W<REG> {
97        self.variant(NZSTS_OUTHSHK_A::VALUE1)
98    }
99    #[doc = "Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register."]
100    #[inline(always)]
101    pub fn value2(self) -> &'a mut crate::W<REG> {
102        self.variant(NZSTS_OUTHSHK_A::VALUE2)
103    }
104}
105#[doc = "Field `DevAddr` reader - Device Address"]
106pub type DEV_ADDR_R = crate::FieldReader;
107#[doc = "Field `DevAddr` writer - Device Address"]
108pub type DEV_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
109#[doc = "Periodic Frame Interval\n\nValue on reset: 0"]
110#[derive(Clone, Copy, Debug, PartialEq, Eq)]
111#[repr(u8)]
112pub enum PER_FR_INT_A {
113    #[doc = "0: 80% of the frame interval"]
114    VALUE1 = 0,
115    #[doc = "1: 85%"]
116    VALUE2 = 1,
117    #[doc = "2: 90%"]
118    VALUE3 = 2,
119    #[doc = "3: 95%"]
120    VALUE4 = 3,
121}
122impl From<PER_FR_INT_A> for u8 {
123    #[inline(always)]
124    fn from(variant: PER_FR_INT_A) -> Self {
125        variant as _
126    }
127}
128impl crate::FieldSpec for PER_FR_INT_A {
129    type Ux = u8;
130}
131impl crate::IsEnum for PER_FR_INT_A {}
132#[doc = "Field `PerFrInt` reader - Periodic Frame Interval"]
133pub type PER_FR_INT_R = crate::FieldReader<PER_FR_INT_A>;
134impl PER_FR_INT_R {
135    #[doc = "Get enumerated values variant"]
136    #[inline(always)]
137    pub const fn variant(&self) -> PER_FR_INT_A {
138        match self.bits {
139            0 => PER_FR_INT_A::VALUE1,
140            1 => PER_FR_INT_A::VALUE2,
141            2 => PER_FR_INT_A::VALUE3,
142            3 => PER_FR_INT_A::VALUE4,
143            _ => unreachable!(),
144        }
145    }
146    #[doc = "80% of the frame interval"]
147    #[inline(always)]
148    pub fn is_value1(&self) -> bool {
149        *self == PER_FR_INT_A::VALUE1
150    }
151    #[doc = "85%"]
152    #[inline(always)]
153    pub fn is_value2(&self) -> bool {
154        *self == PER_FR_INT_A::VALUE2
155    }
156    #[doc = "90%"]
157    #[inline(always)]
158    pub fn is_value3(&self) -> bool {
159        *self == PER_FR_INT_A::VALUE3
160    }
161    #[doc = "95%"]
162    #[inline(always)]
163    pub fn is_value4(&self) -> bool {
164        *self == PER_FR_INT_A::VALUE4
165    }
166}
167#[doc = "Field `PerFrInt` writer - Periodic Frame Interval"]
168pub type PER_FR_INT_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PER_FR_INT_A, crate::Safe>;
169impl<'a, REG> PER_FR_INT_W<'a, REG>
170where
171    REG: crate::Writable + crate::RegisterSpec,
172    REG::Ux: From<u8>,
173{
174    #[doc = "80% of the frame interval"]
175    #[inline(always)]
176    pub fn value1(self) -> &'a mut crate::W<REG> {
177        self.variant(PER_FR_INT_A::VALUE1)
178    }
179    #[doc = "85%"]
180    #[inline(always)]
181    pub fn value2(self) -> &'a mut crate::W<REG> {
182        self.variant(PER_FR_INT_A::VALUE2)
183    }
184    #[doc = "90%"]
185    #[inline(always)]
186    pub fn value3(self) -> &'a mut crate::W<REG> {
187        self.variant(PER_FR_INT_A::VALUE3)
188    }
189    #[doc = "95%"]
190    #[inline(always)]
191    pub fn value4(self) -> &'a mut crate::W<REG> {
192        self.variant(PER_FR_INT_A::VALUE4)
193    }
194}
195#[doc = "Field `DescDMA` reader - Enable Scatter/Gather DMA in Device mode."]
196pub type DESC_DMA_R = crate::BitReader;
197#[doc = "Field `DescDMA` writer - Enable Scatter/Gather DMA in Device mode."]
198pub type DESC_DMA_W<'a, REG> = crate::BitWriter<'a, REG>;
199#[doc = "Periodic Scheduling Interval\n\nValue on reset: 0"]
200#[derive(Clone, Copy, Debug, PartialEq, Eq)]
201#[repr(u8)]
202pub enum PER_SCH_INTVL_A {
203    #[doc = "0: 25% of frame."]
204    VALUE1 = 0,
205    #[doc = "1: 50% of frame."]
206    VALUE2 = 1,
207    #[doc = "2: 75% of frame."]
208    VALUE3 = 2,
209}
210impl From<PER_SCH_INTVL_A> for u8 {
211    #[inline(always)]
212    fn from(variant: PER_SCH_INTVL_A) -> Self {
213        variant as _
214    }
215}
216impl crate::FieldSpec for PER_SCH_INTVL_A {
217    type Ux = u8;
218}
219impl crate::IsEnum for PER_SCH_INTVL_A {}
220#[doc = "Field `PerSchIntvl` reader - Periodic Scheduling Interval"]
221pub type PER_SCH_INTVL_R = crate::FieldReader<PER_SCH_INTVL_A>;
222impl PER_SCH_INTVL_R {
223    #[doc = "Get enumerated values variant"]
224    #[inline(always)]
225    pub const fn variant(&self) -> Option<PER_SCH_INTVL_A> {
226        match self.bits {
227            0 => Some(PER_SCH_INTVL_A::VALUE1),
228            1 => Some(PER_SCH_INTVL_A::VALUE2),
229            2 => Some(PER_SCH_INTVL_A::VALUE3),
230            _ => None,
231        }
232    }
233    #[doc = "25% of frame."]
234    #[inline(always)]
235    pub fn is_value1(&self) -> bool {
236        *self == PER_SCH_INTVL_A::VALUE1
237    }
238    #[doc = "50% of frame."]
239    #[inline(always)]
240    pub fn is_value2(&self) -> bool {
241        *self == PER_SCH_INTVL_A::VALUE2
242    }
243    #[doc = "75% of frame."]
244    #[inline(always)]
245    pub fn is_value3(&self) -> bool {
246        *self == PER_SCH_INTVL_A::VALUE3
247    }
248}
249#[doc = "Field `PerSchIntvl` writer - Periodic Scheduling Interval"]
250pub type PER_SCH_INTVL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PER_SCH_INTVL_A>;
251impl<'a, REG> PER_SCH_INTVL_W<'a, REG>
252where
253    REG: crate::Writable + crate::RegisterSpec,
254    REG::Ux: From<u8>,
255{
256    #[doc = "25% of frame."]
257    #[inline(always)]
258    pub fn value1(self) -> &'a mut crate::W<REG> {
259        self.variant(PER_SCH_INTVL_A::VALUE1)
260    }
261    #[doc = "50% of frame."]
262    #[inline(always)]
263    pub fn value2(self) -> &'a mut crate::W<REG> {
264        self.variant(PER_SCH_INTVL_A::VALUE2)
265    }
266    #[doc = "75% of frame."]
267    #[inline(always)]
268    pub fn value3(self) -> &'a mut crate::W<REG> {
269        self.variant(PER_SCH_INTVL_A::VALUE3)
270    }
271}
272impl R {
273    #[doc = "Bits 0:1 - Device Speed"]
274    #[inline(always)]
275    pub fn dev_spd(&self) -> DEV_SPD_R {
276        DEV_SPD_R::new((self.bits & 3) as u8)
277    }
278    #[doc = "Bit 2 - Non-Zero-Length Status OUT Handshake"]
279    #[inline(always)]
280    pub fn nzsts_outhshk(&self) -> NZSTS_OUTHSHK_R {
281        NZSTS_OUTHSHK_R::new(((self.bits >> 2) & 1) != 0)
282    }
283    #[doc = "Bits 4:10 - Device Address"]
284    #[inline(always)]
285    pub fn dev_addr(&self) -> DEV_ADDR_R {
286        DEV_ADDR_R::new(((self.bits >> 4) & 0x7f) as u8)
287    }
288    #[doc = "Bits 11:12 - Periodic Frame Interval"]
289    #[inline(always)]
290    pub fn per_fr_int(&self) -> PER_FR_INT_R {
291        PER_FR_INT_R::new(((self.bits >> 11) & 3) as u8)
292    }
293    #[doc = "Bit 23 - Enable Scatter/Gather DMA in Device mode."]
294    #[inline(always)]
295    pub fn desc_dma(&self) -> DESC_DMA_R {
296        DESC_DMA_R::new(((self.bits >> 23) & 1) != 0)
297    }
298    #[doc = "Bits 24:25 - Periodic Scheduling Interval"]
299    #[inline(always)]
300    pub fn per_sch_intvl(&self) -> PER_SCH_INTVL_R {
301        PER_SCH_INTVL_R::new(((self.bits >> 24) & 3) as u8)
302    }
303}
304impl W {
305    #[doc = "Bits 0:1 - Device Speed"]
306    #[inline(always)]
307    pub fn dev_spd(&mut self) -> DEV_SPD_W<DCFG_SPEC> {
308        DEV_SPD_W::new(self, 0)
309    }
310    #[doc = "Bit 2 - Non-Zero-Length Status OUT Handshake"]
311    #[inline(always)]
312    pub fn nzsts_outhshk(&mut self) -> NZSTS_OUTHSHK_W<DCFG_SPEC> {
313        NZSTS_OUTHSHK_W::new(self, 2)
314    }
315    #[doc = "Bits 4:10 - Device Address"]
316    #[inline(always)]
317    pub fn dev_addr(&mut self) -> DEV_ADDR_W<DCFG_SPEC> {
318        DEV_ADDR_W::new(self, 4)
319    }
320    #[doc = "Bits 11:12 - Periodic Frame Interval"]
321    #[inline(always)]
322    pub fn per_fr_int(&mut self) -> PER_FR_INT_W<DCFG_SPEC> {
323        PER_FR_INT_W::new(self, 11)
324    }
325    #[doc = "Bit 23 - Enable Scatter/Gather DMA in Device mode."]
326    #[inline(always)]
327    pub fn desc_dma(&mut self) -> DESC_DMA_W<DCFG_SPEC> {
328        DESC_DMA_W::new(self, 23)
329    }
330    #[doc = "Bits 24:25 - Periodic Scheduling Interval"]
331    #[inline(always)]
332    pub fn per_sch_intvl(&mut self) -> PER_SCH_INTVL_W<DCFG_SPEC> {
333        PER_SCH_INTVL_W::new(self, 24)
334    }
335}
336#[doc = "Device Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
337pub struct DCFG_SPEC;
338impl crate::RegisterSpec for DCFG_SPEC {
339    type Ux = u32;
340}
341#[doc = "`read()` method returns [`dcfg::R`](R) reader structure"]
342impl crate::Readable for DCFG_SPEC {}
343#[doc = "`write(|w| ..)` method takes [`dcfg::W`](W) writer structure"]
344impl crate::Writable for DCFG_SPEC {
345    type Safety = crate::Unsafe;
346    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
347    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
348}
349#[doc = "`reset()` method sets DCFG to value 0x0820_0000"]
350impl crate::Resettable for DCFG_SPEC {
351    const RESET_VALUE: u32 = 0x0820_0000;
352}
xmc4300/usb0/dcfg.rs

xmc4300/usb0/
dcfg.rs
