xmc4300/scu_reset/
prclr1.rs

1#[doc = "Register `PRCLR1` writer"]
2pub type W = crate::W<PRCLR1_SPEC>;
3#[doc = "LEDTS Reset Clear\n\nValue on reset: 0"]
4#[derive(Clone, Copy, Debug, PartialEq, Eq)]
5pub enum LEDTSCU0RS_A {
6    #[doc = "0: No effect"]
7    CONST_0 = 0,
8    #[doc = "1: De-assert reset"]
9    CONST_1 = 1,
10}
11impl From<LEDTSCU0RS_A> for bool {
12    #[inline(always)]
13    fn from(variant: LEDTSCU0RS_A) -> Self {
14        variant as u8 != 0
15    }
16}
17#[doc = "Field `LEDTSCU0RS` writer - LEDTS Reset Clear"]
18pub type LEDTSCU0RS_W<'a, REG> = crate::BitWriter<'a, REG, LEDTSCU0RS_A>;
19impl<'a, REG> LEDTSCU0RS_W<'a, REG>
20where
21    REG: crate::Writable + crate::RegisterSpec,
22{
23    #[doc = "No effect"]
24    #[inline(always)]
25    pub fn const_0(self) -> &'a mut crate::W<REG> {
26        self.variant(LEDTSCU0RS_A::CONST_0)
27    }
28    #[doc = "De-assert reset"]
29    #[inline(always)]
30    pub fn const_1(self) -> &'a mut crate::W<REG> {
31        self.variant(LEDTSCU0RS_A::CONST_1)
32    }
33}
34#[doc = "MultiCAN Reset Clear\n\nValue on reset: 0"]
35#[derive(Clone, Copy, Debug, PartialEq, Eq)]
36pub enum MCAN0RS_A {
37    #[doc = "0: No effect"]
38    CONST_0 = 0,
39    #[doc = "1: De-assert reset"]
40    CONST_1 = 1,
41}
42impl From<MCAN0RS_A> for bool {
43    #[inline(always)]
44    fn from(variant: MCAN0RS_A) -> Self {
45        variant as u8 != 0
46    }
47}
48#[doc = "Field `MCAN0RS` writer - MultiCAN Reset Clear"]
49pub type MCAN0RS_W<'a, REG> = crate::BitWriter<'a, REG, MCAN0RS_A>;
50impl<'a, REG> MCAN0RS_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    #[doc = "No effect"]
55    #[inline(always)]
56    pub fn const_0(self) -> &'a mut crate::W<REG> {
57        self.variant(MCAN0RS_A::CONST_0)
58    }
59    #[doc = "De-assert reset"]
60    #[inline(always)]
61    pub fn const_1(self) -> &'a mut crate::W<REG> {
62        self.variant(MCAN0RS_A::CONST_1)
63    }
64}
65#[doc = "DAC Reset Clear\n\nValue on reset: 0"]
66#[derive(Clone, Copy, Debug, PartialEq, Eq)]
67pub enum DACRS_A {
68    #[doc = "0: No effect"]
69    CONST_0 = 0,
70    #[doc = "1: De-assert reset"]
71    CONST_1 = 1,
72}
73impl From<DACRS_A> for bool {
74    #[inline(always)]
75    fn from(variant: DACRS_A) -> Self {
76        variant as u8 != 0
77    }
78}
79#[doc = "Field `DACRS` writer - DAC Reset Clear"]
80pub type DACRS_W<'a, REG> = crate::BitWriter<'a, REG, DACRS_A>;
81impl<'a, REG> DACRS_W<'a, REG>
82where
83    REG: crate::Writable + crate::RegisterSpec,
84{
85    #[doc = "No effect"]
86    #[inline(always)]
87    pub fn const_0(self) -> &'a mut crate::W<REG> {
88        self.variant(DACRS_A::CONST_0)
89    }
90    #[doc = "De-assert reset"]
91    #[inline(always)]
92    pub fn const_1(self) -> &'a mut crate::W<REG> {
93        self.variant(DACRS_A::CONST_1)
94    }
95}
96#[doc = "MMC Interface Reset Clear\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98pub enum MMCIRS_A {
99    #[doc = "0: No effect"]
100    CONST_0 = 0,
101    #[doc = "1: De-assert reset"]
102    CONST_1 = 1,
103}
104impl From<MMCIRS_A> for bool {
105    #[inline(always)]
106    fn from(variant: MMCIRS_A) -> Self {
107        variant as u8 != 0
108    }
109}
110#[doc = "Field `MMCIRS` writer - MMC Interface Reset Clear"]
111pub type MMCIRS_W<'a, REG> = crate::BitWriter<'a, REG, MMCIRS_A>;
112impl<'a, REG> MMCIRS_W<'a, REG>
113where
114    REG: crate::Writable + crate::RegisterSpec,
115{
116    #[doc = "No effect"]
117    #[inline(always)]
118    pub fn const_0(self) -> &'a mut crate::W<REG> {
119        self.variant(MMCIRS_A::CONST_0)
120    }
121    #[doc = "De-assert reset"]
122    #[inline(always)]
123    pub fn const_1(self) -> &'a mut crate::W<REG> {
124        self.variant(MMCIRS_A::CONST_1)
125    }
126}
127#[doc = "USIC1 Reset Clear\n\nValue on reset: 0"]
128#[derive(Clone, Copy, Debug, PartialEq, Eq)]
129pub enum USIC1RS_A {
130    #[doc = "0: No effect"]
131    CONST_0 = 0,
132    #[doc = "1: De-assert reset"]
133    CONST_1 = 1,
134}
135impl From<USIC1RS_A> for bool {
136    #[inline(always)]
137    fn from(variant: USIC1RS_A) -> Self {
138        variant as u8 != 0
139    }
140}
141#[doc = "Field `USIC1RS` writer - USIC1 Reset Clear"]
142pub type USIC1RS_W<'a, REG> = crate::BitWriter<'a, REG, USIC1RS_A>;
143impl<'a, REG> USIC1RS_W<'a, REG>
144where
145    REG: crate::Writable + crate::RegisterSpec,
146{
147    #[doc = "No effect"]
148    #[inline(always)]
149    pub fn const_0(self) -> &'a mut crate::W<REG> {
150        self.variant(USIC1RS_A::CONST_0)
151    }
152    #[doc = "De-assert reset"]
153    #[inline(always)]
154    pub fn const_1(self) -> &'a mut crate::W<REG> {
155        self.variant(USIC1RS_A::CONST_1)
156    }
157}
158#[doc = "PORTS Reset Clear\n\nValue on reset: 0"]
159#[derive(Clone, Copy, Debug, PartialEq, Eq)]
160pub enum PPORTSRS_A {
161    #[doc = "0: No effect"]
162    CONST_0 = 0,
163    #[doc = "1: De-assert reset"]
164    CONST_1 = 1,
165}
166impl From<PPORTSRS_A> for bool {
167    #[inline(always)]
168    fn from(variant: PPORTSRS_A) -> Self {
169        variant as u8 != 0
170    }
171}
172#[doc = "Field `PPORTSRS` writer - PORTS Reset Clear"]
173pub type PPORTSRS_W<'a, REG> = crate::BitWriter<'a, REG, PPORTSRS_A>;
174impl<'a, REG> PPORTSRS_W<'a, REG>
175where
176    REG: crate::Writable + crate::RegisterSpec,
177{
178    #[doc = "No effect"]
179    #[inline(always)]
180    pub fn const_0(self) -> &'a mut crate::W<REG> {
181        self.variant(PPORTSRS_A::CONST_0)
182    }
183    #[doc = "De-assert reset"]
184    #[inline(always)]
185    pub fn const_1(self) -> &'a mut crate::W<REG> {
186        self.variant(PPORTSRS_A::CONST_1)
187    }
188}
189impl W {
190    #[doc = "Bit 3 - LEDTS Reset Clear"]
191    #[inline(always)]
192    pub fn ledtscu0rs(&mut self) -> LEDTSCU0RS_W<PRCLR1_SPEC> {
193        LEDTSCU0RS_W::new(self, 3)
194    }
195    #[doc = "Bit 4 - MultiCAN Reset Clear"]
196    #[inline(always)]
197    pub fn mcan0rs(&mut self) -> MCAN0RS_W<PRCLR1_SPEC> {
198        MCAN0RS_W::new(self, 4)
199    }
200    #[doc = "Bit 5 - DAC Reset Clear"]
201    #[inline(always)]
202    pub fn dacrs(&mut self) -> DACRS_W<PRCLR1_SPEC> {
203        DACRS_W::new(self, 5)
204    }
205    #[doc = "Bit 6 - MMC Interface Reset Clear"]
206    #[inline(always)]
207    pub fn mmcirs(&mut self) -> MMCIRS_W<PRCLR1_SPEC> {
208        MMCIRS_W::new(self, 6)
209    }
210    #[doc = "Bit 7 - USIC1 Reset Clear"]
211    #[inline(always)]
212    pub fn usic1rs(&mut self) -> USIC1RS_W<PRCLR1_SPEC> {
213        USIC1RS_W::new(self, 7)
214    }
215    #[doc = "Bit 9 - PORTS Reset Clear"]
216    #[inline(always)]
217    pub fn pportsrs(&mut self) -> PPORTSRS_W<PRCLR1_SPEC> {
218        PPORTSRS_W::new(self, 9)
219    }
220}
221#[doc = "RCU Peripheral 1 Reset Clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prclr1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
222pub struct PRCLR1_SPEC;
223impl crate::RegisterSpec for PRCLR1_SPEC {
224    type Ux = u32;
225}
226#[doc = "`write(|w| ..)` method takes [`prclr1::W`](W) writer structure"]
227impl crate::Writable for PRCLR1_SPEC {
228    type Safety = crate::Unsafe;
229    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
230    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
231}
232#[doc = "`reset()` method sets PRCLR1 to value 0"]
233impl crate::Resettable for PRCLR1_SPEC {
234    const RESET_VALUE: u32 = 0;
235}
xmc4300/scu_reset/prclr1.rs

xmc4300/scu_reset/
prclr1.rs
