xmc4300/ppb/
cfsr.rs

1#[doc = "Register `CFSR` reader"]
2pub type R = crate::R<CFSR_SPEC>;
3#[doc = "Register `CFSR` writer"]
4pub type W = crate::W<CFSR_SPEC>;
5#[doc = "Instruction access violation flag\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum IACCVIOL_A {
8    #[doc = "0: no instruction access violation fault"]
9    VALUE1 = 0,
10    #[doc = "1: the processor attempted an instruction fetch from a location that does not permit execution."]
11    VALUE2 = 1,
12}
13impl From<IACCVIOL_A> for bool {
14    #[inline(always)]
15    fn from(variant: IACCVIOL_A) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `IACCVIOL` reader - Instruction access violation flag"]
20pub type IACCVIOL_R = crate::BitReader<IACCVIOL_A>;
21impl IACCVIOL_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> IACCVIOL_A {
25        match self.bits {
26            false => IACCVIOL_A::VALUE1,
27            true => IACCVIOL_A::VALUE2,
28        }
29    }
30    #[doc = "no instruction access violation fault"]
31    #[inline(always)]
32    pub fn is_value1(&self) -> bool {
33        *self == IACCVIOL_A::VALUE1
34    }
35    #[doc = "the processor attempted an instruction fetch from a location that does not permit execution."]
36    #[inline(always)]
37    pub fn is_value2(&self) -> bool {
38        *self == IACCVIOL_A::VALUE2
39    }
40}
41#[doc = "Field `IACCVIOL` writer - Instruction access violation flag"]
42pub type IACCVIOL_W<'a, REG> = crate::BitWriter<'a, REG, IACCVIOL_A>;
43impl<'a, REG> IACCVIOL_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "no instruction access violation fault"]
48    #[inline(always)]
49    pub fn value1(self) -> &'a mut crate::W<REG> {
50        self.variant(IACCVIOL_A::VALUE1)
51    }
52    #[doc = "the processor attempted an instruction fetch from a location that does not permit execution."]
53    #[inline(always)]
54    pub fn value2(self) -> &'a mut crate::W<REG> {
55        self.variant(IACCVIOL_A::VALUE2)
56    }
57}
58#[doc = "Data access violation flag\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum DACCVIOL_A {
61    #[doc = "0: no data access violation fault"]
62    VALUE1 = 0,
63    #[doc = "1: the processor attempted a load or store at a location that does not permit the operation."]
64    VALUE2 = 1,
65}
66impl From<DACCVIOL_A> for bool {
67    #[inline(always)]
68    fn from(variant: DACCVIOL_A) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `DACCVIOL` reader - Data access violation flag"]
73pub type DACCVIOL_R = crate::BitReader<DACCVIOL_A>;
74impl DACCVIOL_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> DACCVIOL_A {
78        match self.bits {
79            false => DACCVIOL_A::VALUE1,
80            true => DACCVIOL_A::VALUE2,
81        }
82    }
83    #[doc = "no data access violation fault"]
84    #[inline(always)]
85    pub fn is_value1(&self) -> bool {
86        *self == DACCVIOL_A::VALUE1
87    }
88    #[doc = "the processor attempted a load or store at a location that does not permit the operation."]
89    #[inline(always)]
90    pub fn is_value2(&self) -> bool {
91        *self == DACCVIOL_A::VALUE2
92    }
93}
94#[doc = "Field `DACCVIOL` writer - Data access violation flag"]
95pub type DACCVIOL_W<'a, REG> = crate::BitWriter<'a, REG, DACCVIOL_A>;
96impl<'a, REG> DACCVIOL_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "no data access violation fault"]
101    #[inline(always)]
102    pub fn value1(self) -> &'a mut crate::W<REG> {
103        self.variant(DACCVIOL_A::VALUE1)
104    }
105    #[doc = "the processor attempted a load or store at a location that does not permit the operation."]
106    #[inline(always)]
107    pub fn value2(self) -> &'a mut crate::W<REG> {
108        self.variant(DACCVIOL_A::VALUE2)
109    }
110}
111#[doc = "MemManage fault on unstacking for a return from exception\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum MUNSTKERR_A {
114    #[doc = "0: no unstacking fault"]
115    VALUE1 = 0,
116    #[doc = "1: unstack for an exception return has caused one or more access violations."]
117    VALUE2 = 1,
118}
119impl From<MUNSTKERR_A> for bool {
120    #[inline(always)]
121    fn from(variant: MUNSTKERR_A) -> Self {
122        variant as u8 != 0
123    }
124}
125#[doc = "Field `MUNSTKERR` reader - MemManage fault on unstacking for a return from exception"]
126pub type MUNSTKERR_R = crate::BitReader<MUNSTKERR_A>;
127impl MUNSTKERR_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> MUNSTKERR_A {
131        match self.bits {
132            false => MUNSTKERR_A::VALUE1,
133            true => MUNSTKERR_A::VALUE2,
134        }
135    }
136    #[doc = "no unstacking fault"]
137    #[inline(always)]
138    pub fn is_value1(&self) -> bool {
139        *self == MUNSTKERR_A::VALUE1
140    }
141    #[doc = "unstack for an exception return has caused one or more access violations."]
142    #[inline(always)]
143    pub fn is_value2(&self) -> bool {
144        *self == MUNSTKERR_A::VALUE2
145    }
146}
147#[doc = "Field `MUNSTKERR` writer - MemManage fault on unstacking for a return from exception"]
148pub type MUNSTKERR_W<'a, REG> = crate::BitWriter<'a, REG, MUNSTKERR_A>;
149impl<'a, REG> MUNSTKERR_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "no unstacking fault"]
154    #[inline(always)]
155    pub fn value1(self) -> &'a mut crate::W<REG> {
156        self.variant(MUNSTKERR_A::VALUE1)
157    }
158    #[doc = "unstack for an exception return has caused one or more access violations."]
159    #[inline(always)]
160    pub fn value2(self) -> &'a mut crate::W<REG> {
161        self.variant(MUNSTKERR_A::VALUE2)
162    }
163}
164#[doc = "MemManage fault on stacking for exception entry\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum MSTKERR_A {
167    #[doc = "0: no stacking fault"]
168    VALUE1 = 0,
169    #[doc = "1: stacking for an exception entry has caused one or more access violations."]
170    VALUE2 = 1,
171}
172impl From<MSTKERR_A> for bool {
173    #[inline(always)]
174    fn from(variant: MSTKERR_A) -> Self {
175        variant as u8 != 0
176    }
177}
178#[doc = "Field `MSTKERR` reader - MemManage fault on stacking for exception entry"]
179pub type MSTKERR_R = crate::BitReader<MSTKERR_A>;
180impl MSTKERR_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> MSTKERR_A {
184        match self.bits {
185            false => MSTKERR_A::VALUE1,
186            true => MSTKERR_A::VALUE2,
187        }
188    }
189    #[doc = "no stacking fault"]
190    #[inline(always)]
191    pub fn is_value1(&self) -> bool {
192        *self == MSTKERR_A::VALUE1
193    }
194    #[doc = "stacking for an exception entry has caused one or more access violations."]
195    #[inline(always)]
196    pub fn is_value2(&self) -> bool {
197        *self == MSTKERR_A::VALUE2
198    }
199}
200#[doc = "Field `MSTKERR` writer - MemManage fault on stacking for exception entry"]
201pub type MSTKERR_W<'a, REG> = crate::BitWriter<'a, REG, MSTKERR_A>;
202impl<'a, REG> MSTKERR_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "no stacking fault"]
207    #[inline(always)]
208    pub fn value1(self) -> &'a mut crate::W<REG> {
209        self.variant(MSTKERR_A::VALUE1)
210    }
211    #[doc = "stacking for an exception entry has caused one or more access violations."]
212    #[inline(always)]
213    pub fn value2(self) -> &'a mut crate::W<REG> {
214        self.variant(MSTKERR_A::VALUE2)
215    }
216}
217#[doc = "MemManage fault during floating point lazy state preservation\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219pub enum MLSPERR_A {
220    #[doc = "0: No MemManage fault occurred during floating-point lazy state preservation"]
221    VALUE1 = 0,
222    #[doc = "1: A MemManage fault occurred during floating-point lazy state preservation"]
223    VALUE2 = 1,
224}
225impl From<MLSPERR_A> for bool {
226    #[inline(always)]
227    fn from(variant: MLSPERR_A) -> Self {
228        variant as u8 != 0
229    }
230}
231#[doc = "Field `MLSPERR` reader - MemManage fault during floating point lazy state preservation"]
232pub type MLSPERR_R = crate::BitReader<MLSPERR_A>;
233impl MLSPERR_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> MLSPERR_A {
237        match self.bits {
238            false => MLSPERR_A::VALUE1,
239            true => MLSPERR_A::VALUE2,
240        }
241    }
242    #[doc = "No MemManage fault occurred during floating-point lazy state preservation"]
243    #[inline(always)]
244    pub fn is_value1(&self) -> bool {
245        *self == MLSPERR_A::VALUE1
246    }
247    #[doc = "A MemManage fault occurred during floating-point lazy state preservation"]
248    #[inline(always)]
249    pub fn is_value2(&self) -> bool {
250        *self == MLSPERR_A::VALUE2
251    }
252}
253#[doc = "Field `MLSPERR` writer - MemManage fault during floating point lazy state preservation"]
254pub type MLSPERR_W<'a, REG> = crate::BitWriter<'a, REG, MLSPERR_A>;
255impl<'a, REG> MLSPERR_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "No MemManage fault occurred during floating-point lazy state preservation"]
260    #[inline(always)]
261    pub fn value1(self) -> &'a mut crate::W<REG> {
262        self.variant(MLSPERR_A::VALUE1)
263    }
264    #[doc = "A MemManage fault occurred during floating-point lazy state preservation"]
265    #[inline(always)]
266    pub fn value2(self) -> &'a mut crate::W<REG> {
267        self.variant(MLSPERR_A::VALUE2)
268    }
269}
270#[doc = "MemManage Fault Address Register (MMFAR) valid flag\n\nValue on reset: 0"]
271#[derive(Clone, Copy, Debug, PartialEq, Eq)]
272pub enum MMARVALID_A {
273    #[doc = "0: value in MMAR is not a valid fault address"]
274    VALUE1 = 0,
275    #[doc = "1: MMAR holds a valid fault address."]
276    VALUE2 = 1,
277}
278impl From<MMARVALID_A> for bool {
279    #[inline(always)]
280    fn from(variant: MMARVALID_A) -> Self {
281        variant as u8 != 0
282    }
283}
284#[doc = "Field `MMARVALID` reader - MemManage Fault Address Register (MMFAR) valid flag"]
285pub type MMARVALID_R = crate::BitReader<MMARVALID_A>;
286impl MMARVALID_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> MMARVALID_A {
290        match self.bits {
291            false => MMARVALID_A::VALUE1,
292            true => MMARVALID_A::VALUE2,
293        }
294    }
295    #[doc = "value in MMAR is not a valid fault address"]
296    #[inline(always)]
297    pub fn is_value1(&self) -> bool {
298        *self == MMARVALID_A::VALUE1
299    }
300    #[doc = "MMAR holds a valid fault address."]
301    #[inline(always)]
302    pub fn is_value2(&self) -> bool {
303        *self == MMARVALID_A::VALUE2
304    }
305}
306#[doc = "Field `MMARVALID` writer - MemManage Fault Address Register (MMFAR) valid flag"]
307pub type MMARVALID_W<'a, REG> = crate::BitWriter<'a, REG, MMARVALID_A>;
308impl<'a, REG> MMARVALID_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "value in MMAR is not a valid fault address"]
313    #[inline(always)]
314    pub fn value1(self) -> &'a mut crate::W<REG> {
315        self.variant(MMARVALID_A::VALUE1)
316    }
317    #[doc = "MMAR holds a valid fault address."]
318    #[inline(always)]
319    pub fn value2(self) -> &'a mut crate::W<REG> {
320        self.variant(MMARVALID_A::VALUE2)
321    }
322}
323#[doc = "Instruction bus error\n\nValue on reset: 0"]
324#[derive(Clone, Copy, Debug, PartialEq, Eq)]
325pub enum IBUSERR_A {
326    #[doc = "0: no instruction bus error"]
327    VALUE1 = 0,
328    #[doc = "1: instruction bus error."]
329    VALUE2 = 1,
330}
331impl From<IBUSERR_A> for bool {
332    #[inline(always)]
333    fn from(variant: IBUSERR_A) -> Self {
334        variant as u8 != 0
335    }
336}
337#[doc = "Field `IBUSERR` reader - Instruction bus error"]
338pub type IBUSERR_R = crate::BitReader<IBUSERR_A>;
339impl IBUSERR_R {
340    #[doc = "Get enumerated values variant"]
341    #[inline(always)]
342    pub const fn variant(&self) -> IBUSERR_A {
343        match self.bits {
344            false => IBUSERR_A::VALUE1,
345            true => IBUSERR_A::VALUE2,
346        }
347    }
348    #[doc = "no instruction bus error"]
349    #[inline(always)]
350    pub fn is_value1(&self) -> bool {
351        *self == IBUSERR_A::VALUE1
352    }
353    #[doc = "instruction bus error."]
354    #[inline(always)]
355    pub fn is_value2(&self) -> bool {
356        *self == IBUSERR_A::VALUE2
357    }
358}
359#[doc = "Field `IBUSERR` writer - Instruction bus error"]
360pub type IBUSERR_W<'a, REG> = crate::BitWriter<'a, REG, IBUSERR_A>;
361impl<'a, REG> IBUSERR_W<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364{
365    #[doc = "no instruction bus error"]
366    #[inline(always)]
367    pub fn value1(self) -> &'a mut crate::W<REG> {
368        self.variant(IBUSERR_A::VALUE1)
369    }
370    #[doc = "instruction bus error."]
371    #[inline(always)]
372    pub fn value2(self) -> &'a mut crate::W<REG> {
373        self.variant(IBUSERR_A::VALUE2)
374    }
375}
376#[doc = "Precise data bus error\n\nValue on reset: 0"]
377#[derive(Clone, Copy, Debug, PartialEq, Eq)]
378pub enum PRECISERR_A {
379    #[doc = "0: no precise data bus error"]
380    VALUE1 = 0,
381    #[doc = "1: a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault."]
382    VALUE2 = 1,
383}
384impl From<PRECISERR_A> for bool {
385    #[inline(always)]
386    fn from(variant: PRECISERR_A) -> Self {
387        variant as u8 != 0
388    }
389}
390#[doc = "Field `PRECISERR` reader - Precise data bus error"]
391pub type PRECISERR_R = crate::BitReader<PRECISERR_A>;
392impl PRECISERR_R {
393    #[doc = "Get enumerated values variant"]
394    #[inline(always)]
395    pub const fn variant(&self) -> PRECISERR_A {
396        match self.bits {
397            false => PRECISERR_A::VALUE1,
398            true => PRECISERR_A::VALUE2,
399        }
400    }
401    #[doc = "no precise data bus error"]
402    #[inline(always)]
403    pub fn is_value1(&self) -> bool {
404        *self == PRECISERR_A::VALUE1
405    }
406    #[doc = "a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault."]
407    #[inline(always)]
408    pub fn is_value2(&self) -> bool {
409        *self == PRECISERR_A::VALUE2
410    }
411}
412#[doc = "Field `PRECISERR` writer - Precise data bus error"]
413pub type PRECISERR_W<'a, REG> = crate::BitWriter<'a, REG, PRECISERR_A>;
414impl<'a, REG> PRECISERR_W<'a, REG>
415where
416    REG: crate::Writable + crate::RegisterSpec,
417{
418    #[doc = "no precise data bus error"]
419    #[inline(always)]
420    pub fn value1(self) -> &'a mut crate::W<REG> {
421        self.variant(PRECISERR_A::VALUE1)
422    }
423    #[doc = "a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault."]
424    #[inline(always)]
425    pub fn value2(self) -> &'a mut crate::W<REG> {
426        self.variant(PRECISERR_A::VALUE2)
427    }
428}
429#[doc = "Imprecise data bus error\n\nValue on reset: 0"]
430#[derive(Clone, Copy, Debug, PartialEq, Eq)]
431pub enum IMPRECISERR_A {
432    #[doc = "0: no imprecise data bus error"]
433    VALUE1 = 0,
434    #[doc = "1: a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error."]
435    VALUE2 = 1,
436}
437impl From<IMPRECISERR_A> for bool {
438    #[inline(always)]
439    fn from(variant: IMPRECISERR_A) -> Self {
440        variant as u8 != 0
441    }
442}
443#[doc = "Field `IMPRECISERR` reader - Imprecise data bus error"]
444pub type IMPRECISERR_R = crate::BitReader<IMPRECISERR_A>;
445impl IMPRECISERR_R {
446    #[doc = "Get enumerated values variant"]
447    #[inline(always)]
448    pub const fn variant(&self) -> IMPRECISERR_A {
449        match self.bits {
450            false => IMPRECISERR_A::VALUE1,
451            true => IMPRECISERR_A::VALUE2,
452        }
453    }
454    #[doc = "no imprecise data bus error"]
455    #[inline(always)]
456    pub fn is_value1(&self) -> bool {
457        *self == IMPRECISERR_A::VALUE1
458    }
459    #[doc = "a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error."]
460    #[inline(always)]
461    pub fn is_value2(&self) -> bool {
462        *self == IMPRECISERR_A::VALUE2
463    }
464}
465#[doc = "Field `IMPRECISERR` writer - Imprecise data bus error"]
466pub type IMPRECISERR_W<'a, REG> = crate::BitWriter<'a, REG, IMPRECISERR_A>;
467impl<'a, REG> IMPRECISERR_W<'a, REG>
468where
469    REG: crate::Writable + crate::RegisterSpec,
470{
471    #[doc = "no imprecise data bus error"]
472    #[inline(always)]
473    pub fn value1(self) -> &'a mut crate::W<REG> {
474        self.variant(IMPRECISERR_A::VALUE1)
475    }
476    #[doc = "a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error."]
477    #[inline(always)]
478    pub fn value2(self) -> &'a mut crate::W<REG> {
479        self.variant(IMPRECISERR_A::VALUE2)
480    }
481}
482#[doc = "BusFault on unstacking for a return from exception\n\nValue on reset: 0"]
483#[derive(Clone, Copy, Debug, PartialEq, Eq)]
484pub enum UNSTKERR_A {
485    #[doc = "0: no unstacking fault"]
486    VALUE1 = 0,
487    #[doc = "1: stacking for an exception entry has caused one or more BusFaults."]
488    VALUE2 = 1,
489}
490impl From<UNSTKERR_A> for bool {
491    #[inline(always)]
492    fn from(variant: UNSTKERR_A) -> Self {
493        variant as u8 != 0
494    }
495}
496#[doc = "Field `UNSTKERR` reader - BusFault on unstacking for a return from exception"]
497pub type UNSTKERR_R = crate::BitReader<UNSTKERR_A>;
498impl UNSTKERR_R {
499    #[doc = "Get enumerated values variant"]
500    #[inline(always)]
501    pub const fn variant(&self) -> UNSTKERR_A {
502        match self.bits {
503            false => UNSTKERR_A::VALUE1,
504            true => UNSTKERR_A::VALUE2,
505        }
506    }
507    #[doc = "no unstacking fault"]
508    #[inline(always)]
509    pub fn is_value1(&self) -> bool {
510        *self == UNSTKERR_A::VALUE1
511    }
512    #[doc = "stacking for an exception entry has caused one or more BusFaults."]
513    #[inline(always)]
514    pub fn is_value2(&self) -> bool {
515        *self == UNSTKERR_A::VALUE2
516    }
517}
518#[doc = "Field `UNSTKERR` writer - BusFault on unstacking for a return from exception"]
519pub type UNSTKERR_W<'a, REG> = crate::BitWriter<'a, REG, UNSTKERR_A>;
520impl<'a, REG> UNSTKERR_W<'a, REG>
521where
522    REG: crate::Writable + crate::RegisterSpec,
523{
524    #[doc = "no unstacking fault"]
525    #[inline(always)]
526    pub fn value1(self) -> &'a mut crate::W<REG> {
527        self.variant(UNSTKERR_A::VALUE1)
528    }
529    #[doc = "stacking for an exception entry has caused one or more BusFaults."]
530    #[inline(always)]
531    pub fn value2(self) -> &'a mut crate::W<REG> {
532        self.variant(UNSTKERR_A::VALUE2)
533    }
534}
535#[doc = "BusFault on stacking for exception entry\n\nValue on reset: 0"]
536#[derive(Clone, Copy, Debug, PartialEq, Eq)]
537pub enum STKERR_A {
538    #[doc = "0: no stacking fault"]
539    VALUE1 = 0,
540    #[doc = "1: stacking for an exception entry has caused one or more BusFaults."]
541    VALUE2 = 1,
542}
543impl From<STKERR_A> for bool {
544    #[inline(always)]
545    fn from(variant: STKERR_A) -> Self {
546        variant as u8 != 0
547    }
548}
549#[doc = "Field `STKERR` reader - BusFault on stacking for exception entry"]
550pub type STKERR_R = crate::BitReader<STKERR_A>;
551impl STKERR_R {
552    #[doc = "Get enumerated values variant"]
553    #[inline(always)]
554    pub const fn variant(&self) -> STKERR_A {
555        match self.bits {
556            false => STKERR_A::VALUE1,
557            true => STKERR_A::VALUE2,
558        }
559    }
560    #[doc = "no stacking fault"]
561    #[inline(always)]
562    pub fn is_value1(&self) -> bool {
563        *self == STKERR_A::VALUE1
564    }
565    #[doc = "stacking for an exception entry has caused one or more BusFaults."]
566    #[inline(always)]
567    pub fn is_value2(&self) -> bool {
568        *self == STKERR_A::VALUE2
569    }
570}
571#[doc = "Field `STKERR` writer - BusFault on stacking for exception entry"]
572pub type STKERR_W<'a, REG> = crate::BitWriter<'a, REG, STKERR_A>;
573impl<'a, REG> STKERR_W<'a, REG>
574where
575    REG: crate::Writable + crate::RegisterSpec,
576{
577    #[doc = "no stacking fault"]
578    #[inline(always)]
579    pub fn value1(self) -> &'a mut crate::W<REG> {
580        self.variant(STKERR_A::VALUE1)
581    }
582    #[doc = "stacking for an exception entry has caused one or more BusFaults."]
583    #[inline(always)]
584    pub fn value2(self) -> &'a mut crate::W<REG> {
585        self.variant(STKERR_A::VALUE2)
586    }
587}
588#[doc = "BusFault during floating point lazy state preservation\n\nValue on reset: 0"]
589#[derive(Clone, Copy, Debug, PartialEq, Eq)]
590pub enum LSPERR_A {
591    #[doc = "0: No bus fault occurred during floating-point lazy state preservation."]
592    VALUE1 = 0,
593    #[doc = "1: A bus fault occurred during floating-point lazy state preservation"]
594    VALUE2 = 1,
595}
596impl From<LSPERR_A> for bool {
597    #[inline(always)]
598    fn from(variant: LSPERR_A) -> Self {
599        variant as u8 != 0
600    }
601}
602#[doc = "Field `LSPERR` reader - BusFault during floating point lazy state preservation"]
603pub type LSPERR_R = crate::BitReader<LSPERR_A>;
604impl LSPERR_R {
605    #[doc = "Get enumerated values variant"]
606    #[inline(always)]
607    pub const fn variant(&self) -> LSPERR_A {
608        match self.bits {
609            false => LSPERR_A::VALUE1,
610            true => LSPERR_A::VALUE2,
611        }
612    }
613    #[doc = "No bus fault occurred during floating-point lazy state preservation."]
614    #[inline(always)]
615    pub fn is_value1(&self) -> bool {
616        *self == LSPERR_A::VALUE1
617    }
618    #[doc = "A bus fault occurred during floating-point lazy state preservation"]
619    #[inline(always)]
620    pub fn is_value2(&self) -> bool {
621        *self == LSPERR_A::VALUE2
622    }
623}
624#[doc = "Field `LSPERR` writer - BusFault during floating point lazy state preservation"]
625pub type LSPERR_W<'a, REG> = crate::BitWriter<'a, REG, LSPERR_A>;
626impl<'a, REG> LSPERR_W<'a, REG>
627where
628    REG: crate::Writable + crate::RegisterSpec,
629{
630    #[doc = "No bus fault occurred during floating-point lazy state preservation."]
631    #[inline(always)]
632    pub fn value1(self) -> &'a mut crate::W<REG> {
633        self.variant(LSPERR_A::VALUE1)
634    }
635    #[doc = "A bus fault occurred during floating-point lazy state preservation"]
636    #[inline(always)]
637    pub fn value2(self) -> &'a mut crate::W<REG> {
638        self.variant(LSPERR_A::VALUE2)
639    }
640}
641#[doc = "BusFault Address Register (BFAR) valid flag\n\nValue on reset: 0"]
642#[derive(Clone, Copy, Debug, PartialEq, Eq)]
643pub enum BFARVALID_A {
644    #[doc = "0: value in BFAR is not a valid fault address"]
645    VALUE1 = 0,
646    #[doc = "1: BFAR holds a valid fault address."]
647    VALUE2 = 1,
648}
649impl From<BFARVALID_A> for bool {
650    #[inline(always)]
651    fn from(variant: BFARVALID_A) -> Self {
652        variant as u8 != 0
653    }
654}
655#[doc = "Field `BFARVALID` reader - BusFault Address Register (BFAR) valid flag"]
656pub type BFARVALID_R = crate::BitReader<BFARVALID_A>;
657impl BFARVALID_R {
658    #[doc = "Get enumerated values variant"]
659    #[inline(always)]
660    pub const fn variant(&self) -> BFARVALID_A {
661        match self.bits {
662            false => BFARVALID_A::VALUE1,
663            true => BFARVALID_A::VALUE2,
664        }
665    }
666    #[doc = "value in BFAR is not a valid fault address"]
667    #[inline(always)]
668    pub fn is_value1(&self) -> bool {
669        *self == BFARVALID_A::VALUE1
670    }
671    #[doc = "BFAR holds a valid fault address."]
672    #[inline(always)]
673    pub fn is_value2(&self) -> bool {
674        *self == BFARVALID_A::VALUE2
675    }
676}
677#[doc = "Field `BFARVALID` writer - BusFault Address Register (BFAR) valid flag"]
678pub type BFARVALID_W<'a, REG> = crate::BitWriter<'a, REG, BFARVALID_A>;
679impl<'a, REG> BFARVALID_W<'a, REG>
680where
681    REG: crate::Writable + crate::RegisterSpec,
682{
683    #[doc = "value in BFAR is not a valid fault address"]
684    #[inline(always)]
685    pub fn value1(self) -> &'a mut crate::W<REG> {
686        self.variant(BFARVALID_A::VALUE1)
687    }
688    #[doc = "BFAR holds a valid fault address."]
689    #[inline(always)]
690    pub fn value2(self) -> &'a mut crate::W<REG> {
691        self.variant(BFARVALID_A::VALUE2)
692    }
693}
694#[doc = "Undefined instruction UsageFault\n\nValue on reset: 0"]
695#[derive(Clone, Copy, Debug, PartialEq, Eq)]
696pub enum UNDEFINSTR_A {
697    #[doc = "0: no undefined instruction UsageFault"]
698    VALUE1 = 0,
699    #[doc = "1: the processor has attempted to execute an undefined instruction."]
700    VALUE2 = 1,
701}
702impl From<UNDEFINSTR_A> for bool {
703    #[inline(always)]
704    fn from(variant: UNDEFINSTR_A) -> Self {
705        variant as u8 != 0
706    }
707}
708#[doc = "Field `UNDEFINSTR` reader - Undefined instruction UsageFault"]
709pub type UNDEFINSTR_R = crate::BitReader<UNDEFINSTR_A>;
710impl UNDEFINSTR_R {
711    #[doc = "Get enumerated values variant"]
712    #[inline(always)]
713    pub const fn variant(&self) -> UNDEFINSTR_A {
714        match self.bits {
715            false => UNDEFINSTR_A::VALUE1,
716            true => UNDEFINSTR_A::VALUE2,
717        }
718    }
719    #[doc = "no undefined instruction UsageFault"]
720    #[inline(always)]
721    pub fn is_value1(&self) -> bool {
722        *self == UNDEFINSTR_A::VALUE1
723    }
724    #[doc = "the processor has attempted to execute an undefined instruction."]
725    #[inline(always)]
726    pub fn is_value2(&self) -> bool {
727        *self == UNDEFINSTR_A::VALUE2
728    }
729}
730#[doc = "Field `UNDEFINSTR` writer - Undefined instruction UsageFault"]
731pub type UNDEFINSTR_W<'a, REG> = crate::BitWriter<'a, REG, UNDEFINSTR_A>;
732impl<'a, REG> UNDEFINSTR_W<'a, REG>
733where
734    REG: crate::Writable + crate::RegisterSpec,
735{
736    #[doc = "no undefined instruction UsageFault"]
737    #[inline(always)]
738    pub fn value1(self) -> &'a mut crate::W<REG> {
739        self.variant(UNDEFINSTR_A::VALUE1)
740    }
741    #[doc = "the processor has attempted to execute an undefined instruction."]
742    #[inline(always)]
743    pub fn value2(self) -> &'a mut crate::W<REG> {
744        self.variant(UNDEFINSTR_A::VALUE2)
745    }
746}
747#[doc = "Invalid state UsageFault\n\nValue on reset: 0"]
748#[derive(Clone, Copy, Debug, PartialEq, Eq)]
749pub enum INVSTATE_A {
750    #[doc = "0: no invalid state UsageFault"]
751    VALUE1 = 0,
752    #[doc = "1: the processor has attempted to execute an instruction that makes illegal use of the EPSR."]
753    VALUE2 = 1,
754}
755impl From<INVSTATE_A> for bool {
756    #[inline(always)]
757    fn from(variant: INVSTATE_A) -> Self {
758        variant as u8 != 0
759    }
760}
761#[doc = "Field `INVSTATE` reader - Invalid state UsageFault"]
762pub type INVSTATE_R = crate::BitReader<INVSTATE_A>;
763impl INVSTATE_R {
764    #[doc = "Get enumerated values variant"]
765    #[inline(always)]
766    pub const fn variant(&self) -> INVSTATE_A {
767        match self.bits {
768            false => INVSTATE_A::VALUE1,
769            true => INVSTATE_A::VALUE2,
770        }
771    }
772    #[doc = "no invalid state UsageFault"]
773    #[inline(always)]
774    pub fn is_value1(&self) -> bool {
775        *self == INVSTATE_A::VALUE1
776    }
777    #[doc = "the processor has attempted to execute an instruction that makes illegal use of the EPSR."]
778    #[inline(always)]
779    pub fn is_value2(&self) -> bool {
780        *self == INVSTATE_A::VALUE2
781    }
782}
783#[doc = "Field `INVSTATE` writer - Invalid state UsageFault"]
784pub type INVSTATE_W<'a, REG> = crate::BitWriter<'a, REG, INVSTATE_A>;
785impl<'a, REG> INVSTATE_W<'a, REG>
786where
787    REG: crate::Writable + crate::RegisterSpec,
788{
789    #[doc = "no invalid state UsageFault"]
790    #[inline(always)]
791    pub fn value1(self) -> &'a mut crate::W<REG> {
792        self.variant(INVSTATE_A::VALUE1)
793    }
794    #[doc = "the processor has attempted to execute an instruction that makes illegal use of the EPSR."]
795    #[inline(always)]
796    pub fn value2(self) -> &'a mut crate::W<REG> {
797        self.variant(INVSTATE_A::VALUE2)
798    }
799}
800#[doc = "Invalid PC load UsageFault\n\nValue on reset: 0"]
801#[derive(Clone, Copy, Debug, PartialEq, Eq)]
802pub enum INVPC_A {
803    #[doc = "0: no invalid PC load UsageFault"]
804    VALUE1 = 0,
805    #[doc = "1: the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value."]
806    VALUE2 = 1,
807}
808impl From<INVPC_A> for bool {
809    #[inline(always)]
810    fn from(variant: INVPC_A) -> Self {
811        variant as u8 != 0
812    }
813}
814#[doc = "Field `INVPC` reader - Invalid PC load UsageFault"]
815pub type INVPC_R = crate::BitReader<INVPC_A>;
816impl INVPC_R {
817    #[doc = "Get enumerated values variant"]
818    #[inline(always)]
819    pub const fn variant(&self) -> INVPC_A {
820        match self.bits {
821            false => INVPC_A::VALUE1,
822            true => INVPC_A::VALUE2,
823        }
824    }
825    #[doc = "no invalid PC load UsageFault"]
826    #[inline(always)]
827    pub fn is_value1(&self) -> bool {
828        *self == INVPC_A::VALUE1
829    }
830    #[doc = "the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value."]
831    #[inline(always)]
832    pub fn is_value2(&self) -> bool {
833        *self == INVPC_A::VALUE2
834    }
835}
836#[doc = "Field `INVPC` writer - Invalid PC load UsageFault"]
837pub type INVPC_W<'a, REG> = crate::BitWriter<'a, REG, INVPC_A>;
838impl<'a, REG> INVPC_W<'a, REG>
839where
840    REG: crate::Writable + crate::RegisterSpec,
841{
842    #[doc = "no invalid PC load UsageFault"]
843    #[inline(always)]
844    pub fn value1(self) -> &'a mut crate::W<REG> {
845        self.variant(INVPC_A::VALUE1)
846    }
847    #[doc = "the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value."]
848    #[inline(always)]
849    pub fn value2(self) -> &'a mut crate::W<REG> {
850        self.variant(INVPC_A::VALUE2)
851    }
852}
853#[doc = "No coprocessor UsageFault\n\nValue on reset: 0"]
854#[derive(Clone, Copy, Debug, PartialEq, Eq)]
855pub enum NOCP_A {
856    #[doc = "0: no UsageFault caused by attempting to access a coprocessor"]
857    VALUE1 = 0,
858    #[doc = "1: the processor has attempted to access a coprocessor."]
859    VALUE2 = 1,
860}
861impl From<NOCP_A> for bool {
862    #[inline(always)]
863    fn from(variant: NOCP_A) -> Self {
864        variant as u8 != 0
865    }
866}
867#[doc = "Field `NOCP` reader - No coprocessor UsageFault"]
868pub type NOCP_R = crate::BitReader<NOCP_A>;
869impl NOCP_R {
870    #[doc = "Get enumerated values variant"]
871    #[inline(always)]
872    pub const fn variant(&self) -> NOCP_A {
873        match self.bits {
874            false => NOCP_A::VALUE1,
875            true => NOCP_A::VALUE2,
876        }
877    }
878    #[doc = "no UsageFault caused by attempting to access a coprocessor"]
879    #[inline(always)]
880    pub fn is_value1(&self) -> bool {
881        *self == NOCP_A::VALUE1
882    }
883    #[doc = "the processor has attempted to access a coprocessor."]
884    #[inline(always)]
885    pub fn is_value2(&self) -> bool {
886        *self == NOCP_A::VALUE2
887    }
888}
889#[doc = "Field `NOCP` writer - No coprocessor UsageFault"]
890pub type NOCP_W<'a, REG> = crate::BitWriter<'a, REG, NOCP_A>;
891impl<'a, REG> NOCP_W<'a, REG>
892where
893    REG: crate::Writable + crate::RegisterSpec,
894{
895    #[doc = "no UsageFault caused by attempting to access a coprocessor"]
896    #[inline(always)]
897    pub fn value1(self) -> &'a mut crate::W<REG> {
898        self.variant(NOCP_A::VALUE1)
899    }
900    #[doc = "the processor has attempted to access a coprocessor."]
901    #[inline(always)]
902    pub fn value2(self) -> &'a mut crate::W<REG> {
903        self.variant(NOCP_A::VALUE2)
904    }
905}
906#[doc = "Unaligned access UsageFault\n\nValue on reset: 0"]
907#[derive(Clone, Copy, Debug, PartialEq, Eq)]
908pub enum UNALIGNED_A {
909    #[doc = "0: no unaligned access fault, or unaligned access trapping not enabled"]
910    VALUE1 = 0,
911    #[doc = "1: the processor has made an unaligned memory access."]
912    VALUE2 = 1,
913}
914impl From<UNALIGNED_A> for bool {
915    #[inline(always)]
916    fn from(variant: UNALIGNED_A) -> Self {
917        variant as u8 != 0
918    }
919}
920#[doc = "Field `UNALIGNED` reader - Unaligned access UsageFault"]
921pub type UNALIGNED_R = crate::BitReader<UNALIGNED_A>;
922impl UNALIGNED_R {
923    #[doc = "Get enumerated values variant"]
924    #[inline(always)]
925    pub const fn variant(&self) -> UNALIGNED_A {
926        match self.bits {
927            false => UNALIGNED_A::VALUE1,
928            true => UNALIGNED_A::VALUE2,
929        }
930    }
931    #[doc = "no unaligned access fault, or unaligned access trapping not enabled"]
932    #[inline(always)]
933    pub fn is_value1(&self) -> bool {
934        *self == UNALIGNED_A::VALUE1
935    }
936    #[doc = "the processor has made an unaligned memory access."]
937    #[inline(always)]
938    pub fn is_value2(&self) -> bool {
939        *self == UNALIGNED_A::VALUE2
940    }
941}
942#[doc = "Field `UNALIGNED` writer - Unaligned access UsageFault"]
943pub type UNALIGNED_W<'a, REG> = crate::BitWriter<'a, REG, UNALIGNED_A>;
944impl<'a, REG> UNALIGNED_W<'a, REG>
945where
946    REG: crate::Writable + crate::RegisterSpec,
947{
948    #[doc = "no unaligned access fault, or unaligned access trapping not enabled"]
949    #[inline(always)]
950    pub fn value1(self) -> &'a mut crate::W<REG> {
951        self.variant(UNALIGNED_A::VALUE1)
952    }
953    #[doc = "the processor has made an unaligned memory access."]
954    #[inline(always)]
955    pub fn value2(self) -> &'a mut crate::W<REG> {
956        self.variant(UNALIGNED_A::VALUE2)
957    }
958}
959#[doc = "Divide by zero UsageFault\n\nValue on reset: 0"]
960#[derive(Clone, Copy, Debug, PartialEq, Eq)]
961pub enum DIVBYZERO_A {
962    #[doc = "0: no divide by zero fault, or divide by zero trapping not enabled"]
963    VALUE1 = 0,
964    #[doc = "1: the processor has executed an SDIV or UDIV instruction with a divisor of 0"]
965    VALUE2 = 1,
966}
967impl From<DIVBYZERO_A> for bool {
968    #[inline(always)]
969    fn from(variant: DIVBYZERO_A) -> Self {
970        variant as u8 != 0
971    }
972}
973#[doc = "Field `DIVBYZERO` reader - Divide by zero UsageFault"]
974pub type DIVBYZERO_R = crate::BitReader<DIVBYZERO_A>;
975impl DIVBYZERO_R {
976    #[doc = "Get enumerated values variant"]
977    #[inline(always)]
978    pub const fn variant(&self) -> DIVBYZERO_A {
979        match self.bits {
980            false => DIVBYZERO_A::VALUE1,
981            true => DIVBYZERO_A::VALUE2,
982        }
983    }
984    #[doc = "no divide by zero fault, or divide by zero trapping not enabled"]
985    #[inline(always)]
986    pub fn is_value1(&self) -> bool {
987        *self == DIVBYZERO_A::VALUE1
988    }
989    #[doc = "the processor has executed an SDIV or UDIV instruction with a divisor of 0"]
990    #[inline(always)]
991    pub fn is_value2(&self) -> bool {
992        *self == DIVBYZERO_A::VALUE2
993    }
994}
995#[doc = "Field `DIVBYZERO` writer - Divide by zero UsageFault"]
996pub type DIVBYZERO_W<'a, REG> = crate::BitWriter<'a, REG, DIVBYZERO_A>;
997impl<'a, REG> DIVBYZERO_W<'a, REG>
998where
999    REG: crate::Writable + crate::RegisterSpec,
1000{
1001    #[doc = "no divide by zero fault, or divide by zero trapping not enabled"]
1002    #[inline(always)]
1003    pub fn value1(self) -> &'a mut crate::W<REG> {
1004        self.variant(DIVBYZERO_A::VALUE1)
1005    }
1006    #[doc = "the processor has executed an SDIV or UDIV instruction with a divisor of 0"]
1007    #[inline(always)]
1008    pub fn value2(self) -> &'a mut crate::W<REG> {
1009        self.variant(DIVBYZERO_A::VALUE2)
1010    }
1011}
1012impl R {
1013    #[doc = "Bit 0 - Instruction access violation flag"]
1014    #[inline(always)]
1015    pub fn iaccviol(&self) -> IACCVIOL_R {
1016        IACCVIOL_R::new((self.bits & 1) != 0)
1017    }
1018    #[doc = "Bit 1 - Data access violation flag"]
1019    #[inline(always)]
1020    pub fn daccviol(&self) -> DACCVIOL_R {
1021        DACCVIOL_R::new(((self.bits >> 1) & 1) != 0)
1022    }
1023    #[doc = "Bit 3 - MemManage fault on unstacking for a return from exception"]
1024    #[inline(always)]
1025    pub fn munstkerr(&self) -> MUNSTKERR_R {
1026        MUNSTKERR_R::new(((self.bits >> 3) & 1) != 0)
1027    }
1028    #[doc = "Bit 4 - MemManage fault on stacking for exception entry"]
1029    #[inline(always)]
1030    pub fn mstkerr(&self) -> MSTKERR_R {
1031        MSTKERR_R::new(((self.bits >> 4) & 1) != 0)
1032    }
1033    #[doc = "Bit 5 - MemManage fault during floating point lazy state preservation"]
1034    #[inline(always)]
1035    pub fn mlsperr(&self) -> MLSPERR_R {
1036        MLSPERR_R::new(((self.bits >> 5) & 1) != 0)
1037    }
1038    #[doc = "Bit 7 - MemManage Fault Address Register (MMFAR) valid flag"]
1039    #[inline(always)]
1040    pub fn mmarvalid(&self) -> MMARVALID_R {
1041        MMARVALID_R::new(((self.bits >> 7) & 1) != 0)
1042    }
1043    #[doc = "Bit 8 - Instruction bus error"]
1044    #[inline(always)]
1045    pub fn ibuserr(&self) -> IBUSERR_R {
1046        IBUSERR_R::new(((self.bits >> 8) & 1) != 0)
1047    }
1048    #[doc = "Bit 9 - Precise data bus error"]
1049    #[inline(always)]
1050    pub fn preciserr(&self) -> PRECISERR_R {
1051        PRECISERR_R::new(((self.bits >> 9) & 1) != 0)
1052    }
1053    #[doc = "Bit 10 - Imprecise data bus error"]
1054    #[inline(always)]
1055    pub fn impreciserr(&self) -> IMPRECISERR_R {
1056        IMPRECISERR_R::new(((self.bits >> 10) & 1) != 0)
1057    }
1058    #[doc = "Bit 11 - BusFault on unstacking for a return from exception"]
1059    #[inline(always)]
1060    pub fn unstkerr(&self) -> UNSTKERR_R {
1061        UNSTKERR_R::new(((self.bits >> 11) & 1) != 0)
1062    }
1063    #[doc = "Bit 12 - BusFault on stacking for exception entry"]
1064    #[inline(always)]
1065    pub fn stkerr(&self) -> STKERR_R {
1066        STKERR_R::new(((self.bits >> 12) & 1) != 0)
1067    }
1068    #[doc = "Bit 13 - BusFault during floating point lazy state preservation"]
1069    #[inline(always)]
1070    pub fn lsperr(&self) -> LSPERR_R {
1071        LSPERR_R::new(((self.bits >> 13) & 1) != 0)
1072    }
1073    #[doc = "Bit 15 - BusFault Address Register (BFAR) valid flag"]
1074    #[inline(always)]
1075    pub fn bfarvalid(&self) -> BFARVALID_R {
1076        BFARVALID_R::new(((self.bits >> 15) & 1) != 0)
1077    }
1078    #[doc = "Bit 16 - Undefined instruction UsageFault"]
1079    #[inline(always)]
1080    pub fn undefinstr(&self) -> UNDEFINSTR_R {
1081        UNDEFINSTR_R::new(((self.bits >> 16) & 1) != 0)
1082    }
1083    #[doc = "Bit 17 - Invalid state UsageFault"]
1084    #[inline(always)]
1085    pub fn invstate(&self) -> INVSTATE_R {
1086        INVSTATE_R::new(((self.bits >> 17) & 1) != 0)
1087    }
1088    #[doc = "Bit 18 - Invalid PC load UsageFault"]
1089    #[inline(always)]
1090    pub fn invpc(&self) -> INVPC_R {
1091        INVPC_R::new(((self.bits >> 18) & 1) != 0)
1092    }
1093    #[doc = "Bit 19 - No coprocessor UsageFault"]
1094    #[inline(always)]
1095    pub fn nocp(&self) -> NOCP_R {
1096        NOCP_R::new(((self.bits >> 19) & 1) != 0)
1097    }
1098    #[doc = "Bit 24 - Unaligned access UsageFault"]
1099    #[inline(always)]
1100    pub fn unaligned(&self) -> UNALIGNED_R {
1101        UNALIGNED_R::new(((self.bits >> 24) & 1) != 0)
1102    }
1103    #[doc = "Bit 25 - Divide by zero UsageFault"]
1104    #[inline(always)]
1105    pub fn divbyzero(&self) -> DIVBYZERO_R {
1106        DIVBYZERO_R::new(((self.bits >> 25) & 1) != 0)
1107    }
1108}
1109impl W {
1110    #[doc = "Bit 0 - Instruction access violation flag"]
1111    #[inline(always)]
1112    pub fn iaccviol(&mut self) -> IACCVIOL_W<CFSR_SPEC> {
1113        IACCVIOL_W::new(self, 0)
1114    }
1115    #[doc = "Bit 1 - Data access violation flag"]
1116    #[inline(always)]
1117    pub fn daccviol(&mut self) -> DACCVIOL_W<CFSR_SPEC> {
1118        DACCVIOL_W::new(self, 1)
1119    }
1120    #[doc = "Bit 3 - MemManage fault on unstacking for a return from exception"]
1121    #[inline(always)]
1122    pub fn munstkerr(&mut self) -> MUNSTKERR_W<CFSR_SPEC> {
1123        MUNSTKERR_W::new(self, 3)
1124    }
1125    #[doc = "Bit 4 - MemManage fault on stacking for exception entry"]
1126    #[inline(always)]
1127    pub fn mstkerr(&mut self) -> MSTKERR_W<CFSR_SPEC> {
1128        MSTKERR_W::new(self, 4)
1129    }
1130    #[doc = "Bit 5 - MemManage fault during floating point lazy state preservation"]
1131    #[inline(always)]
1132    pub fn mlsperr(&mut self) -> MLSPERR_W<CFSR_SPEC> {
1133        MLSPERR_W::new(self, 5)
1134    }
1135    #[doc = "Bit 7 - MemManage Fault Address Register (MMFAR) valid flag"]
1136    #[inline(always)]
1137    pub fn mmarvalid(&mut self) -> MMARVALID_W<CFSR_SPEC> {
1138        MMARVALID_W::new(self, 7)
1139    }
1140    #[doc = "Bit 8 - Instruction bus error"]
1141    #[inline(always)]
1142    pub fn ibuserr(&mut self) -> IBUSERR_W<CFSR_SPEC> {
1143        IBUSERR_W::new(self, 8)
1144    }
1145    #[doc = "Bit 9 - Precise data bus error"]
1146    #[inline(always)]
1147    pub fn preciserr(&mut self) -> PRECISERR_W<CFSR_SPEC> {
1148        PRECISERR_W::new(self, 9)
1149    }
1150    #[doc = "Bit 10 - Imprecise data bus error"]
1151    #[inline(always)]
1152    pub fn impreciserr(&mut self) -> IMPRECISERR_W<CFSR_SPEC> {
1153        IMPRECISERR_W::new(self, 10)
1154    }
1155    #[doc = "Bit 11 - BusFault on unstacking for a return from exception"]
1156    #[inline(always)]
1157    pub fn unstkerr(&mut self) -> UNSTKERR_W<CFSR_SPEC> {
1158        UNSTKERR_W::new(self, 11)
1159    }
1160    #[doc = "Bit 12 - BusFault on stacking for exception entry"]
1161    #[inline(always)]
1162    pub fn stkerr(&mut self) -> STKERR_W<CFSR_SPEC> {
1163        STKERR_W::new(self, 12)
1164    }
1165    #[doc = "Bit 13 - BusFault during floating point lazy state preservation"]
1166    #[inline(always)]
1167    pub fn lsperr(&mut self) -> LSPERR_W<CFSR_SPEC> {
1168        LSPERR_W::new(self, 13)
1169    }
1170    #[doc = "Bit 15 - BusFault Address Register (BFAR) valid flag"]
1171    #[inline(always)]
1172    pub fn bfarvalid(&mut self) -> BFARVALID_W<CFSR_SPEC> {
1173        BFARVALID_W::new(self, 15)
1174    }
1175    #[doc = "Bit 16 - Undefined instruction UsageFault"]
1176    #[inline(always)]
1177    pub fn undefinstr(&mut self) -> UNDEFINSTR_W<CFSR_SPEC> {
1178        UNDEFINSTR_W::new(self, 16)
1179    }
1180    #[doc = "Bit 17 - Invalid state UsageFault"]
1181    #[inline(always)]
1182    pub fn invstate(&mut self) -> INVSTATE_W<CFSR_SPEC> {
1183        INVSTATE_W::new(self, 17)
1184    }
1185    #[doc = "Bit 18 - Invalid PC load UsageFault"]
1186    #[inline(always)]
1187    pub fn invpc(&mut self) -> INVPC_W<CFSR_SPEC> {
1188        INVPC_W::new(self, 18)
1189    }
1190    #[doc = "Bit 19 - No coprocessor UsageFault"]
1191    #[inline(always)]
1192    pub fn nocp(&mut self) -> NOCP_W<CFSR_SPEC> {
1193        NOCP_W::new(self, 19)
1194    }
1195    #[doc = "Bit 24 - Unaligned access UsageFault"]
1196    #[inline(always)]
1197    pub fn unaligned(&mut self) -> UNALIGNED_W<CFSR_SPEC> {
1198        UNALIGNED_W::new(self, 24)
1199    }
1200    #[doc = "Bit 25 - Divide by zero UsageFault"]
1201    #[inline(always)]
1202    pub fn divbyzero(&mut self) -> DIVBYZERO_W<CFSR_SPEC> {
1203        DIVBYZERO_W::new(self, 25)
1204    }
1205}
1206#[doc = "Configurable Fault Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1207pub struct CFSR_SPEC;
1208impl crate::RegisterSpec for CFSR_SPEC {
1209    type Ux = u32;
1210}
1211#[doc = "`read()` method returns [`cfsr::R`](R) reader structure"]
1212impl crate::Readable for CFSR_SPEC {}
1213#[doc = "`write(|w| ..)` method takes [`cfsr::W`](W) writer structure"]
1214impl crate::Writable for CFSR_SPEC {
1215    type Safety = crate::Unsafe;
1216    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1217    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1218}
1219#[doc = "`reset()` method sets CFSR to value 0"]
1220impl crate::Resettable for CFSR_SPEC {
1221    const RESET_VALUE: u32 = 0;
1222}
xmc4300/ppb/cfsr.rs

xmc4300/ppb/
cfsr.rs
