xmc4300/ccu80_cc80/
stc.rs

1#[doc = "Register `STC` reader"]
2pub type R = crate::R<STC_SPEC>;
3#[doc = "Register `STC` writer"]
4pub type W = crate::W<STC_SPEC>;
5#[doc = "Cascaded shadow transfer enable\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum CSE_A {
8    #[doc = "0: Cascaded shadow transfer disabled"]
9    VALUE1 = 0,
10    #[doc = "1: Cascaded shadow transfer enabled"]
11    VALUE2 = 1,
12}
13impl From<CSE_A> for bool {
14    #[inline(always)]
15    fn from(variant: CSE_A) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `CSE` reader - Cascaded shadow transfer enable"]
20pub type CSE_R = crate::BitReader<CSE_A>;
21impl CSE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CSE_A {
25        match self.bits {
26            false => CSE_A::VALUE1,
27            true => CSE_A::VALUE2,
28        }
29    }
30    #[doc = "Cascaded shadow transfer disabled"]
31    #[inline(always)]
32    pub fn is_value1(&self) -> bool {
33        *self == CSE_A::VALUE1
34    }
35    #[doc = "Cascaded shadow transfer enabled"]
36    #[inline(always)]
37    pub fn is_value2(&self) -> bool {
38        *self == CSE_A::VALUE2
39    }
40}
41#[doc = "Field `CSE` writer - Cascaded shadow transfer enable"]
42pub type CSE_W<'a, REG> = crate::BitWriter<'a, REG, CSE_A>;
43impl<'a, REG> CSE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Cascaded shadow transfer disabled"]
48    #[inline(always)]
49    pub fn value1(self) -> &'a mut crate::W<REG> {
50        self.variant(CSE_A::VALUE1)
51    }
52    #[doc = "Cascaded shadow transfer enabled"]
53    #[inline(always)]
54    pub fn value2(self) -> &'a mut crate::W<REG> {
55        self.variant(CSE_A::VALUE2)
56    }
57}
58#[doc = "Shadow transfer mode\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60#[repr(u8)]
61pub enum STM_A {
62    #[doc = "0: Shadow transfer is done in Period Match and One match."]
63    VALUE1 = 0,
64    #[doc = "1: Shadow transfer is done only in Period Match."]
65    VALUE2 = 1,
66    #[doc = "2: Shadow transfer is done only in One Match."]
67    VALUE3 = 2,
68}
69impl From<STM_A> for u8 {
70    #[inline(always)]
71    fn from(variant: STM_A) -> Self {
72        variant as _
73    }
74}
75impl crate::FieldSpec for STM_A {
76    type Ux = u8;
77}
78impl crate::IsEnum for STM_A {}
79#[doc = "Field `STM` reader - Shadow transfer mode"]
80pub type STM_R = crate::FieldReader<STM_A>;
81impl STM_R {
82    #[doc = "Get enumerated values variant"]
83    #[inline(always)]
84    pub const fn variant(&self) -> Option<STM_A> {
85        match self.bits {
86            0 => Some(STM_A::VALUE1),
87            1 => Some(STM_A::VALUE2),
88            2 => Some(STM_A::VALUE3),
89            _ => None,
90        }
91    }
92    #[doc = "Shadow transfer is done in Period Match and One match."]
93    #[inline(always)]
94    pub fn is_value1(&self) -> bool {
95        *self == STM_A::VALUE1
96    }
97    #[doc = "Shadow transfer is done only in Period Match."]
98    #[inline(always)]
99    pub fn is_value2(&self) -> bool {
100        *self == STM_A::VALUE2
101    }
102    #[doc = "Shadow transfer is done only in One Match."]
103    #[inline(always)]
104    pub fn is_value3(&self) -> bool {
105        *self == STM_A::VALUE3
106    }
107}
108#[doc = "Field `STM` writer - Shadow transfer mode"]
109pub type STM_W<'a, REG> = crate::FieldWriter<'a, REG, 2, STM_A>;
110impl<'a, REG> STM_W<'a, REG>
111where
112    REG: crate::Writable + crate::RegisterSpec,
113    REG::Ux: From<u8>,
114{
115    #[doc = "Shadow transfer is done in Period Match and One match."]
116    #[inline(always)]
117    pub fn value1(self) -> &'a mut crate::W<REG> {
118        self.variant(STM_A::VALUE1)
119    }
120    #[doc = "Shadow transfer is done only in Period Match."]
121    #[inline(always)]
122    pub fn value2(self) -> &'a mut crate::W<REG> {
123        self.variant(STM_A::VALUE2)
124    }
125    #[doc = "Shadow transfer is done only in One Match."]
126    #[inline(always)]
127    pub fn value3(self) -> &'a mut crate::W<REG> {
128        self.variant(STM_A::VALUE3)
129    }
130}
131impl R {
132    #[doc = "Bit 0 - Cascaded shadow transfer enable"]
133    #[inline(always)]
134    pub fn cse(&self) -> CSE_R {
135        CSE_R::new((self.bits & 1) != 0)
136    }
137    #[doc = "Bits 1:2 - Shadow transfer mode"]
138    #[inline(always)]
139    pub fn stm(&self) -> STM_R {
140        STM_R::new(((self.bits >> 1) & 3) as u8)
141    }
142}
143impl W {
144    #[doc = "Bit 0 - Cascaded shadow transfer enable"]
145    #[inline(always)]
146    pub fn cse(&mut self) -> CSE_W<STC_SPEC> {
147        CSE_W::new(self, 0)
148    }
149    #[doc = "Bits 1:2 - Shadow transfer mode"]
150    #[inline(always)]
151    pub fn stm(&mut self) -> STM_W<STC_SPEC> {
152        STM_W::new(self, 1)
153    }
154}
155#[doc = "Shadow transfer control\n\nYou can [`read`](crate::Reg::read) this register and get [`stc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
156pub struct STC_SPEC;
157impl crate::RegisterSpec for STC_SPEC {
158    type Ux = u32;
159}
160#[doc = "`read()` method returns [`stc::R`](R) reader structure"]
161impl crate::Readable for STC_SPEC {}
162#[doc = "`write(|w| ..)` method takes [`stc::W`](W) writer structure"]
163impl crate::Writable for STC_SPEC {
164    type Safety = crate::Unsafe;
165    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
166    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
167}
168#[doc = "`reset()` method sets STC to value 0"]
169impl crate::Resettable for STC_SPEC {
170    const RESET_VALUE: u32 = 0;
171}
xmc4300/ccu80_cc80/stc.rs

xmc4300/ccu80_cc80/
stc.rs
