xmc4200/vadc/
globcfg.rs

1#[doc = "Register `GLOBCFG` reader"]
2pub type R = crate::R<GLOBCFG_SPEC>;
3#[doc = "Register `GLOBCFG` writer"]
4pub type W = crate::W<GLOBCFG_SPEC>;
5#[doc = "Divider Factor for the Analog Internal Clock\n\nValue on reset: 15"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum DIVA_A {
9    #[doc = "0: fADCI = fADC / 2"]
10    VALUE1 = 0,
11    #[doc = "1: fADCI = fADC / 2"]
12    VALUE2 = 1,
13    #[doc = "2: fADCI = fADC / 3"]
14    VALUE3 = 2,
15    #[doc = "31: fADCI = fADC / 32"]
16    VALUE4 = 31,
17}
18impl From<DIVA_A> for u8 {
19    #[inline(always)]
20    fn from(variant: DIVA_A) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for DIVA_A {
25    type Ux = u8;
26}
27impl crate::IsEnum for DIVA_A {}
28#[doc = "Field `DIVA` reader - Divider Factor for the Analog Internal Clock"]
29pub type DIVA_R = crate::FieldReader<DIVA_A>;
30impl DIVA_R {
31    #[doc = "Get enumerated values variant"]
32    #[inline(always)]
33    pub const fn variant(&self) -> Option<DIVA_A> {
34        match self.bits {
35            0 => Some(DIVA_A::VALUE1),
36            1 => Some(DIVA_A::VALUE2),
37            2 => Some(DIVA_A::VALUE3),
38            31 => Some(DIVA_A::VALUE4),
39            _ => None,
40        }
41    }
42    #[doc = "fADCI = fADC / 2"]
43    #[inline(always)]
44    pub fn is_value1(&self) -> bool {
45        *self == DIVA_A::VALUE1
46    }
47    #[doc = "fADCI = fADC / 2"]
48    #[inline(always)]
49    pub fn is_value2(&self) -> bool {
50        *self == DIVA_A::VALUE2
51    }
52    #[doc = "fADCI = fADC / 3"]
53    #[inline(always)]
54    pub fn is_value3(&self) -> bool {
55        *self == DIVA_A::VALUE3
56    }
57    #[doc = "fADCI = fADC / 32"]
58    #[inline(always)]
59    pub fn is_value4(&self) -> bool {
60        *self == DIVA_A::VALUE4
61    }
62}
63#[doc = "Field `DIVA` writer - Divider Factor for the Analog Internal Clock"]
64pub type DIVA_W<'a, REG> = crate::FieldWriter<'a, REG, 5, DIVA_A>;
65impl<'a, REG> DIVA_W<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "fADCI = fADC / 2"]
71    #[inline(always)]
72    pub fn value1(self) -> &'a mut crate::W<REG> {
73        self.variant(DIVA_A::VALUE1)
74    }
75    #[doc = "fADCI = fADC / 2"]
76    #[inline(always)]
77    pub fn value2(self) -> &'a mut crate::W<REG> {
78        self.variant(DIVA_A::VALUE2)
79    }
80    #[doc = "fADCI = fADC / 3"]
81    #[inline(always)]
82    pub fn value3(self) -> &'a mut crate::W<REG> {
83        self.variant(DIVA_A::VALUE3)
84    }
85    #[doc = "fADCI = fADC / 32"]
86    #[inline(always)]
87    pub fn value4(self) -> &'a mut crate::W<REG> {
88        self.variant(DIVA_A::VALUE4)
89    }
90}
91#[doc = "Double Clock for the MSB Conversion\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq, Eq)]
93pub enum DCMSB_A {
94    #[doc = "0: 1 clock cycles for the MSB (standard)"]
95    VALUE1 = 0,
96    #[doc = "1: 2 clock cycles for the MSB (fADCI > 20 MHz)"]
97    VALUE2 = 1,
98}
99impl From<DCMSB_A> for bool {
100    #[inline(always)]
101    fn from(variant: DCMSB_A) -> Self {
102        variant as u8 != 0
103    }
104}
105#[doc = "Field `DCMSB` reader - Double Clock for the MSB Conversion"]
106pub type DCMSB_R = crate::BitReader<DCMSB_A>;
107impl DCMSB_R {
108    #[doc = "Get enumerated values variant"]
109    #[inline(always)]
110    pub const fn variant(&self) -> DCMSB_A {
111        match self.bits {
112            false => DCMSB_A::VALUE1,
113            true => DCMSB_A::VALUE2,
114        }
115    }
116    #[doc = "1 clock cycles for the MSB (standard)"]
117    #[inline(always)]
118    pub fn is_value1(&self) -> bool {
119        *self == DCMSB_A::VALUE1
120    }
121    #[doc = "2 clock cycles for the MSB (fADCI > 20 MHz)"]
122    #[inline(always)]
123    pub fn is_value2(&self) -> bool {
124        *self == DCMSB_A::VALUE2
125    }
126}
127#[doc = "Field `DCMSB` writer - Double Clock for the MSB Conversion"]
128pub type DCMSB_W<'a, REG> = crate::BitWriter<'a, REG, DCMSB_A>;
129impl<'a, REG> DCMSB_W<'a, REG>
130where
131    REG: crate::Writable + crate::RegisterSpec,
132{
133    #[doc = "1 clock cycles for the MSB (standard)"]
134    #[inline(always)]
135    pub fn value1(self) -> &'a mut crate::W<REG> {
136        self.variant(DCMSB_A::VALUE1)
137    }
138    #[doc = "2 clock cycles for the MSB (fADCI > 20 MHz)"]
139    #[inline(always)]
140    pub fn value2(self) -> &'a mut crate::W<REG> {
141        self.variant(DCMSB_A::VALUE2)
142    }
143}
144#[doc = "Divider Factor for the Arbiter Clock\n\nValue on reset: 0"]
145#[derive(Clone, Copy, Debug, PartialEq, Eq)]
146#[repr(u8)]
147pub enum DIVD_A {
148    #[doc = "0: fADCD = fADC"]
149    VALUE1 = 0,
150    #[doc = "1: fADCD = fADC / 2"]
151    VALUE2 = 1,
152    #[doc = "2: fADCD = fADC / 3"]
153    VALUE3 = 2,
154    #[doc = "3: fADCD = fADC / 4"]
155    VALUE4 = 3,
156}
157impl From<DIVD_A> for u8 {
158    #[inline(always)]
159    fn from(variant: DIVD_A) -> Self {
160        variant as _
161    }
162}
163impl crate::FieldSpec for DIVD_A {
164    type Ux = u8;
165}
166impl crate::IsEnum for DIVD_A {}
167#[doc = "Field `DIVD` reader - Divider Factor for the Arbiter Clock"]
168pub type DIVD_R = crate::FieldReader<DIVD_A>;
169impl DIVD_R {
170    #[doc = "Get enumerated values variant"]
171    #[inline(always)]
172    pub const fn variant(&self) -> DIVD_A {
173        match self.bits {
174            0 => DIVD_A::VALUE1,
175            1 => DIVD_A::VALUE2,
176            2 => DIVD_A::VALUE3,
177            3 => DIVD_A::VALUE4,
178            _ => unreachable!(),
179        }
180    }
181    #[doc = "fADCD = fADC"]
182    #[inline(always)]
183    pub fn is_value1(&self) -> bool {
184        *self == DIVD_A::VALUE1
185    }
186    #[doc = "fADCD = fADC / 2"]
187    #[inline(always)]
188    pub fn is_value2(&self) -> bool {
189        *self == DIVD_A::VALUE2
190    }
191    #[doc = "fADCD = fADC / 3"]
192    #[inline(always)]
193    pub fn is_value3(&self) -> bool {
194        *self == DIVD_A::VALUE3
195    }
196    #[doc = "fADCD = fADC / 4"]
197    #[inline(always)]
198    pub fn is_value4(&self) -> bool {
199        *self == DIVD_A::VALUE4
200    }
201}
202#[doc = "Field `DIVD` writer - Divider Factor for the Arbiter Clock"]
203pub type DIVD_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DIVD_A, crate::Safe>;
204impl<'a, REG> DIVD_W<'a, REG>
205where
206    REG: crate::Writable + crate::RegisterSpec,
207    REG::Ux: From<u8>,
208{
209    #[doc = "fADCD = fADC"]
210    #[inline(always)]
211    pub fn value1(self) -> &'a mut crate::W<REG> {
212        self.variant(DIVD_A::VALUE1)
213    }
214    #[doc = "fADCD = fADC / 2"]
215    #[inline(always)]
216    pub fn value2(self) -> &'a mut crate::W<REG> {
217        self.variant(DIVD_A::VALUE2)
218    }
219    #[doc = "fADCD = fADC / 3"]
220    #[inline(always)]
221    pub fn value3(self) -> &'a mut crate::W<REG> {
222        self.variant(DIVD_A::VALUE3)
223    }
224    #[doc = "fADCD = fADC / 4"]
225    #[inline(always)]
226    pub fn value4(self) -> &'a mut crate::W<REG> {
227        self.variant(DIVD_A::VALUE4)
228    }
229}
230#[doc = "Write Control for Divider Parameters\n\nValue on reset: 0"]
231#[derive(Clone, Copy, Debug, PartialEq, Eq)]
232pub enum DIVWC_A {
233    #[doc = "0: No write access to divider parameters"]
234    VALUE1 = 0,
235    #[doc = "1: Bitfields DIVA, DCMSB, DIVD can be written"]
236    VALUE2 = 1,
237}
238impl From<DIVWC_A> for bool {
239    #[inline(always)]
240    fn from(variant: DIVWC_A) -> Self {
241        variant as u8 != 0
242    }
243}
244#[doc = "Field `DIVWC` writer - Write Control for Divider Parameters"]
245pub type DIVWC_W<'a, REG> = crate::BitWriter<'a, REG, DIVWC_A>;
246impl<'a, REG> DIVWC_W<'a, REG>
247where
248    REG: crate::Writable + crate::RegisterSpec,
249{
250    #[doc = "No write access to divider parameters"]
251    #[inline(always)]
252    pub fn value1(self) -> &'a mut crate::W<REG> {
253        self.variant(DIVWC_A::VALUE1)
254    }
255    #[doc = "Bitfields DIVA, DCMSB, DIVD can be written"]
256    #[inline(always)]
257    pub fn value2(self) -> &'a mut crate::W<REG> {
258        self.variant(DIVWC_A::VALUE2)
259    }
260}
261#[doc = "Disable Post-Calibration\n\nValue on reset: 0"]
262#[derive(Clone, Copy, Debug, PartialEq, Eq)]
263pub enum DPCAL0_A {
264    #[doc = "0: Automatic post-calibration after each conversion of group x"]
265    VALUE1 = 0,
266    #[doc = "1: No post-calibration"]
267    VALUE2 = 1,
268}
269impl From<DPCAL0_A> for bool {
270    #[inline(always)]
271    fn from(variant: DPCAL0_A) -> Self {
272        variant as u8 != 0
273    }
274}
275#[doc = "Field `DPCAL0` reader - Disable Post-Calibration"]
276pub type DPCAL0_R = crate::BitReader<DPCAL0_A>;
277impl DPCAL0_R {
278    #[doc = "Get enumerated values variant"]
279    #[inline(always)]
280    pub const fn variant(&self) -> DPCAL0_A {
281        match self.bits {
282            false => DPCAL0_A::VALUE1,
283            true => DPCAL0_A::VALUE2,
284        }
285    }
286    #[doc = "Automatic post-calibration after each conversion of group x"]
287    #[inline(always)]
288    pub fn is_value1(&self) -> bool {
289        *self == DPCAL0_A::VALUE1
290    }
291    #[doc = "No post-calibration"]
292    #[inline(always)]
293    pub fn is_value2(&self) -> bool {
294        *self == DPCAL0_A::VALUE2
295    }
296}
297#[doc = "Field `DPCAL0` writer - Disable Post-Calibration"]
298pub type DPCAL0_W<'a, REG> = crate::BitWriter<'a, REG, DPCAL0_A>;
299impl<'a, REG> DPCAL0_W<'a, REG>
300where
301    REG: crate::Writable + crate::RegisterSpec,
302{
303    #[doc = "Automatic post-calibration after each conversion of group x"]
304    #[inline(always)]
305    pub fn value1(self) -> &'a mut crate::W<REG> {
306        self.variant(DPCAL0_A::VALUE1)
307    }
308    #[doc = "No post-calibration"]
309    #[inline(always)]
310    pub fn value2(self) -> &'a mut crate::W<REG> {
311        self.variant(DPCAL0_A::VALUE2)
312    }
313}
314#[doc = "Disable Post-Calibration\n\nValue on reset: 0"]
315#[derive(Clone, Copy, Debug, PartialEq, Eq)]
316pub enum DPCAL1_A {
317    #[doc = "0: Automatic post-calibration after each conversion of group x"]
318    VALUE1 = 0,
319    #[doc = "1: No post-calibration"]
320    VALUE2 = 1,
321}
322impl From<DPCAL1_A> for bool {
323    #[inline(always)]
324    fn from(variant: DPCAL1_A) -> Self {
325        variant as u8 != 0
326    }
327}
328#[doc = "Field `DPCAL1` reader - Disable Post-Calibration"]
329pub type DPCAL1_R = crate::BitReader<DPCAL1_A>;
330impl DPCAL1_R {
331    #[doc = "Get enumerated values variant"]
332    #[inline(always)]
333    pub const fn variant(&self) -> DPCAL1_A {
334        match self.bits {
335            false => DPCAL1_A::VALUE1,
336            true => DPCAL1_A::VALUE2,
337        }
338    }
339    #[doc = "Automatic post-calibration after each conversion of group x"]
340    #[inline(always)]
341    pub fn is_value1(&self) -> bool {
342        *self == DPCAL1_A::VALUE1
343    }
344    #[doc = "No post-calibration"]
345    #[inline(always)]
346    pub fn is_value2(&self) -> bool {
347        *self == DPCAL1_A::VALUE2
348    }
349}
350#[doc = "Field `DPCAL1` writer - Disable Post-Calibration"]
351pub type DPCAL1_W<'a, REG> = crate::BitWriter<'a, REG, DPCAL1_A>;
352impl<'a, REG> DPCAL1_W<'a, REG>
353where
354    REG: crate::Writable + crate::RegisterSpec,
355{
356    #[doc = "Automatic post-calibration after each conversion of group x"]
357    #[inline(always)]
358    pub fn value1(self) -> &'a mut crate::W<REG> {
359        self.variant(DPCAL1_A::VALUE1)
360    }
361    #[doc = "No post-calibration"]
362    #[inline(always)]
363    pub fn value2(self) -> &'a mut crate::W<REG> {
364        self.variant(DPCAL1_A::VALUE2)
365    }
366}
367#[doc = "Disable Post-Calibration\n\nValue on reset: 0"]
368#[derive(Clone, Copy, Debug, PartialEq, Eq)]
369pub enum DPCAL2_A {
370    #[doc = "0: Automatic post-calibration after each conversion of group x"]
371    VALUE1 = 0,
372    #[doc = "1: No post-calibration"]
373    VALUE2 = 1,
374}
375impl From<DPCAL2_A> for bool {
376    #[inline(always)]
377    fn from(variant: DPCAL2_A) -> Self {
378        variant as u8 != 0
379    }
380}
381#[doc = "Field `DPCAL2` reader - Disable Post-Calibration"]
382pub type DPCAL2_R = crate::BitReader<DPCAL2_A>;
383impl DPCAL2_R {
384    #[doc = "Get enumerated values variant"]
385    #[inline(always)]
386    pub const fn variant(&self) -> DPCAL2_A {
387        match self.bits {
388            false => DPCAL2_A::VALUE1,
389            true => DPCAL2_A::VALUE2,
390        }
391    }
392    #[doc = "Automatic post-calibration after each conversion of group x"]
393    #[inline(always)]
394    pub fn is_value1(&self) -> bool {
395        *self == DPCAL2_A::VALUE1
396    }
397    #[doc = "No post-calibration"]
398    #[inline(always)]
399    pub fn is_value2(&self) -> bool {
400        *self == DPCAL2_A::VALUE2
401    }
402}
403#[doc = "Field `DPCAL2` writer - Disable Post-Calibration"]
404pub type DPCAL2_W<'a, REG> = crate::BitWriter<'a, REG, DPCAL2_A>;
405impl<'a, REG> DPCAL2_W<'a, REG>
406where
407    REG: crate::Writable + crate::RegisterSpec,
408{
409    #[doc = "Automatic post-calibration after each conversion of group x"]
410    #[inline(always)]
411    pub fn value1(self) -> &'a mut crate::W<REG> {
412        self.variant(DPCAL2_A::VALUE1)
413    }
414    #[doc = "No post-calibration"]
415    #[inline(always)]
416    pub fn value2(self) -> &'a mut crate::W<REG> {
417        self.variant(DPCAL2_A::VALUE2)
418    }
419}
420#[doc = "Disable Post-Calibration\n\nValue on reset: 0"]
421#[derive(Clone, Copy, Debug, PartialEq, Eq)]
422pub enum DPCAL3_A {
423    #[doc = "0: Automatic post-calibration after each conversion of group x"]
424    VALUE1 = 0,
425    #[doc = "1: No post-calibration"]
426    VALUE2 = 1,
427}
428impl From<DPCAL3_A> for bool {
429    #[inline(always)]
430    fn from(variant: DPCAL3_A) -> Self {
431        variant as u8 != 0
432    }
433}
434#[doc = "Field `DPCAL3` reader - Disable Post-Calibration"]
435pub type DPCAL3_R = crate::BitReader<DPCAL3_A>;
436impl DPCAL3_R {
437    #[doc = "Get enumerated values variant"]
438    #[inline(always)]
439    pub const fn variant(&self) -> DPCAL3_A {
440        match self.bits {
441            false => DPCAL3_A::VALUE1,
442            true => DPCAL3_A::VALUE2,
443        }
444    }
445    #[doc = "Automatic post-calibration after each conversion of group x"]
446    #[inline(always)]
447    pub fn is_value1(&self) -> bool {
448        *self == DPCAL3_A::VALUE1
449    }
450    #[doc = "No post-calibration"]
451    #[inline(always)]
452    pub fn is_value2(&self) -> bool {
453        *self == DPCAL3_A::VALUE2
454    }
455}
456#[doc = "Field `DPCAL3` writer - Disable Post-Calibration"]
457pub type DPCAL3_W<'a, REG> = crate::BitWriter<'a, REG, DPCAL3_A>;
458impl<'a, REG> DPCAL3_W<'a, REG>
459where
460    REG: crate::Writable + crate::RegisterSpec,
461{
462    #[doc = "Automatic post-calibration after each conversion of group x"]
463    #[inline(always)]
464    pub fn value1(self) -> &'a mut crate::W<REG> {
465        self.variant(DPCAL3_A::VALUE1)
466    }
467    #[doc = "No post-calibration"]
468    #[inline(always)]
469    pub fn value2(self) -> &'a mut crate::W<REG> {
470        self.variant(DPCAL3_A::VALUE2)
471    }
472}
473#[doc = "Start-Up Calibration\n\nValue on reset: 0"]
474#[derive(Clone, Copy, Debug, PartialEq, Eq)]
475pub enum SUCAL_A {
476    #[doc = "0: No action"]
477    VALUE1 = 0,
478    #[doc = "1: Initiate the start-up calibration phase (indication in bit GxARBCFG.CAL)"]
479    VALUE2 = 1,
480}
481impl From<SUCAL_A> for bool {
482    #[inline(always)]
483    fn from(variant: SUCAL_A) -> Self {
484        variant as u8 != 0
485    }
486}
487#[doc = "Field `SUCAL` writer - Start-Up Calibration"]
488pub type SUCAL_W<'a, REG> = crate::BitWriter<'a, REG, SUCAL_A>;
489impl<'a, REG> SUCAL_W<'a, REG>
490where
491    REG: crate::Writable + crate::RegisterSpec,
492{
493    #[doc = "No action"]
494    #[inline(always)]
495    pub fn value1(self) -> &'a mut crate::W<REG> {
496        self.variant(SUCAL_A::VALUE1)
497    }
498    #[doc = "Initiate the start-up calibration phase (indication in bit GxARBCFG.CAL)"]
499    #[inline(always)]
500    pub fn value2(self) -> &'a mut crate::W<REG> {
501        self.variant(SUCAL_A::VALUE2)
502    }
503}
504impl R {
505    #[doc = "Bits 0:4 - Divider Factor for the Analog Internal Clock"]
506    #[inline(always)]
507    pub fn diva(&self) -> DIVA_R {
508        DIVA_R::new((self.bits & 0x1f) as u8)
509    }
510    #[doc = "Bit 7 - Double Clock for the MSB Conversion"]
511    #[inline(always)]
512    pub fn dcmsb(&self) -> DCMSB_R {
513        DCMSB_R::new(((self.bits >> 7) & 1) != 0)
514    }
515    #[doc = "Bits 8:9 - Divider Factor for the Arbiter Clock"]
516    #[inline(always)]
517    pub fn divd(&self) -> DIVD_R {
518        DIVD_R::new(((self.bits >> 8) & 3) as u8)
519    }
520    #[doc = "Bit 16 - Disable Post-Calibration"]
521    #[inline(always)]
522    pub fn dpcal0(&self) -> DPCAL0_R {
523        DPCAL0_R::new(((self.bits >> 16) & 1) != 0)
524    }
525    #[doc = "Bit 17 - Disable Post-Calibration"]
526    #[inline(always)]
527    pub fn dpcal1(&self) -> DPCAL1_R {
528        DPCAL1_R::new(((self.bits >> 17) & 1) != 0)
529    }
530    #[doc = "Bit 18 - Disable Post-Calibration"]
531    #[inline(always)]
532    pub fn dpcal2(&self) -> DPCAL2_R {
533        DPCAL2_R::new(((self.bits >> 18) & 1) != 0)
534    }
535    #[doc = "Bit 19 - Disable Post-Calibration"]
536    #[inline(always)]
537    pub fn dpcal3(&self) -> DPCAL3_R {
538        DPCAL3_R::new(((self.bits >> 19) & 1) != 0)
539    }
540}
541impl W {
542    #[doc = "Bits 0:4 - Divider Factor for the Analog Internal Clock"]
543    #[inline(always)]
544    pub fn diva(&mut self) -> DIVA_W<GLOBCFG_SPEC> {
545        DIVA_W::new(self, 0)
546    }
547    #[doc = "Bit 7 - Double Clock for the MSB Conversion"]
548    #[inline(always)]
549    pub fn dcmsb(&mut self) -> DCMSB_W<GLOBCFG_SPEC> {
550        DCMSB_W::new(self, 7)
551    }
552    #[doc = "Bits 8:9 - Divider Factor for the Arbiter Clock"]
553    #[inline(always)]
554    pub fn divd(&mut self) -> DIVD_W<GLOBCFG_SPEC> {
555        DIVD_W::new(self, 8)
556    }
557    #[doc = "Bit 15 - Write Control for Divider Parameters"]
558    #[inline(always)]
559    pub fn divwc(&mut self) -> DIVWC_W<GLOBCFG_SPEC> {
560        DIVWC_W::new(self, 15)
561    }
562    #[doc = "Bit 16 - Disable Post-Calibration"]
563    #[inline(always)]
564    pub fn dpcal0(&mut self) -> DPCAL0_W<GLOBCFG_SPEC> {
565        DPCAL0_W::new(self, 16)
566    }
567    #[doc = "Bit 17 - Disable Post-Calibration"]
568    #[inline(always)]
569    pub fn dpcal1(&mut self) -> DPCAL1_W<GLOBCFG_SPEC> {
570        DPCAL1_W::new(self, 17)
571    }
572    #[doc = "Bit 18 - Disable Post-Calibration"]
573    #[inline(always)]
574    pub fn dpcal2(&mut self) -> DPCAL2_W<GLOBCFG_SPEC> {
575        DPCAL2_W::new(self, 18)
576    }
577    #[doc = "Bit 19 - Disable Post-Calibration"]
578    #[inline(always)]
579    pub fn dpcal3(&mut self) -> DPCAL3_W<GLOBCFG_SPEC> {
580        DPCAL3_W::new(self, 19)
581    }
582    #[doc = "Bit 31 - Start-Up Calibration"]
583    #[inline(always)]
584    pub fn sucal(&mut self) -> SUCAL_W<GLOBCFG_SPEC> {
585        SUCAL_W::new(self, 31)
586    }
587}
588#[doc = "Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`globcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`globcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
589pub struct GLOBCFG_SPEC;
590impl crate::RegisterSpec for GLOBCFG_SPEC {
591    type Ux = u32;
592}
593#[doc = "`read()` method returns [`globcfg::R`](R) reader structure"]
594impl crate::Readable for GLOBCFG_SPEC {}
595#[doc = "`write(|w| ..)` method takes [`globcfg::W`](W) writer structure"]
596impl crate::Writable for GLOBCFG_SPEC {
597    type Safety = crate::Unsafe;
598    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
599    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
600}
601#[doc = "`reset()` method sets GLOBCFG to value 0x0f"]
602impl crate::Resettable for GLOBCFG_SPEC {
603    const RESET_VALUE: u32 = 0x0f;
604}
xmc4200/vadc/globcfg.rs

xmc4200/vadc/
globcfg.rs
