xmc4200/usb0/
diepmsk.rs

1#[doc = "Register `DIEPMSK` reader"]
2pub type R = crate::R<DIEPMSK_SPEC>;
3#[doc = "Register `DIEPMSK` writer"]
4pub type W = crate::W<DIEPMSK_SPEC>;
5#[doc = "Field `XferComplMsk` reader - Transfer Completed Interrupt Mask"]
6pub type XFER_COMPL_MSK_R = crate::BitReader;
7#[doc = "Field `XferComplMsk` writer - Transfer Completed Interrupt Mask"]
8pub type XFER_COMPL_MSK_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `EPDisbldMsk` reader - Endpoint Disabled Interrupt Mask"]
10pub type EPDISBLD_MSK_R = crate::BitReader;
11#[doc = "Field `EPDisbldMsk` writer - Endpoint Disabled Interrupt Mask"]
12pub type EPDISBLD_MSK_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `AHBErrMsk` reader - AHB Error Mask"]
14pub type AHBERR_MSK_R = crate::BitReader;
15#[doc = "Field `AHBErrMsk` writer - AHB Error Mask"]
16pub type AHBERR_MSK_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TimeOUTMsk` reader - Timeout Condition Mask"]
18pub type TIME_OUTMSK_R = crate::BitReader;
19#[doc = "Field `TimeOUTMsk` writer - Timeout Condition Mask"]
20pub type TIME_OUTMSK_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `INTknTXFEmpMsk` reader - IN Token Received When TxFIFO Empty Mask"]
22pub type INTKN_TXFEMP_MSK_R = crate::BitReader;
23#[doc = "Field `INTknTXFEmpMsk` writer - IN Token Received When TxFIFO Empty Mask"]
24pub type INTKN_TXFEMP_MSK_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `INEPNakEffMsk` reader - IN Endpoint NAK Effective Mask"]
26pub type INEPNAK_EFF_MSK_R = crate::BitReader;
27#[doc = "Field `INEPNakEffMsk` writer - IN Endpoint NAK Effective Mask"]
28pub type INEPNAK_EFF_MSK_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TxfifoUndrnMsk` reader - Fifo Underrun Mask"]
30pub type TXFIFO_UNDRN_MSK_R = crate::BitReader;
31#[doc = "Field `TxfifoUndrnMsk` writer - Fifo Underrun Mask"]
32pub type TXFIFO_UNDRN_MSK_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `BNAInIntrMsk` reader - BNA Interrupt Mask"]
34pub type BNAIN_INTR_MSK_R = crate::BitReader;
35#[doc = "Field `BNAInIntrMsk` writer - BNA Interrupt Mask"]
36pub type BNAIN_INTR_MSK_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `NAKMsk` reader - NAK interrupt Mask"]
38pub type NAKMSK_R = crate::BitReader;
39#[doc = "Field `NAKMsk` writer - NAK interrupt Mask"]
40pub type NAKMSK_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    #[doc = "Bit 0 - Transfer Completed Interrupt Mask"]
43    #[inline(always)]
44    pub fn xfer_compl_msk(&self) -> XFER_COMPL_MSK_R {
45        XFER_COMPL_MSK_R::new((self.bits & 1) != 0)
46    }
47    #[doc = "Bit 1 - Endpoint Disabled Interrupt Mask"]
48    #[inline(always)]
49    pub fn epdisbld_msk(&self) -> EPDISBLD_MSK_R {
50        EPDISBLD_MSK_R::new(((self.bits >> 1) & 1) != 0)
51    }
52    #[doc = "Bit 2 - AHB Error Mask"]
53    #[inline(always)]
54    pub fn ahberr_msk(&self) -> AHBERR_MSK_R {
55        AHBERR_MSK_R::new(((self.bits >> 2) & 1) != 0)
56    }
57    #[doc = "Bit 3 - Timeout Condition Mask"]
58    #[inline(always)]
59    pub fn time_outmsk(&self) -> TIME_OUTMSK_R {
60        TIME_OUTMSK_R::new(((self.bits >> 3) & 1) != 0)
61    }
62    #[doc = "Bit 4 - IN Token Received When TxFIFO Empty Mask"]
63    #[inline(always)]
64    pub fn intkn_txfemp_msk(&self) -> INTKN_TXFEMP_MSK_R {
65        INTKN_TXFEMP_MSK_R::new(((self.bits >> 4) & 1) != 0)
66    }
67    #[doc = "Bit 6 - IN Endpoint NAK Effective Mask"]
68    #[inline(always)]
69    pub fn inepnak_eff_msk(&self) -> INEPNAK_EFF_MSK_R {
70        INEPNAK_EFF_MSK_R::new(((self.bits >> 6) & 1) != 0)
71    }
72    #[doc = "Bit 8 - Fifo Underrun Mask"]
73    #[inline(always)]
74    pub fn txfifo_undrn_msk(&self) -> TXFIFO_UNDRN_MSK_R {
75        TXFIFO_UNDRN_MSK_R::new(((self.bits >> 8) & 1) != 0)
76    }
77    #[doc = "Bit 9 - BNA Interrupt Mask"]
78    #[inline(always)]
79    pub fn bnain_intr_msk(&self) -> BNAIN_INTR_MSK_R {
80        BNAIN_INTR_MSK_R::new(((self.bits >> 9) & 1) != 0)
81    }
82    #[doc = "Bit 13 - NAK interrupt Mask"]
83    #[inline(always)]
84    pub fn nakmsk(&self) -> NAKMSK_R {
85        NAKMSK_R::new(((self.bits >> 13) & 1) != 0)
86    }
87}
88impl W {
89    #[doc = "Bit 0 - Transfer Completed Interrupt Mask"]
90    #[inline(always)]
91    pub fn xfer_compl_msk(&mut self) -> XFER_COMPL_MSK_W<DIEPMSK_SPEC> {
92        XFER_COMPL_MSK_W::new(self, 0)
93    }
94    #[doc = "Bit 1 - Endpoint Disabled Interrupt Mask"]
95    #[inline(always)]
96    pub fn epdisbld_msk(&mut self) -> EPDISBLD_MSK_W<DIEPMSK_SPEC> {
97        EPDISBLD_MSK_W::new(self, 1)
98    }
99    #[doc = "Bit 2 - AHB Error Mask"]
100    #[inline(always)]
101    pub fn ahberr_msk(&mut self) -> AHBERR_MSK_W<DIEPMSK_SPEC> {
102        AHBERR_MSK_W::new(self, 2)
103    }
104    #[doc = "Bit 3 - Timeout Condition Mask"]
105    #[inline(always)]
106    pub fn time_outmsk(&mut self) -> TIME_OUTMSK_W<DIEPMSK_SPEC> {
107        TIME_OUTMSK_W::new(self, 3)
108    }
109    #[doc = "Bit 4 - IN Token Received When TxFIFO Empty Mask"]
110    #[inline(always)]
111    pub fn intkn_txfemp_msk(&mut self) -> INTKN_TXFEMP_MSK_W<DIEPMSK_SPEC> {
112        INTKN_TXFEMP_MSK_W::new(self, 4)
113    }
114    #[doc = "Bit 6 - IN Endpoint NAK Effective Mask"]
115    #[inline(always)]
116    pub fn inepnak_eff_msk(&mut self) -> INEPNAK_EFF_MSK_W<DIEPMSK_SPEC> {
117        INEPNAK_EFF_MSK_W::new(self, 6)
118    }
119    #[doc = "Bit 8 - Fifo Underrun Mask"]
120    #[inline(always)]
121    pub fn txfifo_undrn_msk(&mut self) -> TXFIFO_UNDRN_MSK_W<DIEPMSK_SPEC> {
122        TXFIFO_UNDRN_MSK_W::new(self, 8)
123    }
124    #[doc = "Bit 9 - BNA Interrupt Mask"]
125    #[inline(always)]
126    pub fn bnain_intr_msk(&mut self) -> BNAIN_INTR_MSK_W<DIEPMSK_SPEC> {
127        BNAIN_INTR_MSK_W::new(self, 9)
128    }
129    #[doc = "Bit 13 - NAK interrupt Mask"]
130    #[inline(always)]
131    pub fn nakmsk(&mut self) -> NAKMSK_W<DIEPMSK_SPEC> {
132        NAKMSK_W::new(self, 13)
133    }
134}
135#[doc = "Device IN Endpoint Common Interrupt Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`diepmsk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`diepmsk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
136pub struct DIEPMSK_SPEC;
137impl crate::RegisterSpec for DIEPMSK_SPEC {
138    type Ux = u32;
139}
140#[doc = "`read()` method returns [`diepmsk::R`](R) reader structure"]
141impl crate::Readable for DIEPMSK_SPEC {}
142#[doc = "`write(|w| ..)` method takes [`diepmsk::W`](W) writer structure"]
143impl crate::Writable for DIEPMSK_SPEC {
144    type Safety = crate::Unsafe;
145    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
146    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
147}
148#[doc = "`reset()` method sets DIEPMSK to value 0"]
149impl crate::Resettable for DIEPMSK_SPEC {
150    const RESET_VALUE: u32 = 0;
151}
xmc4200/usb0/diepmsk.rs

xmc4200/usb0/
diepmsk.rs
