xmc4200/eru0/
exicon.rs

1#[doc = "Register `EXICON[%s]` reader"]
2pub type R = crate::R<EXICON_SPEC>;
3#[doc = "Register `EXICON[%s]` writer"]
4pub type W = crate::W<EXICON_SPEC>;
5#[doc = "Output Trigger Pulse Enable for ETLx\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum PE_A {
8    #[doc = "0: The trigger pulse generation is disabled"]
9    VALUE1 = 0,
10    #[doc = "1: The trigger pulse generation is enabled"]
11    VALUE2 = 1,
12}
13impl From<PE_A> for bool {
14    #[inline(always)]
15    fn from(variant: PE_A) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `PE` reader - Output Trigger Pulse Enable for ETLx"]
20pub type PE_R = crate::BitReader<PE_A>;
21impl PE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> PE_A {
25        match self.bits {
26            false => PE_A::VALUE1,
27            true => PE_A::VALUE2,
28        }
29    }
30    #[doc = "The trigger pulse generation is disabled"]
31    #[inline(always)]
32    pub fn is_value1(&self) -> bool {
33        *self == PE_A::VALUE1
34    }
35    #[doc = "The trigger pulse generation is enabled"]
36    #[inline(always)]
37    pub fn is_value2(&self) -> bool {
38        *self == PE_A::VALUE2
39    }
40}
41#[doc = "Field `PE` writer - Output Trigger Pulse Enable for ETLx"]
42pub type PE_W<'a, REG> = crate::BitWriter<'a, REG, PE_A>;
43impl<'a, REG> PE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "The trigger pulse generation is disabled"]
48    #[inline(always)]
49    pub fn value1(self) -> &'a mut crate::W<REG> {
50        self.variant(PE_A::VALUE1)
51    }
52    #[doc = "The trigger pulse generation is enabled"]
53    #[inline(always)]
54    pub fn value2(self) -> &'a mut crate::W<REG> {
55        self.variant(PE_A::VALUE2)
56    }
57}
58#[doc = "Rebuild Level Detection for Status Flag for ETLx\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum LD_A {
61    #[doc = "0: The status flag FL is not cleared by hardware and is used as \"sticky\" bit. Once set, it is not influenced by any edge until it becomes cleared by software."]
62    VALUE1 = 0,
63    #[doc = "1: The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0."]
64    VALUE2 = 1,
65}
66impl From<LD_A> for bool {
67    #[inline(always)]
68    fn from(variant: LD_A) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `LD` reader - Rebuild Level Detection for Status Flag for ETLx"]
73pub type LD_R = crate::BitReader<LD_A>;
74impl LD_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> LD_A {
78        match self.bits {
79            false => LD_A::VALUE1,
80            true => LD_A::VALUE2,
81        }
82    }
83    #[doc = "The status flag FL is not cleared by hardware and is used as \"sticky\" bit. Once set, it is not influenced by any edge until it becomes cleared by software."]
84    #[inline(always)]
85    pub fn is_value1(&self) -> bool {
86        *self == LD_A::VALUE1
87    }
88    #[doc = "The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0."]
89    #[inline(always)]
90    pub fn is_value2(&self) -> bool {
91        *self == LD_A::VALUE2
92    }
93}
94#[doc = "Field `LD` writer - Rebuild Level Detection for Status Flag for ETLx"]
95pub type LD_W<'a, REG> = crate::BitWriter<'a, REG, LD_A>;
96impl<'a, REG> LD_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "The status flag FL is not cleared by hardware and is used as \"sticky\" bit. Once set, it is not influenced by any edge until it becomes cleared by software."]
101    #[inline(always)]
102    pub fn value1(self) -> &'a mut crate::W<REG> {
103        self.variant(LD_A::VALUE1)
104    }
105    #[doc = "The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0."]
106    #[inline(always)]
107    pub fn value2(self) -> &'a mut crate::W<REG> {
108        self.variant(LD_A::VALUE2)
109    }
110}
111#[doc = "Rising Edge Detection Enable ETLx\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum RE_A {
114    #[doc = "0: A rising edge is not considered as edge event"]
115    VALUE1 = 0,
116    #[doc = "1: A rising edge is considered as edge event"]
117    VALUE2 = 1,
118}
119impl From<RE_A> for bool {
120    #[inline(always)]
121    fn from(variant: RE_A) -> Self {
122        variant as u8 != 0
123    }
124}
125#[doc = "Field `RE` reader - Rising Edge Detection Enable ETLx"]
126pub type RE_R = crate::BitReader<RE_A>;
127impl RE_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> RE_A {
131        match self.bits {
132            false => RE_A::VALUE1,
133            true => RE_A::VALUE2,
134        }
135    }
136    #[doc = "A rising edge is not considered as edge event"]
137    #[inline(always)]
138    pub fn is_value1(&self) -> bool {
139        *self == RE_A::VALUE1
140    }
141    #[doc = "A rising edge is considered as edge event"]
142    #[inline(always)]
143    pub fn is_value2(&self) -> bool {
144        *self == RE_A::VALUE2
145    }
146}
147#[doc = "Field `RE` writer - Rising Edge Detection Enable ETLx"]
148pub type RE_W<'a, REG> = crate::BitWriter<'a, REG, RE_A>;
149impl<'a, REG> RE_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "A rising edge is not considered as edge event"]
154    #[inline(always)]
155    pub fn value1(self) -> &'a mut crate::W<REG> {
156        self.variant(RE_A::VALUE1)
157    }
158    #[doc = "A rising edge is considered as edge event"]
159    #[inline(always)]
160    pub fn value2(self) -> &'a mut crate::W<REG> {
161        self.variant(RE_A::VALUE2)
162    }
163}
164#[doc = "Falling Edge Detection Enable ETLx\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum FE_A {
167    #[doc = "0: A falling edge is not considered as edge event"]
168    VALUE1 = 0,
169    #[doc = "1: A falling edge is considered as edge event"]
170    VALUE2 = 1,
171}
172impl From<FE_A> for bool {
173    #[inline(always)]
174    fn from(variant: FE_A) -> Self {
175        variant as u8 != 0
176    }
177}
178#[doc = "Field `FE` reader - Falling Edge Detection Enable ETLx"]
179pub type FE_R = crate::BitReader<FE_A>;
180impl FE_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> FE_A {
184        match self.bits {
185            false => FE_A::VALUE1,
186            true => FE_A::VALUE2,
187        }
188    }
189    #[doc = "A falling edge is not considered as edge event"]
190    #[inline(always)]
191    pub fn is_value1(&self) -> bool {
192        *self == FE_A::VALUE1
193    }
194    #[doc = "A falling edge is considered as edge event"]
195    #[inline(always)]
196    pub fn is_value2(&self) -> bool {
197        *self == FE_A::VALUE2
198    }
199}
200#[doc = "Field `FE` writer - Falling Edge Detection Enable ETLx"]
201pub type FE_W<'a, REG> = crate::BitWriter<'a, REG, FE_A>;
202impl<'a, REG> FE_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "A falling edge is not considered as edge event"]
207    #[inline(always)]
208    pub fn value1(self) -> &'a mut crate::W<REG> {
209        self.variant(FE_A::VALUE1)
210    }
211    #[doc = "A falling edge is considered as edge event"]
212    #[inline(always)]
213    pub fn value2(self) -> &'a mut crate::W<REG> {
214        self.variant(FE_A::VALUE2)
215    }
216}
217#[doc = "Output Channel Select for ETLx Output Trigger Pulse\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219#[repr(u8)]
220pub enum OCS_A {
221    #[doc = "0: Trigger pulses are sent to OGU0"]
222    VALUE1 = 0,
223    #[doc = "1: Trigger pulses are sent to OGU1"]
224    VALUE2 = 1,
225    #[doc = "2: Trigger pulses are sent to OGU2"]
226    VALUE3 = 2,
227    #[doc = "3: Trigger pulses are sent to OGU3"]
228    VALUE4 = 3,
229}
230impl From<OCS_A> for u8 {
231    #[inline(always)]
232    fn from(variant: OCS_A) -> Self {
233        variant as _
234    }
235}
236impl crate::FieldSpec for OCS_A {
237    type Ux = u8;
238}
239impl crate::IsEnum for OCS_A {}
240#[doc = "Field `OCS` reader - Output Channel Select for ETLx Output Trigger Pulse"]
241pub type OCS_R = crate::FieldReader<OCS_A>;
242impl OCS_R {
243    #[doc = "Get enumerated values variant"]
244    #[inline(always)]
245    pub const fn variant(&self) -> Option<OCS_A> {
246        match self.bits {
247            0 => Some(OCS_A::VALUE1),
248            1 => Some(OCS_A::VALUE2),
249            2 => Some(OCS_A::VALUE3),
250            3 => Some(OCS_A::VALUE4),
251            _ => None,
252        }
253    }
254    #[doc = "Trigger pulses are sent to OGU0"]
255    #[inline(always)]
256    pub fn is_value1(&self) -> bool {
257        *self == OCS_A::VALUE1
258    }
259    #[doc = "Trigger pulses are sent to OGU1"]
260    #[inline(always)]
261    pub fn is_value2(&self) -> bool {
262        *self == OCS_A::VALUE2
263    }
264    #[doc = "Trigger pulses are sent to OGU2"]
265    #[inline(always)]
266    pub fn is_value3(&self) -> bool {
267        *self == OCS_A::VALUE3
268    }
269    #[doc = "Trigger pulses are sent to OGU3"]
270    #[inline(always)]
271    pub fn is_value4(&self) -> bool {
272        *self == OCS_A::VALUE4
273    }
274}
275#[doc = "Field `OCS` writer - Output Channel Select for ETLx Output Trigger Pulse"]
276pub type OCS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, OCS_A>;
277impl<'a, REG> OCS_W<'a, REG>
278where
279    REG: crate::Writable + crate::RegisterSpec,
280    REG::Ux: From<u8>,
281{
282    #[doc = "Trigger pulses are sent to OGU0"]
283    #[inline(always)]
284    pub fn value1(self) -> &'a mut crate::W<REG> {
285        self.variant(OCS_A::VALUE1)
286    }
287    #[doc = "Trigger pulses are sent to OGU1"]
288    #[inline(always)]
289    pub fn value2(self) -> &'a mut crate::W<REG> {
290        self.variant(OCS_A::VALUE2)
291    }
292    #[doc = "Trigger pulses are sent to OGU2"]
293    #[inline(always)]
294    pub fn value3(self) -> &'a mut crate::W<REG> {
295        self.variant(OCS_A::VALUE3)
296    }
297    #[doc = "Trigger pulses are sent to OGU3"]
298    #[inline(always)]
299    pub fn value4(self) -> &'a mut crate::W<REG> {
300        self.variant(OCS_A::VALUE4)
301    }
302}
303#[doc = "Status Flag for ETLx\n\nValue on reset: 0"]
304#[derive(Clone, Copy, Debug, PartialEq, Eq)]
305pub enum FL_A {
306    #[doc = "0: The enabled edge event has not been detected"]
307    VALUE1 = 0,
308    #[doc = "1: The enabled edge event has been detected"]
309    VALUE2 = 1,
310}
311impl From<FL_A> for bool {
312    #[inline(always)]
313    fn from(variant: FL_A) -> Self {
314        variant as u8 != 0
315    }
316}
317#[doc = "Field `FL` reader - Status Flag for ETLx"]
318pub type FL_R = crate::BitReader<FL_A>;
319impl FL_R {
320    #[doc = "Get enumerated values variant"]
321    #[inline(always)]
322    pub const fn variant(&self) -> FL_A {
323        match self.bits {
324            false => FL_A::VALUE1,
325            true => FL_A::VALUE2,
326        }
327    }
328    #[doc = "The enabled edge event has not been detected"]
329    #[inline(always)]
330    pub fn is_value1(&self) -> bool {
331        *self == FL_A::VALUE1
332    }
333    #[doc = "The enabled edge event has been detected"]
334    #[inline(always)]
335    pub fn is_value2(&self) -> bool {
336        *self == FL_A::VALUE2
337    }
338}
339#[doc = "Field `FL` writer - Status Flag for ETLx"]
340pub type FL_W<'a, REG> = crate::BitWriter<'a, REG, FL_A>;
341impl<'a, REG> FL_W<'a, REG>
342where
343    REG: crate::Writable + crate::RegisterSpec,
344{
345    #[doc = "The enabled edge event has not been detected"]
346    #[inline(always)]
347    pub fn value1(self) -> &'a mut crate::W<REG> {
348        self.variant(FL_A::VALUE1)
349    }
350    #[doc = "The enabled edge event has been detected"]
351    #[inline(always)]
352    pub fn value2(self) -> &'a mut crate::W<REG> {
353        self.variant(FL_A::VALUE2)
354    }
355}
356#[doc = "Input Source Select for ERSx\n\nValue on reset: 0"]
357#[derive(Clone, Copy, Debug, PartialEq, Eq)]
358#[repr(u8)]
359pub enum SS_A {
360    #[doc = "0: Input A without additional combination"]
361    VALUE1 = 0,
362    #[doc = "1: Input B without additional combination"]
363    VALUE2 = 1,
364    #[doc = "2: Input A OR input B"]
365    VALUE3 = 2,
366    #[doc = "3: Input A AND input B"]
367    VALUE4 = 3,
368}
369impl From<SS_A> for u8 {
370    #[inline(always)]
371    fn from(variant: SS_A) -> Self {
372        variant as _
373    }
374}
375impl crate::FieldSpec for SS_A {
376    type Ux = u8;
377}
378impl crate::IsEnum for SS_A {}
379#[doc = "Field `SS` reader - Input Source Select for ERSx"]
380pub type SS_R = crate::FieldReader<SS_A>;
381impl SS_R {
382    #[doc = "Get enumerated values variant"]
383    #[inline(always)]
384    pub const fn variant(&self) -> SS_A {
385        match self.bits {
386            0 => SS_A::VALUE1,
387            1 => SS_A::VALUE2,
388            2 => SS_A::VALUE3,
389            3 => SS_A::VALUE4,
390            _ => unreachable!(),
391        }
392    }
393    #[doc = "Input A without additional combination"]
394    #[inline(always)]
395    pub fn is_value1(&self) -> bool {
396        *self == SS_A::VALUE1
397    }
398    #[doc = "Input B without additional combination"]
399    #[inline(always)]
400    pub fn is_value2(&self) -> bool {
401        *self == SS_A::VALUE2
402    }
403    #[doc = "Input A OR input B"]
404    #[inline(always)]
405    pub fn is_value3(&self) -> bool {
406        *self == SS_A::VALUE3
407    }
408    #[doc = "Input A AND input B"]
409    #[inline(always)]
410    pub fn is_value4(&self) -> bool {
411        *self == SS_A::VALUE4
412    }
413}
414#[doc = "Field `SS` writer - Input Source Select for ERSx"]
415pub type SS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SS_A, crate::Safe>;
416impl<'a, REG> SS_W<'a, REG>
417where
418    REG: crate::Writable + crate::RegisterSpec,
419    REG::Ux: From<u8>,
420{
421    #[doc = "Input A without additional combination"]
422    #[inline(always)]
423    pub fn value1(self) -> &'a mut crate::W<REG> {
424        self.variant(SS_A::VALUE1)
425    }
426    #[doc = "Input B without additional combination"]
427    #[inline(always)]
428    pub fn value2(self) -> &'a mut crate::W<REG> {
429        self.variant(SS_A::VALUE2)
430    }
431    #[doc = "Input A OR input B"]
432    #[inline(always)]
433    pub fn value3(self) -> &'a mut crate::W<REG> {
434        self.variant(SS_A::VALUE3)
435    }
436    #[doc = "Input A AND input B"]
437    #[inline(always)]
438    pub fn value4(self) -> &'a mut crate::W<REG> {
439        self.variant(SS_A::VALUE4)
440    }
441}
442#[doc = "Input A Negation Select for ERSx\n\nValue on reset: 0"]
443#[derive(Clone, Copy, Debug, PartialEq, Eq)]
444pub enum NA_A {
445    #[doc = "0: Input A is used directly"]
446    VALUE1 = 0,
447    #[doc = "1: Input A is inverted"]
448    VALUE2 = 1,
449}
450impl From<NA_A> for bool {
451    #[inline(always)]
452    fn from(variant: NA_A) -> Self {
453        variant as u8 != 0
454    }
455}
456#[doc = "Field `NA` reader - Input A Negation Select for ERSx"]
457pub type NA_R = crate::BitReader<NA_A>;
458impl NA_R {
459    #[doc = "Get enumerated values variant"]
460    #[inline(always)]
461    pub const fn variant(&self) -> NA_A {
462        match self.bits {
463            false => NA_A::VALUE1,
464            true => NA_A::VALUE2,
465        }
466    }
467    #[doc = "Input A is used directly"]
468    #[inline(always)]
469    pub fn is_value1(&self) -> bool {
470        *self == NA_A::VALUE1
471    }
472    #[doc = "Input A is inverted"]
473    #[inline(always)]
474    pub fn is_value2(&self) -> bool {
475        *self == NA_A::VALUE2
476    }
477}
478#[doc = "Field `NA` writer - Input A Negation Select for ERSx"]
479pub type NA_W<'a, REG> = crate::BitWriter<'a, REG, NA_A>;
480impl<'a, REG> NA_W<'a, REG>
481where
482    REG: crate::Writable + crate::RegisterSpec,
483{
484    #[doc = "Input A is used directly"]
485    #[inline(always)]
486    pub fn value1(self) -> &'a mut crate::W<REG> {
487        self.variant(NA_A::VALUE1)
488    }
489    #[doc = "Input A is inverted"]
490    #[inline(always)]
491    pub fn value2(self) -> &'a mut crate::W<REG> {
492        self.variant(NA_A::VALUE2)
493    }
494}
495#[doc = "Input B Negation Select for ERSx\n\nValue on reset: 0"]
496#[derive(Clone, Copy, Debug, PartialEq, Eq)]
497pub enum NB_A {
498    #[doc = "0: Input B is used directly"]
499    VALUE1 = 0,
500    #[doc = "1: Input B is inverted"]
501    VALUE2 = 1,
502}
503impl From<NB_A> for bool {
504    #[inline(always)]
505    fn from(variant: NB_A) -> Self {
506        variant as u8 != 0
507    }
508}
509#[doc = "Field `NB` reader - Input B Negation Select for ERSx"]
510pub type NB_R = crate::BitReader<NB_A>;
511impl NB_R {
512    #[doc = "Get enumerated values variant"]
513    #[inline(always)]
514    pub const fn variant(&self) -> NB_A {
515        match self.bits {
516            false => NB_A::VALUE1,
517            true => NB_A::VALUE2,
518        }
519    }
520    #[doc = "Input B is used directly"]
521    #[inline(always)]
522    pub fn is_value1(&self) -> bool {
523        *self == NB_A::VALUE1
524    }
525    #[doc = "Input B is inverted"]
526    #[inline(always)]
527    pub fn is_value2(&self) -> bool {
528        *self == NB_A::VALUE2
529    }
530}
531#[doc = "Field `NB` writer - Input B Negation Select for ERSx"]
532pub type NB_W<'a, REG> = crate::BitWriter<'a, REG, NB_A>;
533impl<'a, REG> NB_W<'a, REG>
534where
535    REG: crate::Writable + crate::RegisterSpec,
536{
537    #[doc = "Input B is used directly"]
538    #[inline(always)]
539    pub fn value1(self) -> &'a mut crate::W<REG> {
540        self.variant(NB_A::VALUE1)
541    }
542    #[doc = "Input B is inverted"]
543    #[inline(always)]
544    pub fn value2(self) -> &'a mut crate::W<REG> {
545        self.variant(NB_A::VALUE2)
546    }
547}
548impl R {
549    #[doc = "Bit 0 - Output Trigger Pulse Enable for ETLx"]
550    #[inline(always)]
551    pub fn pe(&self) -> PE_R {
552        PE_R::new((self.bits & 1) != 0)
553    }
554    #[doc = "Bit 1 - Rebuild Level Detection for Status Flag for ETLx"]
555    #[inline(always)]
556    pub fn ld(&self) -> LD_R {
557        LD_R::new(((self.bits >> 1) & 1) != 0)
558    }
559    #[doc = "Bit 2 - Rising Edge Detection Enable ETLx"]
560    #[inline(always)]
561    pub fn re(&self) -> RE_R {
562        RE_R::new(((self.bits >> 2) & 1) != 0)
563    }
564    #[doc = "Bit 3 - Falling Edge Detection Enable ETLx"]
565    #[inline(always)]
566    pub fn fe(&self) -> FE_R {
567        FE_R::new(((self.bits >> 3) & 1) != 0)
568    }
569    #[doc = "Bits 4:6 - Output Channel Select for ETLx Output Trigger Pulse"]
570    #[inline(always)]
571    pub fn ocs(&self) -> OCS_R {
572        OCS_R::new(((self.bits >> 4) & 7) as u8)
573    }
574    #[doc = "Bit 7 - Status Flag for ETLx"]
575    #[inline(always)]
576    pub fn fl(&self) -> FL_R {
577        FL_R::new(((self.bits >> 7) & 1) != 0)
578    }
579    #[doc = "Bits 8:9 - Input Source Select for ERSx"]
580    #[inline(always)]
581    pub fn ss(&self) -> SS_R {
582        SS_R::new(((self.bits >> 8) & 3) as u8)
583    }
584    #[doc = "Bit 10 - Input A Negation Select for ERSx"]
585    #[inline(always)]
586    pub fn na(&self) -> NA_R {
587        NA_R::new(((self.bits >> 10) & 1) != 0)
588    }
589    #[doc = "Bit 11 - Input B Negation Select for ERSx"]
590    #[inline(always)]
591    pub fn nb(&self) -> NB_R {
592        NB_R::new(((self.bits >> 11) & 1) != 0)
593    }
594}
595impl W {
596    #[doc = "Bit 0 - Output Trigger Pulse Enable for ETLx"]
597    #[inline(always)]
598    pub fn pe(&mut self) -> PE_W<EXICON_SPEC> {
599        PE_W::new(self, 0)
600    }
601    #[doc = "Bit 1 - Rebuild Level Detection for Status Flag for ETLx"]
602    #[inline(always)]
603    pub fn ld(&mut self) -> LD_W<EXICON_SPEC> {
604        LD_W::new(self, 1)
605    }
606    #[doc = "Bit 2 - Rising Edge Detection Enable ETLx"]
607    #[inline(always)]
608    pub fn re(&mut self) -> RE_W<EXICON_SPEC> {
609        RE_W::new(self, 2)
610    }
611    #[doc = "Bit 3 - Falling Edge Detection Enable ETLx"]
612    #[inline(always)]
613    pub fn fe(&mut self) -> FE_W<EXICON_SPEC> {
614        FE_W::new(self, 3)
615    }
616    #[doc = "Bits 4:6 - Output Channel Select for ETLx Output Trigger Pulse"]
617    #[inline(always)]
618    pub fn ocs(&mut self) -> OCS_W<EXICON_SPEC> {
619        OCS_W::new(self, 4)
620    }
621    #[doc = "Bit 7 - Status Flag for ETLx"]
622    #[inline(always)]
623    pub fn fl(&mut self) -> FL_W<EXICON_SPEC> {
624        FL_W::new(self, 7)
625    }
626    #[doc = "Bits 8:9 - Input Source Select for ERSx"]
627    #[inline(always)]
628    pub fn ss(&mut self) -> SS_W<EXICON_SPEC> {
629        SS_W::new(self, 8)
630    }
631    #[doc = "Bit 10 - Input A Negation Select for ERSx"]
632    #[inline(always)]
633    pub fn na(&mut self) -> NA_W<EXICON_SPEC> {
634        NA_W::new(self, 10)
635    }
636    #[doc = "Bit 11 - Input B Negation Select for ERSx"]
637    #[inline(always)]
638    pub fn nb(&mut self) -> NB_W<EXICON_SPEC> {
639        NB_W::new(self, 11)
640    }
641}
642#[doc = "Event Input Control\n\nYou can [`read`](crate::Reg::read) this register and get [`exicon::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exicon::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
643pub struct EXICON_SPEC;
644impl crate::RegisterSpec for EXICON_SPEC {
645    type Ux = u32;
646}
647#[doc = "`read()` method returns [`exicon::R`](R) reader structure"]
648impl crate::Readable for EXICON_SPEC {}
649#[doc = "`write(|w| ..)` method takes [`exicon::W`](W) writer structure"]
650impl crate::Writable for EXICON_SPEC {
651    type Safety = crate::Unsafe;
652    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
653    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
654}
655#[doc = "`reset()` method sets EXICON[%s]
656to value 0"]
657impl crate::Resettable for EXICON_SPEC {
658    const RESET_VALUE: u32 = 0;
659}
xmc4200/eru0/exicon.rs

xmc4200/eru0/
exicon.rs
