xmc4200/ccu40_cc40/
swr.rs

1#[doc = "Register `SWR` writer"]
2pub type W = crate::W<SWR_SPEC>;
3#[doc = "Field `RPM` writer - Period match while counting up clear"]
4pub type RPM_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `ROM` writer - One match while counting down clear"]
6pub type ROM_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `RCMU` writer - Compare match while counting up clear"]
8pub type RCMU_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RCMD` writer - Compare match while counting down clear"]
10pub type RCMD_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `RE0A` writer - Event 0 detection clear"]
12pub type RE0A_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RE1A` writer - Event 1 detection clear"]
14pub type RE1A_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `RE2A` writer - Event 2 detection clear"]
16pub type RE2A_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RTRPF` writer - Trap Flag status clear"]
18pub type RTRPF_W<'a, REG> = crate::BitWriter<'a, REG>;
19impl W {
20    #[doc = "Bit 0 - Period match while counting up clear"]
21    #[inline(always)]
22    pub fn rpm(&mut self) -> RPM_W<SWR_SPEC> {
23        RPM_W::new(self, 0)
24    }
25    #[doc = "Bit 1 - One match while counting down clear"]
26    #[inline(always)]
27    pub fn rom(&mut self) -> ROM_W<SWR_SPEC> {
28        ROM_W::new(self, 1)
29    }
30    #[doc = "Bit 2 - Compare match while counting up clear"]
31    #[inline(always)]
32    pub fn rcmu(&mut self) -> RCMU_W<SWR_SPEC> {
33        RCMU_W::new(self, 2)
34    }
35    #[doc = "Bit 3 - Compare match while counting down clear"]
36    #[inline(always)]
37    pub fn rcmd(&mut self) -> RCMD_W<SWR_SPEC> {
38        RCMD_W::new(self, 3)
39    }
40    #[doc = "Bit 8 - Event 0 detection clear"]
41    #[inline(always)]
42    pub fn re0a(&mut self) -> RE0A_W<SWR_SPEC> {
43        RE0A_W::new(self, 8)
44    }
45    #[doc = "Bit 9 - Event 1 detection clear"]
46    #[inline(always)]
47    pub fn re1a(&mut self) -> RE1A_W<SWR_SPEC> {
48        RE1A_W::new(self, 9)
49    }
50    #[doc = "Bit 10 - Event 2 detection clear"]
51    #[inline(always)]
52    pub fn re2a(&mut self) -> RE2A_W<SWR_SPEC> {
53        RE2A_W::new(self, 10)
54    }
55    #[doc = "Bit 11 - Trap Flag status clear"]
56    #[inline(always)]
57    pub fn rtrpf(&mut self) -> RTRPF_W<SWR_SPEC> {
58        RTRPF_W::new(self, 11)
59    }
60}
61#[doc = "Interrupt Status Clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct SWR_SPEC;
63impl crate::RegisterSpec for SWR_SPEC {
64    type Ux = u32;
65}
66#[doc = "`write(|w| ..)` method takes [`swr::W`](W) writer structure"]
67impl crate::Writable for SWR_SPEC {
68    type Safety = crate::Unsafe;
69    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
70    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
71}
72#[doc = "`reset()` method sets SWR to value 0"]
73impl crate::Resettable for SWR_SPEC {
74    const RESET_VALUE: u32 = 0;
75}
xmc4200/ccu40_cc40/swr.rs

xmc4200/ccu40_cc40/
swr.rs
